Clean up daisy GPIO and SPI init

Much of the board init duplicated stuff already done in gpio init, so remove it.

Powering the SPI module should be done in spi.c, not board.c.

BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; boot EC on daisy

Change-Id: I9a99eeeb971ebbf7de5b9c0548153684fbb7fff6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47469
Reviewed-by: Bill Richardson <wfrichar@chromium.org>

6 files changed, 12 insertions, 41 deletions

diff --git a/board/daisy/board.c b/board/daisy/board.c
index a0f8cb3bd3..e67ec8d3a8 100644
--- a/board/daisy/board.c
+++ b/board/daisy/board.c
@@ -135,31 +135,9 @@ int board_i2c_host_port(void)
 }
 #endif /* CONFIG_I2C_HOST_AUTO */
 
-void board_config_pre_init(void)
+void board_config_post_gpio_init(void)
 {
-	/* Enable all GPIOs clocks
-	 * TODO: more fine-grained enabling for power saving
-	 */
-	STM32_RCC_AHBENR |= 0x3f;
-	/* Required to configure external IRQ lines (SYSCFG_EXTICRn) */
-	/* FIXME: This seems to break USB download in U-Boot (?!?) */
-	STM32_RCC_APB2ENR |= 1 << 0;
-
-	/* Enable SPI */
-	STM32_RCC_APB2ENR |= (1<<12);
-
-	/*
-	 * I2C SCL/SDA on PB10-11 and PB6-7, bi-directional, no pull-up/down,
-	 * initialized as hi-Z until alt. function is set
-	 */
-	STM32_GPIO_PUPDR_OFF(GPIO_B) &= ~((3 << (11*2)) | (3 << (10*2)) |
-					(3 << (7*2)) | (3 << (6*2)));
-	STM32_GPIO_MODER_OFF(GPIO_B) &= ~((3 << (11*2)) | (3 << (10*2)) |
-					(3 << (7*2)) | (3 << (6*2)));
-	STM32_GPIO_MODER_OFF(GPIO_B) |= (1 << (11*2)) | (1 << (10*2)) |
-					(1 << (7*2)) | (1 << (6*2));
-	STM32_GPIO_OTYPER_OFF(GPIO_B) |= (1<<11) | (1<<10) | (1<<7) | (1<<6);
-	STM32_GPIO_BSRR_OFF(GPIO_B) |= (1<<11) | (1<<10) | (1<<7) | (1<<6);
+	/* I2C SCL/SDA on PB10-11 and PB6-7 */
 	gpio_set_alternate_function(GPIO_B, (1<<11) |
 					(1<<10) |
 					(1<<7)  |
@@ -167,14 +145,6 @@ void board_config_pre_init(void)
 
 	/* Select Alternate function for USART1 on pins PA9/PA10 */
 	gpio_set_alternate_function(GPIO_A, (1<<9) | (1<<10), GPIO_ALT_USART);
-
-	/* EC_INT is output, open-drain */
-	STM32_GPIO_OTYPER_OFF(GPIO_B) |= (1<<9);
-	STM32_GPIO_PUPDR_OFF(GPIO_B) &= ~(0x3 << (2*9));
-	STM32_GPIO_MODER_OFF(GPIO_B) &= ~(0x3 << (2*9));
-	STM32_GPIO_MODER_OFF(GPIO_B) |= 0x1 << (2*9);
-	/* put GPIO in Hi-Z state */
-	gpio_set_level(GPIO_EC_INT, 1);
 }
 
 void keyboard_suppress_noise(void)
diff --git a/board/daisy/board.h b/board/daisy/board.h
index dcf9fb18d1..a31f3dfa25 100644
--- a/board/daisy/board.h
+++ b/board/daisy/board.h
@@ -19,7 +19,7 @@
 #define CONFIG_ASSERT_HELP
 
 /* Optional features */
-#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_POST_GPIO_INIT
 #define CONFIG_CHIPSET_GAIA
 #define CONFIG_EXTPOWER_SNOW
 #define CONFIG_I2C
diff --git a/board/mccroskey/board.c b/board/mccroskey/board.c
index 5be787edd5..fbfac0fb7a 100644
--- a/board/mccroskey/board.c
+++ b/board/mccroskey/board.c
@@ -107,9 +107,6 @@ void board_config_pre_init(void)
 	STM32_RCC_APB2ENR |= 0x1fd;
 
 #ifdef CONFIG_SPI
-	/* Enable SPI */
-	STM32_RCC_APB2ENR |= (1<<12);
-
 	/* SPI1 on pins PA4-7 (alt. function push-pull, 10MHz) */
 	/* FIXME: Connected device SPI freq is fxo/2 in master mode, fxo/4
 	 * in slave mode. fxo ranges from 12-40MHz */
diff --git a/board/snow/board.c b/board/snow/board.c
index 81f078bad3..aaca03f7fd 100644
--- a/board/snow/board.c
+++ b/board/snow/board.c
@@ -102,9 +102,6 @@ void board_config_pre_init(void)
 	STM32_RCC_APB2ENR |= 0x1fd;
 
 #ifdef CONFIG_SPI
-	/* Enable SPI */
-	STM32_RCC_APB2ENR |= (1<<12);
-
 	/* SPI1 on pins PA4-7 (alt. function push-pull, 10MHz) */
 	val = STM32_GPIO_CRL_OFF(GPIO_A) & ~0xffff0000;
 	val |= 0x99990000;
diff --git a/chip/stm32/gpio-stm32l15x.c b/chip/stm32/gpio-stm32l15x.c
index 587abb7644..72c118cbf5 100644
--- a/chip/stm32/gpio-stm32l15x.c
+++ b/chip/stm32/gpio-stm32l15x.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,6 +34,10 @@ void gpio_pre_init(void)
 	int is_warm = 0;
 	int i;
 
+	/* Required to configure external IRQ lines (SYSCFG_EXTICRn) */
+	/* FIXME: This seems to break USB download in U-Boot (?!?) */
+	STM32_RCC_APB2ENR |= 1 << 0;
+
 	if ((STM32_RCC_AHBENR & 0x3f) == 0x3f) {
 		/* This is a warm reboot */
 		is_warm = 1;
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index ec8e078c73..bf57b0b361 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -326,6 +326,9 @@ static int spi_init(void)
 {
 	struct spi_ctlr *spi;
 
+	/* Enable clocks to SPI module */
+	STM32_RCC_APB2ENR |= 1 << 12;
+
 	/**
 	 * SPI1
 	 * PA7: SPI1_MOSI