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authorBill Richardson <wfrichar@chromium.org>2013-04-23 16:59:08 -0700
committerChromeBot <chrome-bot@google.com>2013-04-24 10:59:48 -0700
commit39b0f6ce0c86a2b8adf37624c08279bfe322686e (patch)
treee827a52c64f7960224ebd5396187158e89d587e9
parentbe2a21338cfa108075e286e8288d5384fb21045c (diff)
downloadchrome-ec-39b0f6ce0c86a2b8adf37624c08279bfe322686e.tar.gz
Specify the LM4 GPIOs to use for UART1
UART0 is the EC console, and it's consistent. UART1 is the AP console that we export via servo. It was connected to a different set of GPIOS on the BDS. BUG=chrome-os-partner:18343 TEST=build link, bds BRANCH=none Change-Id: Ib4c10fd4d2b7a8ffb4e41e216528d4760ba50de3 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48975 Reviewed-by: Randall Spangler <rspangler@chromium.org>
-rw-r--r--board/bds/board.h3
-rw-r--r--board/link/board.h3
-rw-r--r--chip/lm4/uart.c9
3 files changed, 11 insertions, 4 deletions
diff --git a/board/bds/board.h b/board/bds/board.h
index 2250ef6e06..6f4850d769 100644
--- a/board/bds/board.h
+++ b/board/bds/board.h
@@ -35,6 +35,9 @@ enum adc_channel
/* Number of I2C ports used */
#define I2C_PORTS_USED 1
+/* GPIOs for second UART port */
+#define CONFIG_UART1_GPIOS_PB0_1
+
/* GPIO signal list */
enum gpio_signal {
GPIO_RECOVERYn = 0, /* Recovery signal from DOWN button */
diff --git a/board/link/board.h b/board/link/board.h
index c7cb23f4df..5e3003f452 100644
--- a/board/link/board.h
+++ b/board/link/board.h
@@ -119,6 +119,9 @@ enum adc_channel
/* USB charge port */
#define USB_CHARGE_PORT_COUNT 2
+/* GPIOs for second UART port */
+#define CONFIG_UART1_GPIOS_PC4_5
+
/* GPIO signal definitions. */
enum gpio_signal {
/* Inputs with interrupt handlers are first for efficiency */
diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c
index bc5cadb3fe..3aebbac269 100644
--- a/chip/lm4/uart.c
+++ b/chip/lm4/uart.c
@@ -145,16 +145,17 @@ DECLARE_IRQ(LM4_IRQ_UART1, uart_1_interrupt, 2);
*/
static void configure_gpio(void)
{
-#ifdef BOARD_link
/* UART0 RX and TX are GPIO PA0:1 alternate function 1 */
gpio_set_alternate_function(LM4_GPIO_A, 0x03, 1);
+
+#if defined(CONFIG_UART1_GPIOS_PC4_5)
/* UART1 RX and TX are GPIO PC4:5 alternate function 2 */
gpio_set_alternate_function(LM4_GPIO_C, 0x30, 2);
-#else
- /* UART0 RX and TX are GPIO PA0:1 alternate function 1 */
- gpio_set_alternate_function(LM4_GPIO_A, 0x03, 1);
+#elif defined(CONFIG_UART1_GPIOS_PB0_1)
/* UART1 RX and TX are GPIO PB0:1 alternate function 1*/
gpio_set_alternate_function(LM4_GPIO_B, 0x03, 1);
+#else
+#error "Must put UART1 GPIOs somewhere"
#endif
}