bolt: add prelimnary support

The preliminary bolt support allows the board to boot
with all the necessary peripherals working except for the
following things:
- Not all board temp sensors are added.
- WLAN is not powered on because of inrush issues.
- USB power chargers are fixed to normal mode for now.

BUG=chrome-os-partner:20372
BRANCH=None
TEST=Built and booted

Change-Id: Iea7a39e812bb396e5731f212630b7fe97c164bf2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62210
Reviewed-by: Randall Spangler <rspangler@chromium.org>

7 files changed, 871 insertions, 1 deletions

diff --git a/board/bolt/board.c b/board/bolt/board.c
new file mode 100644
index 0000000000..bd7ec971e9
--- /dev/null
+++ b/board/bolt/board.c
@@ -0,0 +1,224 @@
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* EC for Bolt board configuration */
+
+#include "adc.h"
+#include "board.h"
+#include "backlight.h"
+#include "chip_temp_sensor.h"
+#include "chipset_haswell.h"
+#include "chipset_x86_common.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "lm4_adc.h"
+#include "peci.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "registers.h"
+#include "switch.h"
+#include "temp_sensor.h"
+#include "timer.h"
+#include "tmp006.h"
+#include "util.h"
+
+/* GPIO signal list.  Must match order from enum gpio_signal. */
+const struct gpio_info gpio_list[GPIO_COUNT] = {
+	/* Inputs with interrupt handlers are first for efficiency */
+	{"POWER_BUTTON_L",       LM4_GPIO_A, (1<<2), GPIO_INT_BOTH,
+	 power_button_interrupt},
+	{"LID_OPEN",             LM4_GPIO_A, (1<<3), GPIO_INT_BOTH,
+	 lid_interrupt},
+	{"AC_PRESENT",           LM4_GPIO_H, (1<<3), GPIO_INT_BOTH,
+	 extpower_interrupt},
+	{"PCH_BKLTEN",           LM4_GPIO_M, (1<<3), GPIO_INT_BOTH,
+	 backlight_interrupt},
+	{"PCH_SLP_S0_L",         LM4_GPIO_G, (1<<6), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PCH_SLP_S3_L",         LM4_GPIO_G, (1<<7), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PCH_SLP_S5_L",         LM4_GPIO_H, (1<<1), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PCH_SLP_SUS_L",        LM4_GPIO_G, (1<<3), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PCH_SUSWARN_L",        LM4_GPIO_G, (1<<2), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PP1050_PGOOD",         LM4_GPIO_H, (1<<4), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PP1350_PGOOD",         LM4_GPIO_H, (1<<6), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PP5000_PGOOD",         LM4_GPIO_N, (1<<0), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"VCORE_PGOOD",          LM4_GPIO_C, (1<<6), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PCH_EDP_VDD_EN",       LM4_GPIO_J, (1<<1), GPIO_INT_BOTH,
+	 haswell_interrupt},
+	{"RECOVERY_L",           LM4_GPIO_A, (1<<5), GPIO_PULL_UP|GPIO_INT_BOTH,
+	 switch_interrupt},
+	{"WP",                   LM4_GPIO_A, (1<<4), GPIO_INT_BOTH,
+	 switch_interrupt},
+
+	/* Other inputs */
+	{"BOARD_VERSION1",       LM4_GPIO_Q, (1<<5), GPIO_INPUT, NULL},
+	{"BOARD_VERSION2",       LM4_GPIO_Q, (1<<6), GPIO_INPUT, NULL},
+	{"BOARD_VERSION3",       LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
+	{"CPU_PGOOD",            LM4_GPIO_C, (1<<4), GPIO_INPUT, NULL},
+	{"PCH_CATERR_L",         LM4_GPIO_F, (1<<3), GPIO_INPUT, NULL},
+	{"THERMAL_DATA_READY_L", LM4_GPIO_B, (1<<0), GPIO_INPUT, NULL},
+	{"USB1_OC_L",            LM4_GPIO_E, (1<<7), GPIO_INPUT, NULL},
+	{"USB1_STATUS_L",        LM4_GPIO_E, (1<<6), GPIO_INPUT, NULL},
+	{"USB2_OC_L",            LM4_GPIO_E, (1<<0), GPIO_INPUT, NULL},
+	{"USB2_STATUS_L",        LM4_GPIO_D, (1<<7), GPIO_INPUT, NULL},
+
+	/* Outputs; all unasserted by default except for reset signals */
+	{"CPU_PROCHOT",          LM4_GPIO_B, (1<<1), GPIO_OUT_LOW, NULL},
+	{"PP1350_EN",            LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
+	{"PP3300_DSW_GATED_EN",  LM4_GPIO_J, (1<<3), GPIO_OUT_LOW, NULL},
+	{"PP3300_DX_EN",         LM4_GPIO_F, (1<<6), GPIO_OUT_LOW, NULL},
+	{"PP3300_LTE_EN",        LM4_GPIO_D, (1<<2), GPIO_OUT_LOW, NULL},
+	{"PP3300_WLAN_EN",       LM4_GPIO_J, (1<<0), GPIO_OUT_LOW, NULL},
+	{"PP1050_EN",            LM4_GPIO_C, (1<<7), GPIO_OUT_LOW, NULL},
+	{"VCORE_EN",             LM4_GPIO_C, (1<<5), GPIO_OUT_LOW, NULL},
+	{"PP5000_EN",            LM4_GPIO_H, (1<<7), GPIO_OUT_LOW, NULL},
+	{"SYS_PWROK",            LM4_GPIO_H, (1<<2), GPIO_OUT_LOW, NULL},
+	{"WLAN_OFF_L",           LM4_GPIO_J, (1<<4), GPIO_OUT_LOW, NULL},
+
+	{"ENABLE_BACKLIGHT",     LM4_GPIO_M, (1<<7), GPIO_OUT_LOW, NULL},
+	{"ENABLE_TOUCHPAD",      LM4_GPIO_N, (1<<1), GPIO_OUT_LOW, NULL},
+	{"ENTERING_RW",          LM4_GPIO_D, (1<<3), GPIO_OUT_LOW, NULL},
+	{"LIGHTBAR_RESET_L",     LM4_GPIO_J, (1<<2), GPIO_OUT_LOW, NULL},
+	{"PCH_DPWROK",           LM4_GPIO_G, (1<<0), GPIO_OUT_LOW, NULL},
+	/*
+	 * HDA_SDO is technically an output, but we need to leave it as an
+	 * input until we drive it high.  So can't use open-drain (HI_Z).
+	 */
+	{"PCH_HDA_SDO",          LM4_GPIO_G, (1<<1), GPIO_INPUT, NULL},
+	{"PCH_WAKE_L",           LM4_GPIO_F, (1<<0), GPIO_OUT_HIGH, NULL},
+	{"PCH_NMI_L",            LM4_GPIO_F, (1<<2), GPIO_ODR_HIGH, NULL},
+	{"PCH_PWRBTN_L",         LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL},
+	{"PCH_PWROK",            LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
+	/* FIXME: Why is PL6 act like it is inverted. Setting value to
+	 * 0 makes the signal high, and setting it to 1 makes the signal low. */
+	{"PCH_RCIN_L",           LM4_GPIO_L, (1<<6), GPIO_INPUT, NULL},
+	{"PCH_SYSRST_L",         LM4_GPIO_F, (1<<1), GPIO_ODR_HIGH, NULL},
+	{"PCH_SMI_L",            LM4_GPIO_F, (1<<4), GPIO_ODR_HIGH, NULL},
+	{"TOUCHSCREEN_RESET_L",  LM4_GPIO_N, (1<<7), GPIO_OUT_LOW, NULL},
+	{"EC_EDP_VDD_EN",        LM4_GPIO_J, (1<<5), GPIO_OUT_LOW, NULL},
+
+	{"LPC_CLKRUN_L",         LM4_GPIO_M, (1<<2), GPIO_ODR_HIGH, NULL},
+	{"USB1_CTL1",            LM4_GPIO_E, (1<<1), GPIO_OUT_LOW, NULL},
+	{"USB1_CTL2",            LM4_GPIO_E, (1<<2), GPIO_OUT_HIGH, NULL},
+	{"USB1_CTL3",            LM4_GPIO_E, (1<<3), GPIO_OUT_LOW, NULL},
+	{"USB1_ENABLE",          LM4_GPIO_E, (1<<4), GPIO_OUT_HIGH, NULL},
+	{"USB1_ILIM_SEL",        LM4_GPIO_E, (1<<5), GPIO_OUT_LOW, NULL},
+	{"USB2_CTL1",            LM4_GPIO_D, (1<<0), GPIO_OUT_LOW, NULL},
+	{"USB2_CTL2",            LM4_GPIO_D, (1<<1), GPIO_OUT_HIGH, NULL},
+	{"USB2_CTL3",            LM4_GPIO_D, (1<<4), GPIO_OUT_LOW, NULL},
+	{"USB2_ENABLE",          LM4_GPIO_D, (1<<5), GPIO_OUT_HIGH, NULL},
+	{"USB2_ILIM_SEL",        LM4_GPIO_D, (1<<6), GPIO_OUT_LOW, NULL},
+};
+
+/* x86 signal list.  Must match order of enum x86_signal. */
+const struct x86_signal_info x86_signal_list[X86_SIGNAL_COUNT] = {
+	{GPIO_PP5000_PGOOD,  1, "PGOOD_PP5000"},
+	{GPIO_PP1350_PGOOD,  1, "PGOOD_PP1350"},
+	{GPIO_PP1050_PGOOD,  1, "PGOOD_PP1050"},
+	{GPIO_VCORE_PGOOD,   1, "PGOOD_VCORE"},
+	{GPIO_PCH_SLP_S0_L,  1, "SLP_S0#_DEASSERTED"},
+	{GPIO_PCH_SLP_S3_L,  1, "SLP_S3#_DEASSERTED"},
+	{GPIO_PCH_SLP_S5_L,  1, "SLP_S5#_DEASSERTED"},
+	{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS#_DEASSERTED"},
+};
+
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[ADC_CH_COUNT] = {
+	/* EC internal temperature is calculated by
+	 * 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
+	 * = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
+	 */
+	{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
+	 LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
+
+	/* IOUT == ICMNT is on PE3/AIN0 */
+	/* We have 0.01-ohm resistors, and IOUT is 20X the differential
+	 * voltage, so 1000mA ==> 200mV.
+	 * ADC returns 0x000-0xFFF, which maps to 0.0-3.3V (as configured).
+	 * mA = 1000 * ADC_VALUE / ADC_READ_MAX * 3300 / 200
+	 */
+	{"ChargerCurrent", LM4_ADC_SEQ1, 33000, ADC_READ_MAX * 2, 0,
+	 LM4_AIN(0), 0x06 /* IE0 | END0 */, LM4_GPIO_E, (1<<3)},
+};
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[I2C_PORTS_USED] = {
+	/* Note: battery and charger share a port.  Only include it once in
+	 * this list so we don't double-initialize it. */
+	{"batt_chg", I2C_PORT_BATTERY,  100},
+	{"lightbar", I2C_PORT_LIGHTBAR, 400},
+	{"thermal",  I2C_PORT_THERMAL,  100},
+};
+
+
+/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
+const struct temp_sensor_t temp_sensors[TEMP_SENSOR_COUNT] = {
+/* HEY: Need correct I2C addresses and read function for external sensor */
+	{"ECInternal", TEMP_SENSOR_TYPE_BOARD, chip_temp_sensor_get_val, 0, 4},
+#ifdef CONFIG_PECI
+	{"PECI", TEMP_SENSOR_TYPE_CPU, peci_temp_sensor_get_val, 0, 2},
+#endif
+};
+
+struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 40,
+	.debounce_down_us = 6 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 1500,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = SECOND,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8  /* full set */
+	},
+};
+
+/**
+ * Configure the GPIOs for the pwm module.
+ */
+void configure_fan_gpios(void)
+{
+	/* PN2:3 alternate function 1 = channel 0 PWM/tach */
+	gpio_set_alternate_function(LM4_GPIO_N, 0x0c, 1);
+}
+
+/**
+ * Perform necessary actions on host wake events.
+ */
+void board_process_wake_events(uint32_t active_wake_events)
+{
+	uint32_t power_button_mask;
+
+	power_button_mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
+
+	/* If there are other events aside from the power button press drive
+	 * the wake pin. Otherwise ensure it is high. */
+	if (active_wake_events & ~power_button_mask)
+		gpio_set_level(GPIO_PCH_WAKE_L, 0);
+	else
+		gpio_set_level(GPIO_PCH_WAKE_L, 1);
+}
+
+/**
+ * Configure the GPIOs for the pwm module.
+ */
+void configure_kblight_gpios(void)
+{
+	/* PN6 alternate function 1 = channel 4 PWM */
+	gpio_set_alternate_function(LM4_GPIO_N, 0x40, 1);
+}
diff --git a/board/bolt/board.h b/board/bolt/board.h
new file mode 100644
index 0000000000..3f6aa36c71
--- /dev/null
+++ b/board/bolt/board.h
@@ -0,0 +1,221 @@
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Bolt mainboard */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* Debug features */
+#define CONFIG_ASSERT_HELP
+#define CONFIG_CONSOLE_CMDHELP
+#define CONFIG_PANIC_HELP
+#define CONFIG_TASK_PROFILING
+
+/* Optional features */
+#ifdef HAS_TASK_CHIPSET
+#define CONFIG_CHIPSET_X86
+#endif
+#define CONFIG_CUSTOM_KEYSCAN
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_KEYBOARD_BOARD_CONFIG
+#ifdef HAS_TASK_KEYPROTO
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#endif
+#define CONFIG_LID_SWITCH
+#define CONFIG_LPC
+#define CONFIG_ONEWIRE
+#define  ONEWIRE_BANK LM4_GPIO_F
+#define  ONEWIRE_PIN (1 << 7)
+#define CONFIG_ONEWIRE_LED
+#define CONFIG_PECI
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_WP_ACTIVE_HIGH
+
+#define CONFIG_BATTERY_SMART
+#define CONFIG_BACKLIGHT_X86
+#define CONFIG_CHARGER
+#define CONFIG_CHARGER_BQ24715
+/* 10mOhm sense resitors. */
+#define   CONFIG_CHARGER_SENSE_RESISTOR 10
+#define   CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+/* External Charger maximum current. */
+#define   CONFIG_CHARGER_INPUT_CURRENT 5000
+#define CONFIG_BATTERY_LINK
+#define CONFIG_PWM_FAN
+#define CONFIG_PWM_KBLIGHT
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_WIRELESS
+#if 0
+#define CONFIG_USB_PORT_POWER_DUMB
+#endif
+
+
+#ifndef __ASSEMBLER__
+
+/* PWM channels */
+#define FAN_CH_CPU         2  /* CPU fan */
+#define FAN_CH_KBLIGHT     4  /* Keyboard backlight */
+#define FAN_CH_BL_DISPLAY  0  /* Panel backlight (from PCH, cleaned by EC) */
+
+/* I2C ports */
+#define I2C_PORT_BATTERY 0
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_LIGHTBAR 1
+#define I2C_PORT_THERMAL 5
+/* There are only two I2C ports used because battery and charger share a port */
+#define I2C_PORTS_USED 3
+
+/* 13x8 keyboard scanner uses an entire GPIO bank for row inputs */
+#define KB_SCAN_ROW_IRQ  LM4_IRQ_GPIOK
+#define KB_SCAN_ROW_GPIO LM4_GPIO_K
+
+/* Host connects to keyboard controller module via LPC */
+#define HOST_KB_BUS_LPC
+
+/* USB ports */
+#define USB_PORT_COUNT 2
+
+/* GPIOs for second UART port */
+#define CONFIG_HOST_UART 2
+#define CONFIG_HOST_UART_IRQ LM4_IRQ_UART2
+#define CONFIG_HOST_UART2_GPIOS_PG4_5
+
+/* GPIO signal definitions. */
+enum gpio_signal {
+	/* Inputs with interrupt handlers are first for efficiency */
+	GPIO_POWER_BUTTON_L = 0,   /* Power button */
+	GPIO_LID_OPEN,             /* Lid switch */
+	GPIO_AC_PRESENT,           /* AC power present */
+	GPIO_PCH_BKLTEN,           /* Backlight enable signal from PCH */
+	GPIO_PCH_SLP_S0_L,         /* SLP_S0# signal from PCH */
+	GPIO_PCH_SLP_S3_L,         /* SLP_S3# signal from PCH */
+	GPIO_PCH_SLP_S5_L,         /* SLP_S5# signal from PCH */
+	GPIO_PCH_SLP_SUS_L,        /* SLP_SUS# signal from PCH */
+	GPIO_PCH_SUSWARN_L,        /* SUSWARN# signal from PCH */
+	GPIO_PP1050_PGOOD,         /* Power good on 1.05V */
+	GPIO_PP1350_PGOOD,         /* Power good on 1.35V (DRAM) */
+	GPIO_PP5000_PGOOD,         /* Power good on 5V */
+	GPIO_VCORE_PGOOD,          /* Power good on core VR */
+	GPIO_PCH_EDP_VDD_EN,       /* PCH wants EDP enabled */
+	GPIO_RECOVERY_L,           /* Recovery signal from servo */
+	GPIO_WP,                   /* Write protect input */
+
+	/* Other inputs */
+	GPIO_BOARD_VERSION1,       /* Board version stuffing resistor 1 */
+	GPIO_BOARD_VERSION2,       /* Board version stuffing resistor 2 */
+	GPIO_BOARD_VERSION3,       /* Board version stuffing resistor 3 */
+	GPIO_CPU_PGOOD,            /* Power good to the CPU */
+	GPIO_PCH_CATERR_L,         /* Catastrophic error signal from PCH */
+	GPIO_THERMAL_DATA_READY_L, /* From thermal sensor */
+	GPIO_USB1_OC_L,            /* USB port overcurrent warning */
+	GPIO_USB1_STATUS_L,        /* USB charger port 1 status output */
+	GPIO_USB2_OC_L,            /* USB port overcurrent warning */
+	GPIO_USB2_STATUS_L,        /* USB charger port 2 status output */
+
+	/* Outputs */
+	GPIO_CPU_PROCHOT,          /* Force CPU to think it's overheated */
+	GPIO_PP1350_EN,            /* Enable 1.35V supply */
+	GPIO_PP3300_DSW_GATED_EN,  /* Enable DSW rails */
+	GPIO_PP3300_DX_EN,         /* Enable power to lots of peripherals */
+	GPIO_PP3300_LTE_EN,        /* Enable LTE radio */
+	GPIO_PP3300_WLAN_EN,       /* Enable WiFi power */
+	GPIO_PP1050_EN,            /* Enable 1.05V regulator */
+	GPIO_VCORE_EN,             /* Stuffing option - not connected */
+	GPIO_PP5000_EN,            /* Enable 5V supply */
+	GPIO_SYS_PWROK,            /* EC thinks everything is up and ready */
+	GPIO_WLAN_OFF_L,           /* Disable WiFi radio */
+
+	GPIO_ENABLE_BACKLIGHT,     /* Enable backlight power */
+	GPIO_ENABLE_TOUCHPAD,      /* Enable touchpad power */
+	GPIO_ENTERING_RW,          /* Indicate when EC is entering RW code */
+	GPIO_LIGHTBAR_RESET_L,     /* Reset lightbar controllers */
+	GPIO_PCH_DPWROK,           /* Indicate when VccDSW is good */
+
+	GPIO_PCH_HDA_SDO,          /* HDA_SDO signal to PCH; when high, ME
+				    * ignores security descriptor */
+	GPIO_PCH_WAKE_L,           /* Wake signal from EC to PCH */
+	GPIO_PCH_NMI_L,            /* Non-maskable interrupt pin to PCH */
+	GPIO_PCH_PWRBTN_L,         /* Power button output to PCH */
+	GPIO_PCH_PWROK,            /* PWROK / APWROK signals to PCH */
+	GPIO_PCH_RCIN_L,           /* RCIN# line to PCH (for 8042 emulation) */
+	GPIO_PCH_SYS_RST_L,        /* Reset PCH resume power plane logic */
+	GPIO_PCH_SMI_L,            /* System management interrupt to PCH */
+	GPIO_TOUCHSCREEN_RESET_L,  /* Reset touch screen */
+	GPIO_EC_EDP_VDD_EN,        /* Enable EDP (passthru from PCH) */
+	GPIO_LPC_CLKRUN_L,         /* Dunno. Probably important, though. */
+
+	GPIO_USB1_CTL1,            /* USB charger port 1 CTL1 output */
+	GPIO_USB1_CTL2,            /* USB charger port 1 CTL2 output */
+	GPIO_USB1_CTL3,            /* USB charger port 1 CTL3 output */
+	GPIO_USB1_ENABLE,          /* USB charger port 1 enable */
+	GPIO_USB1_ILIM_SEL,        /* USB charger port 1 ILIM_SEL output */
+	GPIO_USB2_CTL1,            /* USB charger port 2 CTL1 output */
+	GPIO_USB2_CTL2,            /* USB charger port 2 CTL2 output */
+	GPIO_USB2_CTL3,            /* USB charger port 2 CTL3 output */
+	GPIO_USB2_ENABLE,          /* USB charger port 2 enable */
+	GPIO_USB2_ILIM_SEL,        /* USB charger port 2 ILIM_SEL output */
+
+	/* Number of GPIOs; not an actual GPIO */
+	GPIO_COUNT
+};
+
+/* x86 signal definitions */
+enum x86_signal {
+	X86_PGOOD_PP5000 = 0,
+	X86_PGOOD_PP1350,
+	X86_PGOOD_PP1050,
+	X86_PGOOD_VCORE,
+	X86_PCH_SLP_S0n_DEASSERTED,
+	X86_PCH_SLP_S3n_DEASSERTED,
+	X86_PCH_SLP_S5n_DEASSERTED,
+	X86_PCH_SLP_SUSn_DEASSERTED,
+
+	/* Number of X86 signals */
+	X86_SIGNAL_COUNT
+};
+enum adc_channel {
+	/* EC internal die temperature in degrees K. */
+	ADC_CH_EC_TEMP = 0,
+
+	/* Charger current in mA. */
+	ADC_CH_CHARGER_CURRENT,
+
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	/* HEY - need two I2C sensor values */
+
+	/* EC internal temperature sensor */
+	TEMP_SENSOR_EC_INTERNAL,
+	/* CPU die temperature via PECI */
+	TEMP_SENSOR_CPU_PECI,
+
+	TEMP_SENSOR_COUNT
+};
+
+/* HEY: The below stuff is for Link. Pick a different pin for bolt */
+/* Target value for BOOTCFG. This is set to PE2/USB1_CTL1, which has an external
+ * pullup. If this signal is pulled to ground when the EC boots, the EC will get
+ * into the boot loader and we can recover bricked EC. */
+/* #define BOOTCFG_VALUE 0x7fff88fe -- as used on slippy */
+#define BOOTCFG_VALUE 0xfffffffe  /* TODO: not configured */
+
+/* Known board versions for system_get_board_version(). */
+enum board_version {
+	BOARD_VERSION_PROTO1 = 0,
+	BOARD_VERSION_EVT = 1,
+};
+
+/* Wireless signals */
+#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
+#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN
+#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
diff --git a/board/bolt/build.mk b/board/bolt/build.mk
new file mode 100644
index 0000000000..7bbc05b261
--- /dev/null
+++ b/board/bolt/build.mk
@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+# the IC is TI Stellaris LM4
+CHIP:=lm4
+
+board-y=board.o power_sequence.o
diff --git a/board/bolt/ec.tasklist b/board/bolt/ec.tasklist
new file mode 100644
index 0000000000..35eefdfb77
--- /dev/null
+++ b/board/bolt/ec.tasklist
@@ -0,0 +1,30 @@
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' is the name of the task
+ * 'r' is the main routine of the task
+ * 'd' is an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(VBOOTHASH, vboot_hash_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(THERMAL, thermal_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/bolt/power_sequence.c b/board/bolt/power_sequence.c
new file mode 100644
index 0000000000..bca948a596
--- /dev/null
+++ b/board/bolt/power_sequence.c
@@ -0,0 +1,370 @@
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* X86 chipset power control module for Chrome EC */
+
+#include "chipset.h"
+#include "chipset_x86_common.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "registers.h"
+#include "system.h"
+#include "timer.h"
+#include "util.h"
+#include "wireless.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+
+/* Input state flags */
+#define IN_PGOOD_PP5000            X86_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_PGOOD_PP1350            X86_SIGNAL_MASK(X86_PGOOD_PP1350)
+#define IN_PGOOD_PP1050            X86_SIGNAL_MASK(X86_PGOOD_PP1050)
+#define IN_PGOOD_VCORE             X86_SIGNAL_MASK(X86_PGOOD_VCORE)
+#define IN_PCH_SLP_S0n_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S0n_DEASSERTED)
+#define IN_PCH_SLP_S3n_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S3n_DEASSERTED)
+#define IN_PCH_SLP_S5n_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S5n_DEASSERTED)
+#define IN_PCH_SLP_SUSn_DEASSERTED X86_SIGNAL_MASK(X86_PCH_SLP_SUSn_DEASSERTED)
+
+/* All always-on supplies */
+#define IN_PGOOD_ALWAYS_ON   (IN_PGOOD_PP5000)
+/* All non-core power rails */
+#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP1350 | IN_PGOOD_PP1050)
+/* All core power rails */
+#define IN_PGOOD_ALL_CORE    (IN_PGOOD_VCORE)
+/* Rails required for S3 */
+#define IN_PGOOD_S3          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_PP1350)
+/* Rails required for S0 */
+#define IN_PGOOD_S0          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
+
+/* All PM_SLP signals from PCH deasserted */
+#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3n_DEASSERTED |		\
+				  IN_PCH_SLP_S5n_DEASSERTED)
+/* All inputs in the right state for S0 */
+#define IN_ALL_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE |		\
+		   IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
+
+static int throttle_cpu;      /* Throttle CPU? */
+
+void chipset_force_shutdown(void)
+{
+	CPRINTF("[%T %s()]\n", __func__);
+
+	/*
+	 * Force x86 off. This condition will reset once the state machine
+	 * transitions to G3.
+	 */
+	gpio_set_level(GPIO_PCH_DPWROK, 0);
+}
+
+void chipset_reset(int cold_reset)
+{
+	CPRINTF("[%T %s(%d)]\n", __func__, cold_reset);
+	if (cold_reset) {
+		/*
+		 * Drop and restore PWROK.  This causes the PCH to reboot,
+		 * regardless of its after-G3 setting.  This type of reboot
+		 * causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
+		 * we actually drop power to the rest of the system (hence, a
+		 * "cold" reboot).
+		 */
+
+		/* Ignore if PWROK is already low */
+		if (gpio_get_level(GPIO_PCH_PWROK) == 0)
+			return;
+
+		/* PWROK must deassert for at least 3 RTC clocks = 91 us */
+		gpio_set_level(GPIO_PCH_PWROK, 0);
+		udelay(100);
+		gpio_set_level(GPIO_PCH_PWROK, 1);
+
+	} else {
+		/*
+		 * Send a RCIN# pulse to the PCH.  This just causes it to
+		 * assert INIT# to the CPU without dropping power or asserting
+		 * PLTRST# to reset the rest of the system.
+		 */
+
+		/*
+		 * Pulse must be at least 16 PCI clocks long = 500 ns. The gpio
+		 * pin used by the EC (PL6) does not behave in the correct
+		 * manner when configured as open drain. In order to mimic
+		 * open drain, the pin is initially configured as an input.
+		 * When it is needed to drive low, the flags are updated which
+		 * changes the pin to an output and drives the pin low.  */
+		gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_OUT_LOW);
+		udelay(10);
+		gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_INPUT);
+	}
+}
+
+void chipset_throttle_cpu(int throttle)
+{
+	/* FIXME CPRINTF("[%T %s(%d)]\n", __func__, throttle);*/
+}
+
+enum x86_state x86_chipset_init(void)
+{
+	/* Enable interrupts for our GPIOs */
+	gpio_enable_interrupt(GPIO_PCH_EDP_VDD_EN);
+
+	/*
+	 * If we're switching between images without rebooting, see if the x86
+	 * is already powered on; if so, leave it there instead of cycling
+	 * through G3.
+	 */
+	if (system_jumped_to_this_image()) {
+		if ((x86_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
+			CPRINTF("[%T x86 already in S0]\n");
+			return X86_S0;
+		} else {
+			/* Force all signals to their G3 states */
+			CPRINTF("[%T x86 forcing G3]\n");
+			gpio_set_level(GPIO_PCH_PWROK, 0);
+			gpio_set_level(GPIO_VCORE_EN, 0);
+			gpio_set_level(GPIO_PP1050_EN, 0);
+			gpio_set_level(GPIO_PP1350_EN, 0);
+			gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
+			gpio_set_level(GPIO_PP3300_DX_EN, 0);
+			gpio_set_level(GPIO_PP5000_EN, 0);
+			gpio_set_level(GPIO_PCH_DPWROK, 0);
+			wireless_enable(0);
+		}
+	}
+
+	return X86_G3;
+}
+
+enum x86_state x86_handle_state(enum x86_state state)
+{
+	switch (state) {
+	case X86_G3:
+		break;
+
+	case X86_S5:
+		if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1)
+			return X86_S5S3; /* Power up to next state */
+
+		break;
+
+	case X86_S3:
+		/*
+		 * If lid is closed; hold touchscreen in reset to cut
+		 * power usage.  If lid is open, take touchscreen out
+		 * of reset so it can wake the processor.
+		 */
+		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, lid_is_open());
+
+		/* Check for state transitions */
+		if (!x86_has_signals(IN_PGOOD_S3)) {
+			/* Required rail went away */
+			chipset_force_shutdown();
+			return X86_S3S5;
+		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
+			/* Power up to next state */
+			return X86_S3S0;
+		} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
+			/* Power down to next state */
+			return X86_S3S5;
+		}
+		break;
+
+	case X86_S0:
+		if (!x86_has_signals(IN_PGOOD_S0)) {
+			/* Required rail went away */
+			chipset_force_shutdown();
+			return X86_S0S3;
+		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
+			/* Power down to next state */
+			return X86_S0S3;
+		}
+		break;
+
+	case X86_G3S5:
+		/*
+		 * Wait 10ms after +3VALW good, since that powers VccDSW and
+		 * VccSUS.
+		 */
+		msleep(10);
+
+		/* Assert DPWROK */
+		gpio_set_level(GPIO_PCH_DPWROK, 1);
+		if (x86_wait_signals(IN_PCH_SLP_SUSn_DEASSERTED)) {
+			chipset_force_shutdown();
+			return X86_G3;
+		}
+
+		/* Enable PP5000 (5V) rail as 1.05V and 1.35V rails are
+		 * derived from 5V. */
+		gpio_set_level(GPIO_PP5000_EN, 1);
+		if (x86_wait_signals(IN_PGOOD_PP5000)) {
+			chipset_force_shutdown();
+			return X86_G3;
+		}
+
+		gpio_set_level(GPIO_PP1050_EN, 1);
+		if (x86_wait_signals(IN_PGOOD_PP1050)) {
+			chipset_force_shutdown();
+			return X86_G3;
+		}
+
+		/* Wait 5ms for SUSCLK to stabilize */
+		msleep(5);
+		return X86_S5;
+
+	case X86_S5S3:
+		/* Wait for the always-on rails to be good */
+		if (x86_wait_signals(IN_PGOOD_ALWAYS_ON)) {
+			chipset_force_shutdown();
+			return X86_S5;
+		}
+
+		/* Turn on power to RAM */
+		gpio_set_level(GPIO_PP1350_EN, 1);
+		if (x86_wait_signals(IN_PGOOD_S3)) {
+			chipset_force_shutdown();
+			return X86_S5;
+		}
+
+		/*
+		 * Take lightbar out of reset, now that +5VALW is
+		 * available and we won't leak +3VALW through the reset
+		 * line.
+		 */
+		gpio_set_level(GPIO_LIGHTBAR_RESET_L, 1);
+
+		/*
+		 * Enable touchpad power so it can wake the system from
+		 * suspend.
+		 */
+		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_STARTUP);
+		return X86_S3;
+
+	case X86_S3S0:
+		/* Turn on power rails */
+		gpio_set_level(GPIO_PP3300_DX_EN, 1);
+		gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
+
+		/* Enable wireless -- FIXME: not really*/
+		wireless_enable(0 /* EC_WIRELESS_SWITCH_ALL */);
+
+		/*
+		 * Make sure touchscreen is out if reset (even if the
+		 * lid is still closed); it may have been turned off if
+		 * the lid was closed in S3.
+		 */
+		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
+
+		/* Wait for non-core power rails good */
+		if (x86_wait_signals(IN_PGOOD_S0)) {
+			chipset_force_shutdown();
+			wireless_enable(0);
+			gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
+			gpio_set_level(GPIO_PP3300_DX_EN, 0);
+			gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
+			return X86_S3;
+		}
+
+		/*
+		 * Enable +CPU_CORE.  The CPU itself will request the supplies
+		 * when it's ready.
+		 */
+		gpio_set_level(GPIO_VCORE_EN, 1);
+
+		/* Call hooks now that rails are up */
+		hook_notify(HOOK_CHIPSET_RESUME);
+
+		/* Wait 99ms after all voltages good */
+		msleep(99);
+
+		/*
+		 * Throttle CPU if necessary.  This should only be asserted
+		 * when +VCCP is powered (it is by now).
+		 */
+		gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
+
+		/* Set PCH_PWROK */
+		gpio_set_level(GPIO_PCH_PWROK, 1);
+		gpio_set_level(GPIO_SYS_PWROK, 1);
+		return X86_S0;
+
+	case X86_S0S3:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+
+		/* Clear PCH_PWROK */
+		gpio_set_level(GPIO_SYS_PWROK, 0);
+		gpio_set_level(GPIO_PCH_PWROK, 0);
+
+		/* Wait 40ns */
+		udelay(1);
+
+		/* Disable +CPU_CORE */
+		gpio_set_level(GPIO_VCORE_EN, 0);
+
+		/* Disable wireless */
+		wireless_enable(0);
+
+		/*
+		 * Deassert prochot since CPU is off and we're about to drop
+		 * +VCCP.
+		 */
+		gpio_set_level(GPIO_CPU_PROCHOT, 0);
+
+		/* Turn off power rails */
+		gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
+		gpio_set_level(GPIO_PP3300_DX_EN, 0);
+		gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
+		return X86_S3;
+
+	case X86_S3S5:
+		/* Call hooks before we remove power rails */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+
+		/* Disable touchpad power */
+		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
+
+		/* Turn off power to RAM */
+		gpio_set_level(GPIO_PP1350_EN, 0);
+
+		/*
+		 * Put touchscreen and lightbar in reset, so we won't
+		 * leak +3VALW through the reset line to chips powered
+		 * by +5VALW.
+		 *
+		 * (Note that we're no longer powering down +5VALW due
+		 * to crosbug.com/p/16600, but to minimize side effects
+		 * of that change we'll still reset these components in
+		 * S5.)
+		 */
+		gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
+		gpio_set_level(GPIO_LIGHTBAR_RESET_L, 0);
+
+		return X86_S5;
+
+	case X86_S5G3:
+		/* Deassert DPWROK */
+		gpio_set_level(GPIO_PCH_DPWROK, 0);
+		gpio_set_level(GPIO_PP1050_EN, 0);
+		/* Disable PP5000 (5V) rail. */
+		gpio_set_level(GPIO_PP5000_EN, 0);
+		return X86_G3;
+	}
+
+	return state;
+}
+
+void haswell_interrupt(enum gpio_signal signal)
+{
+	/* Pass through eDP VDD enable from PCH */
+	gpio_set_level(GPIO_EC_EDP_VDD_EN, gpio_get_level(GPIO_PCH_EDP_VDD_EN));
+}
diff --git a/chip/lm4/openocd/lm4x_cmds.tcl b/chip/lm4/openocd/lm4x_cmds.tcl
index 3b32014710..47fff7fece 100644
--- a/chip/lm4/openocd/lm4x_cmds.tcl
+++ b/chip/lm4/openocd/lm4x_cmds.tcl
@@ -35,7 +35,19 @@ proc flash_slippy { } {
 	flash_lm4 ../../../build/slippy/ec.bin 0
 }
 
-# Slippy/falco/peppy/wolf have 128KB images
+# Bolt/slippy/falco/peppy/wolf have 128KB images
+proc flash_bolt { } {
+	flash_lm4 ../../../build/bolt/ec.bin 0
+}
+
+proc flash_bolt_ro { } {
+	flash_lm4 ../../../build/bolt/ec.RO.flat 0
+}
+
+proc flash_bolt_rw { } {
+	flash_lm4 ../../../build/bolt/ec.RW.bin 131072
+}
+
 proc flash_slippy_rw { } {
 	flash_lm4 ../../../build/slippy/ec.RW.bin 131072
 }
diff --git a/test/build.mk b/test/build.mk
index be882d02a0..3e09caa0fb 100644
--- a/test/build.mk
+++ b/test/build.mk
@@ -26,6 +26,7 @@ test-list-$(BOARD_slippy)=
 test-list-$(BOARD_falco)=
 test-list-$(BOARD_peppy)=
 test-list-$(BOARD_wolf)=
+test-list-$(BOARD_bolt)=
 
 # Emulator tests
 test-list-host=mutex pingpong utils kb_scan kb_mkbp lid_sw power_button hooks