samus: First pass at GPIOs

This is the first attempt at wiring the GPIOs for Samus. More to come, of
course.

BUG=chrome-os-partner:22870
BRANCH=none
TEST=manual

The only thing we can check is that it compiles and doesn't break anything.

  cd src/platform/ec
  make BOARD=samus
  make runtests

Change-Id: Ia9dc94c420c21551c5db3e28e749954cea3055a1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171528

3 files changed, 79 insertions, 135 deletions

diff --git a/board/samus/board.c b/board/samus/board.c
index 219cd6abf7..2126364367 100644
--- a/board/samus/board.c
+++ b/board/samus/board.c
@@ -40,8 +40,6 @@ const struct gpio_info gpio_list[] = {
 	 lid_interrupt},
 	{"AC_PRESENT",           LM4_GPIO_H, (1<<3), GPIO_INT_BOTH,
 	 extpower_interrupt},
-	{"PCH_BKLTEN",           LM4_GPIO_M, (1<<3), GPIO_INT_BOTH,
-	 backlight_interrupt},
 	{"PCH_SLP_S0_L",         LM4_GPIO_G, (1<<6), GPIO_INT_BOTH,
 	 x86_interrupt},
 	{"PCH_SLP_S3_L",         LM4_GPIO_G, (1<<7), GPIO_INT_BOTH,
@@ -52,19 +50,17 @@ const struct gpio_info gpio_list[] = {
 	 x86_interrupt},
 	{"PCH_SUSWARN_L",        LM4_GPIO_G, (1<<2), GPIO_INT_BOTH,
 	 x86_interrupt},
-	/* EC needs to control PP1050_PGOOD as it goes to VCCST_PGOOD. */
-	{"PP1050_PGOOD",         LM4_GPIO_H, (1<<4), GPIO_ODR_LOW, NULL },
-	{"PP1350_PGOOD",         LM4_GPIO_H, (1<<6), GPIO_INT_BOTH,
+	{"PP1050_PGOOD",         LM4_GPIO_H, (1<<4), GPIO_INT_BOTH,
 	 x86_interrupt},
-	{"PP5000_PGOOD",         LM4_GPIO_N, (1<<0), GPIO_INT_BOTH,
+	{"PP1200_PGOOD",         LM4_GPIO_H, (1<<6), GPIO_INT_BOTH,
+	 x86_interrupt},
+	{"PP1800_PGOOD",         LM4_GPIO_L, (1<<7), GPIO_INT_BOTH,
 	 x86_interrupt},
 	{"VCORE_PGOOD",          LM4_GPIO_C, (1<<6), GPIO_INT_BOTH,
 	 x86_interrupt},
-	{"PCH_EDP_VDD_EN",       LM4_GPIO_J, (1<<1), GPIO_INT_BOTH,
-	 haswell_interrupt},
 	{"RECOVERY_L",           LM4_GPIO_A, (1<<5), GPIO_PULL_UP|GPIO_INT_BOTH,
 	 switch_interrupt},
-	{"WP",                   LM4_GPIO_A, (1<<4), GPIO_INT_BOTH,
+	{"WP_L",                 LM4_GPIO_A, (1<<4), GPIO_INT_BOTH,
 	 switch_interrupt},
 
 	/* Other inputs */
@@ -73,23 +69,24 @@ const struct gpio_info gpio_list[] = {
 	{"BOARD_VERSION3",       LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
 	{"CPU_PGOOD",            LM4_GPIO_C, (1<<4), GPIO_INPUT, NULL},
 	{"ONEWIRE",              LM4_GPIO_F, (1<<7), GPIO_INPUT, NULL},
-	{"PCH_CATERR_L",         LM4_GPIO_F, (1<<3), GPIO_INPUT, NULL},
 	{"THERMAL_DATA_READY_L", LM4_GPIO_B, (1<<0), GPIO_INPUT, NULL},
 	{"USB1_OC_L",            LM4_GPIO_E, (1<<7), GPIO_INPUT, NULL},
 	{"USB1_STATUS_L",        LM4_GPIO_E, (1<<6), GPIO_INPUT, NULL},
 	{"USB2_OC_L",            LM4_GPIO_E, (1<<0), GPIO_INPUT, NULL},
 	{"USB2_STATUS_L",        LM4_GPIO_D, (1<<7), GPIO_INPUT, NULL},
+	/* Not yet sure if this will need to be handled as an interrupt */
+	{"CAPSENSE_INT_L",       LM4_GPIO_N, (1<<0), GPIO_INPUT, NULL},
 
 	/* Outputs; all unasserted by default except for reset signals */
 	{"CPU_PROCHOT",          LM4_GPIO_B, (1<<1), GPIO_OUT_LOW, NULL},
-	{"PP1350_EN",            LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
+	{"PP1200_EN",            LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
 	{"PP3300_DSW_GATED_EN",  LM4_GPIO_J, (1<<3), GPIO_OUT_LOW, NULL},
-	{"PP3300_DX_EN",         LM4_GPIO_F, (1<<6), GPIO_OUT_LOW, NULL},
 	{"PP3300_LTE_EN",        LM4_GPIO_D, (1<<2), GPIO_OUT_LOW, NULL},
 	{"PP3300_WLAN_EN",       LM4_GPIO_J, (1<<0), GPIO_OUT_LOW, NULL},
 	{"PP1050_EN",            LM4_GPIO_C, (1<<7), GPIO_OUT_LOW, NULL},
-	{"VCORE_EN",             LM4_GPIO_C, (1<<5), GPIO_OUT_LOW, NULL},
+	{"PP5000_USB_EN",        LM4_GPIO_C, (1<<5), GPIO_OUT_LOW, NULL},
 	{"PP5000_EN",            LM4_GPIO_H, (1<<7), GPIO_OUT_LOW, NULL},
+	{"PP1800_EN",            LM4_GPIO_L, (1<<6), GPIO_OUT_LOW, NULL},
 	{"SYS_PWROK",            LM4_GPIO_H, (1<<2), GPIO_OUT_LOW, NULL},
 	{"WLAN_OFF_L",           LM4_GPIO_J, (1<<4), GPIO_OUT_LOW, NULL},
 
@@ -107,13 +104,10 @@ const struct gpio_info gpio_list[] = {
 	{"PCH_NMI_L",            LM4_GPIO_F, (1<<2), GPIO_ODR_HIGH, NULL},
 	{"PCH_PWRBTN_L",         LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL},
 	{"PCH_PWROK",            LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
-	/* FIXME: Why is PL6 act like it is inverted. Setting value to
-	 * 0 makes the signal high, and setting it to 1 makes the signal low. */
-	{"PCH_RCIN_L",           LM4_GPIO_L, (1<<6), GPIO_INPUT, NULL},
-	{"PCH_SYSRST_L",         LM4_GPIO_F, (1<<1), GPIO_ODR_HIGH, NULL},
+	{"PCH_RCIN_L",           LM4_GPIO_F, (1<<3), GPIO_OUT_HIGH, NULL},
+	{"PCH_SYS_RST_L",        LM4_GPIO_F, (1<<1), GPIO_ODR_HIGH, NULL},
 	{"PCH_SMI_L",            LM4_GPIO_F, (1<<4), GPIO_ODR_HIGH, NULL},
 	{"TOUCHSCREEN_RESET_L",  LM4_GPIO_N, (1<<7), GPIO_OUT_LOW, NULL},
-	{"EC_EDP_VDD_EN",        LM4_GPIO_J, (1<<5), GPIO_OUT_LOW, NULL},
 
 	{"LPC_CLKRUN_L",         LM4_GPIO_M, (1<<2), GPIO_ODR_HIGH, NULL},
 	{"USB1_CTL1",            LM4_GPIO_E, (1<<1), GPIO_OUT_LOW, NULL},
@@ -150,13 +144,15 @@ const int gpio_alt_funcs_count = ARRAY_SIZE(gpio_alt_funcs);
 
 /* x86 signal list.  Must match order of enum x86_signal. */
 const struct x86_signal_info x86_signal_list[] = {
-	{GPIO_PP5000_PGOOD,  1, "PGOOD_PP5000"},
-	{GPIO_PP1350_PGOOD,  1, "PGOOD_PP1350"},
+	{GPIO_PP1050_PGOOD,  1, "PGOOD_PP1050"},
+	{GPIO_PP1200_PGOOD,  1, "PGOOD_PP1200"},
+	{GPIO_PP1800_PGOOD,  1, "PGOOD_PP1800"},
 	{GPIO_VCORE_PGOOD,   1, "PGOOD_VCORE"},
-	{GPIO_PCH_SLP_S0_L,  1, "SLP_S0#_DEASSERTED"},
-	{GPIO_PCH_SLP_S3_L,  1, "SLP_S3#_DEASSERTED"},
-	{GPIO_PCH_SLP_S5_L,  1, "SLP_S5#_DEASSERTED"},
-	{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS#_DEASSERTED"},
+	{GPIO_PCH_SLP_S0_L,  1, "SLP_S0_L_DEASSERTED"},
+	{GPIO_PCH_SLP_S3_L,  1, "SLP_S3_L_DEASSERTED"},
+	{GPIO_PCH_SLP_S5_L,  1, "SLP_S5_L_DEASSERTED"},
+	{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS_L_DEASSERTED"},
+	{GPIO_PCH_SUSWARN_L, 1, "SUSWARN_L_DEASSERTED"},
 };
 BUILD_ASSERT(ARRAY_SIZE(x86_signal_list) == X86_SIGNAL_COUNT);
 
diff --git a/board/samus/board.h b/board/samus/board.h
index 3a6935fa01..05c53e973d 100644
--- a/board/samus/board.h
+++ b/board/samus/board.h
@@ -15,6 +15,7 @@
 #define CONFIG_TASK_PROFILING
 
 /* Optional features */
+#define CONFIG_BOARD_VERSION
 #define CONFIG_CHIPSET_X86
 #define CONFIG_CHIPSET_CAN_THROTTLE
 #define CONFIG_CUSTOM_KEYSCAN
@@ -25,12 +26,10 @@
 #define CONFIG_ONEWIRE
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
-#define CONFIG_WP_ACTIVE_HIGH
 
 #define CONFIG_BATTERY_LINK
 #define CONFIG_BATTERY_SMART
 #define CONFIG_BACKLIGHT_LID
-#define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_BQ24715
 /* 10mOhm sense resitors. */
@@ -49,10 +48,7 @@
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_UART_HOST 2
 #define CONFIG_WIRELESS
-#if 0
-#define CONFIG_USB_PORT_POWER_DUMB
-#endif
-
+#define CONFIG_USB_PORT_POWER_SMART
 
 #ifndef __ASSEMBLER__
 
@@ -91,19 +87,17 @@ enum gpio_signal {
 	GPIO_POWER_BUTTON_L = 0,   /* Power button */
 	GPIO_LID_OPEN,             /* Lid switch */
 	GPIO_AC_PRESENT,           /* AC power present */
-	GPIO_PCH_BKLTEN,           /* Backlight enable signal from PCH */
 	GPIO_PCH_SLP_S0_L,         /* SLP_S0# signal from PCH */
 	GPIO_PCH_SLP_S3_L,         /* SLP_S3# signal from PCH */
 	GPIO_PCH_SLP_S5_L,         /* SLP_S5# signal from PCH */
 	GPIO_PCH_SLP_SUS_L,        /* SLP_SUS# signal from PCH */
 	GPIO_PCH_SUSWARN_L,        /* SUSWARN# signal from PCH */
 	GPIO_PP1050_PGOOD,         /* Power good on 1.05V */
-	GPIO_PP1350_PGOOD,         /* Power good on 1.35V (DRAM) */
-	GPIO_PP5000_PGOOD,         /* Power good on 5V */
+	GPIO_PP1200_PGOOD,         /* Power good on 1.2V (DRAM) */
+	GPIO_PP1800_PGOOD,         /* Power good on 1.8V (DRAM) */
 	GPIO_VCORE_PGOOD,          /* Power good on core VR */
-	GPIO_PCH_EDP_VDD_EN,       /* PCH wants EDP enabled */
 	GPIO_RECOVERY_L,           /* Recovery signal from servo */
-	GPIO_WP,                   /* Write protect input */
+	GPIO_WP_L,                 /* Write protect input */
 
 	/* Other inputs */
 	GPIO_BOARD_VERSION1,       /* Board version stuffing resistor 1 */
@@ -111,23 +105,23 @@ enum gpio_signal {
 	GPIO_BOARD_VERSION3,       /* Board version stuffing resistor 3 */
 	GPIO_CPU_PGOOD,            /* Power good to the CPU */
 	GPIO_ONEWIRE,              /* One-wire bus to adapter LED */
-	GPIO_PCH_CATERR_L,         /* Catastrophic error signal from PCH */
 	GPIO_THERMAL_DATA_READY_L, /* From thermal sensor */
 	GPIO_USB1_OC_L,            /* USB port overcurrent warning */
 	GPIO_USB1_STATUS_L,        /* USB charger port 1 status output */
 	GPIO_USB2_OC_L,            /* USB port overcurrent warning */
 	GPIO_USB2_STATUS_L,        /* USB charger port 2 status output */
+	GPIO_CAPSENSE_INT_L,       /* Capsense interrupt (through EC_WAKE_L) */
 
 	/* Outputs */
 	GPIO_CPU_PROCHOT,          /* Force CPU to think it's overheated */
-	GPIO_PP1350_EN,            /* Enable 1.35V supply */
+	GPIO_PP1200_EN,            /* Enable 1.20V supply */
 	GPIO_PP3300_DSW_GATED_EN,  /* Enable DSW rails */
-	GPIO_PP3300_DX_EN,         /* Enable power to lots of peripherals */
 	GPIO_PP3300_LTE_EN,        /* Enable LTE radio */
 	GPIO_PP3300_WLAN_EN,       /* Enable WiFi power */
 	GPIO_PP1050_EN,            /* Enable 1.05V regulator */
-	GPIO_VCORE_EN,             /* Stuffing option - not connected */
+	GPIO_PP5000_USB_EN,        /* Enable USB power */
 	GPIO_PP5000_EN,            /* Enable 5V supply */
+	GPIO_PP1800_EN,            /* Enable 1.8V supply */
 	GPIO_SYS_PWROK,            /* EC thinks everything is up and ready */
 	GPIO_WLAN_OFF_L,           /* Disable WiFi radio */
 
@@ -147,7 +141,6 @@ enum gpio_signal {
 	GPIO_PCH_SYS_RST_L,        /* Reset PCH resume power plane logic */
 	GPIO_PCH_SMI_L,            /* System management interrupt to PCH */
 	GPIO_TOUCHSCREEN_RESET_L,  /* Reset touch screen */
-	GPIO_EC_EDP_VDD_EN,        /* Enable EDP (passthru from PCH) */
 	GPIO_LPC_CLKRUN_L,         /* Dunno. Probably important, though. */
 
 	GPIO_USB1_CTL1,            /* USB charger port 1 CTL1 output */
@@ -167,13 +160,16 @@ enum gpio_signal {
 
 /* x86 signal definitions */
 enum x86_signal {
-	X86_PGOOD_PP5000 = 0,
-	X86_PGOOD_PP1350,
+	X86_PGOOD_PP1050 = 0,
+	X86_PGOOD_PP1200,
+	X86_PGOOD_PP1800,
 	X86_PGOOD_VCORE,
-	X86_PCH_SLP_S0n_DEASSERTED,
-	X86_PCH_SLP_S3n_DEASSERTED,
-	X86_PCH_SLP_S5n_DEASSERTED,
-	X86_PCH_SLP_SUSn_DEASSERTED,
+
+	X86_PCH_SLP_S0_L_DEASSERTED,
+	X86_PCH_SLP_S3_L_DEASSERTED,
+	X86_PCH_SLP_S5_L_DEASSERTED,
+	X86_PCH_SLP_SUS_L_DEASSERTED,
+	X86_PCH_SUSWARN_L_DEASSERTED,
 
 	/* Number of X86 signals */
 	X86_SIGNAL_COUNT
diff --git a/board/samus/power_sequence.c b/board/samus/power_sequence.c
index 606e5434cb..771906e699 100644
--- a/board/samus/power_sequence.c
+++ b/board/samus/power_sequence.c
@@ -23,31 +23,34 @@
 #define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
 
 /* Input state flags */
-#define IN_PGOOD_PP5000            X86_SIGNAL_MASK(X86_PGOOD_PP5000)
-#define IN_PGOOD_PP1350            X86_SIGNAL_MASK(X86_PGOOD_PP1350)
-#define IN_PGOOD_VCORE             X86_SIGNAL_MASK(X86_PGOOD_VCORE)
-#define IN_PCH_SLP_S0n_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S0n_DEASSERTED)
-#define IN_PCH_SLP_S3n_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S3n_DEASSERTED)
-#define IN_PCH_SLP_S5n_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S5n_DEASSERTED)
-#define IN_PCH_SLP_SUSn_DEASSERTED X86_SIGNAL_MASK(X86_PCH_SLP_SUSn_DEASSERTED)
-
-/* All always-on supplies */
-#define IN_PGOOD_ALWAYS_ON   (IN_PGOOD_PP5000)
+#define IN_PGOOD_PP1050           X86_SIGNAL_MASK(X86_PGOOD_PP1050)
+#define IN_PGOOD_PP1200           X86_SIGNAL_MASK(X86_PGOOD_PP1200)
+#define IN_PGOOD_PP1800           X86_SIGNAL_MASK(X86_PGOOD_PP1800)
+#define IN_PGOOD_VCORE            X86_SIGNAL_MASK(X86_PGOOD_VCORE)
+
+#define IN_PCH_SLP_S0_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S0_L_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S3_L_DEASSERTED)
+#define IN_PCH_SLP_S5_DEASSERTED  X86_SIGNAL_MASK(X86_PCH_SLP_S5_L_DEASSERTED)
+#define IN_PCH_SLP_SUS_DEASSERTED X86_SIGNAL_MASK(X86_PCH_SLP_SUS_L_DEASSERTED)
+
+
 /* All non-core power rails */
-#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP1350)
+#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP1050)
 /* All core power rails */
 #define IN_PGOOD_ALL_CORE    (IN_PGOOD_VCORE)
 /* Rails required for S3 */
-#define IN_PGOOD_S3          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_PP1350)
+#define IN_PGOOD_S3          (IN_PGOOD_PP1200 | IN_PGOOD_PP1800)
 /* Rails required for S0 */
-#define IN_PGOOD_S0          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
+#define IN_PGOOD_S0          (IN_PGOOD_ALL_NONCORE)
 
 /* All PM_SLP signals from PCH deasserted */
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3n_DEASSERTED |		\
-				  IN_PCH_SLP_S5n_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
+				  IN_PCH_SLP_S5_DEASSERTED | \
+				  IN_PCH_SLP_SUS_DEASSERTED)
+
 /* All inputs in the right state for S0 */
-#define IN_ALL_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE |		\
-		   IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
+#define IN_ALL_S0 (IN_PGOOD_ALL_NONCORE | IN_PGOOD_ALL_CORE | \
+		   IN_ALL_PM_SLP_DEASSERTED)
 
 static int throttle_cpu;      /* Throttle CPU? */
 
@@ -91,15 +94,11 @@ void chipset_reset(int cold_reset)
 		 */
 
 		/*
-		 * Pulse must be at least 16 PCI clocks long = 500 ns. The gpio
-		 * pin used by the EC (PL6) does not behave in the correct
-		 * manner when configured as open drain. In order to mimic
-		 * open drain, the pin is initially configured as an input.
-		 * When it is needed to drive low, the flags are updated which
-		 * changes the pin to an output and drives the pin low.  */
-		gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_OUT_LOW);
+		 * Pulse must be at least 16 PCI clocks long = 500 ns.
+		 */
+		gpio_set_level(GPIO_PCH_RCIN_L, 0);
 		udelay(10);
-		gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_INPUT);
+		gpio_set_level(GPIO_PCH_RCIN_L, 1);
 	}
 }
 
@@ -110,9 +109,6 @@ void chipset_throttle_cpu(int throttle)
 
 enum x86_state x86_chipset_init(void)
 {
-	/* Enable interrupts for our GPIOs */
-	gpio_enable_interrupt(GPIO_PCH_EDP_VDD_EN);
-
 	/*
 	 * If we're switching between images without rebooting, see if the x86
 	 * is already powered on; if so, leave it there instead of cycling
@@ -127,13 +123,11 @@ enum x86_state x86_chipset_init(void)
 			CPRINTF("[%T x86 forcing G3]\n");
 			gpio_set_level(GPIO_PCH_PWROK, 0);
 			gpio_set_level(GPIO_SYS_PWROK, 0);
-			gpio_set_level(GPIO_VCORE_EN, 0);
 			gpio_set_level(GPIO_PP1050_EN, 0);
-			gpio_set_level(GPIO_PP1350_EN, 0);
-			gpio_set_level(GPIO_PP1050_PGOOD, 0);
-			gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
-			gpio_set_level(GPIO_PP3300_DX_EN, 0);
+			gpio_set_level(GPIO_PP1200_EN, 0);
+			gpio_set_level(GPIO_PP1800_EN, 0);
 			gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
+			gpio_set_level(GPIO_PP5000_USB_EN, 0);
 			gpio_set_level(GPIO_PP5000_EN, 0);
 			gpio_set_level(GPIO_PCH_DPWROK, 0);
 			wireless_enable(0);
@@ -195,33 +189,19 @@ enum x86_state x86_handle_state(enum x86_state state)
 		 */
 		msleep(10);
 
-		/* Enable PP5000 (5V) rail as 1.05V and 1.35V rails need 5V
+		/* Enable PP5000 (5V) rail as 1.05V and 1.2V rails need 5V
 		 * rail to regulate properly. */
 		gpio_set_level(GPIO_PP5000_EN, 1);
-		if (x86_wait_signals(IN_PGOOD_PP5000)) {
-			chipset_force_shutdown();
-			return X86_G3;
-		}
 
 		/* Assert DPWROK */
 		gpio_set_level(GPIO_PCH_DPWROK, 1);
 
-		/* Enable PP1050 rail. Bring up the PP1050_PCH_SUS rail to
-		 * provide 1.05V suspend as early as possible as the RSMSRT#
-		 * signal deasserting indicates both the PP3300_PCH_SUS
-		 * and PP1050_PCH_SUS rails are good. Since PP1050_PGGOOD is
-		 * driven as output to work around VCCST_PWRGD timing problems
-		 * there is no way to know when PP1050_PCH_SUS rail is good.
-		 * Similarly the PP3300_PCH_SUS rail is enabled by SLP_SUS#
-		 * being deasserted without a power good signal. The RSMRST#
-		 * is driven by an RC circuit feeding into schmitt trigger.
-		 * Therefore, the PP1050_PCH_SUS rail is brought up as early
-		 * as possible after DPWROK is asserted so that it will be
-		 * ready by the time RSMRST# is deasserted. */
+		/* Enable PP1050 rail. */
 		gpio_set_level(GPIO_PP1050_EN, 1);
 
-		/* Wait for SLP_SUS# to deassert before enabling PP1050. */
-		if (x86_wait_signals(IN_PCH_SLP_SUSn_DEASSERTED)) {
+		/* Wait for 1.05V to come up and CPU to notice */
+		if (x86_wait_signals(IN_PGOOD_PP1050 |
+				     IN_PCH_SLP_SUS_DEASSERTED)) {
 			chipset_force_shutdown();
 			return X86_G3;
 		}
@@ -231,14 +211,9 @@ enum x86_state x86_handle_state(enum x86_state state)
 		return X86_S5;
 
 	case X86_S5S3:
-		/* Wait for the always-on rails to be good */
-		if (x86_wait_signals(IN_PGOOD_ALWAYS_ON)) {
-			chipset_force_shutdown();
-			return X86_S5;
-		}
-
 		/* Turn on power to RAM */
-		gpio_set_level(GPIO_PP1350_EN, 1);
+		gpio_set_level(GPIO_PP1200_EN, 1);
+		gpio_set_level(GPIO_PP1800_EN, 1);
 		if (x86_wait_signals(IN_PGOOD_S3)) {
 			chipset_force_shutdown();
 			return X86_S5;
@@ -263,13 +238,11 @@ enum x86_state x86_handle_state(enum x86_state state)
 
 	case X86_S3S0:
 		/* Wait 20ms before allowing VCCST_PGOOD to rise. */
-		msleep(20);
-		/* Assert VCCST_PGOOD using PP1050_PGOOD. */
-		gpio_set_level(GPIO_PP1050_PGOOD, 1);
+		msleep(20);	   /* HEY: really? */
 
 		/* Turn on power rails */
-		gpio_set_level(GPIO_PP3300_DX_EN, 1);
 		gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
+		gpio_set_level(GPIO_PP5000_USB_EN, 1);
 
 		/* Enable wireless */
 		wireless_enable(EC_WIRELESS_SWITCH_ALL);
@@ -285,19 +258,11 @@ enum x86_state x86_handle_state(enum x86_state state)
 		if (x86_wait_signals(IN_PGOOD_S0)) {
 			chipset_force_shutdown();
 			wireless_enable(0);
-			gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
-			gpio_set_level(GPIO_PP3300_DX_EN, 0);
 			gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
-			gpio_set_level(GPIO_PP1050_PGOOD, 0);
+			gpio_set_level(GPIO_PP5000_USB_EN, 0);
 			return X86_S3;
 		}
 
-		/*
-		 * Enable +CPU_CORE.  The CPU itself will request the supplies
-		 * when it's ready.
-		 */
-		gpio_set_level(GPIO_VCORE_EN, 1);
-
 		/* Call hooks now that rails are up */
 		hook_notify(HOOK_CHIPSET_RESUME);
 
@@ -319,8 +284,6 @@ enum x86_state x86_handle_state(enum x86_state state)
 		/* Call hooks before we remove power rails */
 		hook_notify(HOOK_CHIPSET_SUSPEND);
 
-		/* Drop VCCST_PGOOD */
-		gpio_set_level(GPIO_PP1050_PGOOD, 0);
 		/* Clear PCH_PWROK */
 		gpio_set_level(GPIO_SYS_PWROK, 0);
 		gpio_set_level(GPIO_PCH_PWROK, 0);
@@ -328,9 +291,6 @@ enum x86_state x86_handle_state(enum x86_state state)
 		/* Wait 40ns */
 		udelay(1);
 
-		/* Disable +CPU_CORE */
-		gpio_set_level(GPIO_VCORE_EN, 0);
-
 		/* Disable wireless */
 		wireless_enable(0);
 
@@ -341,8 +301,6 @@ enum x86_state x86_handle_state(enum x86_state state)
 		gpio_set_level(GPIO_CPU_PROCHOT, 0);
 
 		/* Turn off power rails */
-		gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
-		gpio_set_level(GPIO_PP3300_DX_EN, 0);
 		gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
 		return X86_S3;
 
@@ -350,11 +308,13 @@ enum x86_state x86_handle_state(enum x86_state state)
 		/* Call hooks before we remove power rails */
 		hook_notify(HOOK_CHIPSET_SHUTDOWN);
 
-		/* Disable touchpad power */
+		/* Disable peripheral power */
 		gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
+		gpio_set_level(GPIO_PP5000_USB_EN, 0);
 
 		/* Turn off power to RAM */
-		gpio_set_level(GPIO_PP1350_EN, 0);
+		gpio_set_level(GPIO_PP1800_EN, 0);
+		gpio_set_level(GPIO_PP1200_EN, 0);
 
 		/*
 		 * Put touchscreen and lightbar in reset, so we won't
@@ -375,16 +335,8 @@ enum x86_state x86_handle_state(enum x86_state state)
 		/* Deassert DPWROK */
 		gpio_set_level(GPIO_PCH_DPWROK, 0);
 		gpio_set_level(GPIO_PP1050_EN, 0);
-		/* Disable PP5000 (5V) rail. */
-		gpio_set_level(GPIO_PP5000_EN, 0);
 		return X86_G3;
 	}
 
 	return state;
 }
-
-void haswell_interrupt(enum gpio_signal signal)
-{
-	/* Pass through eDP VDD enable from PCH */
-	gpio_set_level(GPIO_EC_EDP_VDD_EN, gpio_get_level(GPIO_PCH_EDP_VDD_EN));
-}