diff options
| author | Randall Spangler <rspangler@chromium.org> | 2013-10-18 16:44:06 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-10-21 21:10:40 +0000 |
| commit | 1d6687429c1ea236bf09ac32d4936888a36730e6 (patch) | |
| tree | 8efe4e10affdc11c6d288bec17faeb0efe37c093 | |
| parent | d9530449fd75650a53d2ee8d9cfdc8ef063781b5 (diff) | |
| download | chrome-ec-1d6687429c1ea236bf09ac32d4936888a36730e6.tar.gz | |
rambi: Support USB port power control
Rambi shares several of the control signals (CTL1, ILIM_SEL) between
both ports, and hard-wires some of the others (CTL2, CTL3). It still
has separate enable lines for each port.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=boot system; gpioget shows (in part)
1 USB_CTL1
0 USB_ILIM_SEL
1 USB1_ENABLE
1 USB2_ENABLE
Then do 'apshutdown' and gpioget shows
1 USB_CTL1
0 USB_ILIM_SEL
0 USB1_ENABLE
0 USB2_ENABLE
Change-Id: Ib3d321ca2b0aa7dce08ddd6633810a75641bc9a8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173737
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
| -rw-r--r-- | board/rambi/board.h | 2 | ||||
| -rw-r--r-- | common/usb_port_power_smart.c | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/board/rambi/board.h b/board/rambi/board.h index 2cc95f1fb1..4531bdfc8d 100644 --- a/board/rambi/board.h +++ b/board/rambi/board.h @@ -26,6 +26,7 @@ #define CONFIG_TEMP_SENSOR #define CONFIG_TEMP_SENSOR_G781 #define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PP3300_DX_EN +#define CONFIG_USB_PORT_POWER_SMART #define CONFIG_WIRELESS /* TODO(rspangler): port these to Rambi, or remove if not needed */ @@ -38,7 +39,6 @@ #define CONFIG_CHARGER_INPUT_CURRENT 4032 /* mA, about half max */ #define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */ #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input sensor resistor, mOhm */ -#define CONFIG_USB_PORT_POWER_DUMB #endif #ifndef __ASSEMBLER__ diff --git a/common/usb_port_power_smart.c b/common/usb_port_power_smart.c index dfe7b32d5f..def565239a 100644 --- a/common/usb_port_power_smart.c +++ b/common/usb_port_power_smart.c @@ -34,6 +34,14 @@ static uint8_t charge_mode[USB_CHARGE_PORT_COUNT]; static void usb_charge_set_control_mode(int port_id, int mode) { +#ifdef BOARD_rambi + /* + * Rambi has only a single shared control signal, so the last mode set + * to either port wins. Also, only CTL1 can be set; the other pins + * are hard-wired. + */ + gpio_set_level(GPIO_USB_CTL1, mode & 0x4); +#else if (port_id == 0) { gpio_set_level(GPIO_USB1_CTL1, mode & 0x4); gpio_set_level(GPIO_USB1_CTL2, mode & 0x2); @@ -43,6 +51,7 @@ static void usb_charge_set_control_mode(int port_id, int mode) gpio_set_level(GPIO_USB2_CTL2, mode & 0x2); gpio_set_level(GPIO_USB2_CTL3, mode & 0x1); } +#endif } static void usb_charge_set_enabled(int port_id, int en) @@ -55,10 +64,15 @@ static void usb_charge_set_enabled(int port_id, int en) static void usb_charge_set_ilim(int port_id, int sel) { +#ifdef BOARD_rambi + /* Rambi has a shared ILIM_SEL signal too */ + gpio_set_level(GPIO_USB_ILIM_SEL, sel); +#else if (port_id == 0) gpio_set_level(GPIO_USB1_ILIM_SEL, sel); else gpio_set_level(GPIO_USB2_ILIM_SEL, sel); +#endif } static void usb_charge_all_ports_on(void) |