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authorAaron Durbin <adurbin@chromium.org>2013-10-09 17:49:48 -0500
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2013-10-10 16:40:46 +0000
commit6a46446ccc3c7ce867d145be93876f87464928cf (patch)
tree94500f5d13bc03478bfd4a60ba6f3feec56e195c
parent2fb228c198d2581df4c90bd94f0240737a9db134 (diff)
downloadchrome-ec-6a46446ccc3c7ce867d145be93876f87464928cf.tar.gz
rambi: fix leakage on pp3300_pch_s5 rail
PWRBTN_L is pulled up to PP3300_PCH_S5 through a 30K resistor. However, the PWRBTN_L pin was configured push-pull. So we are leaking into that rail. Fix this by configuring it to be open drain. BUG=chrome-os-partner:23221 BRANCH=None TEST=Loaded new EC with change and noted the PP3300_PCH_S5_PG is driven low correctly once the PP5000_DSW rail is up an SUSP_VR_EN=0. Change-Id: Id6d5079ca0c11c36b00ed913be378f53b48f27f3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172520 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
-rw-r--r--board/rambi/board.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/rambi/board.c b/board/rambi/board.c
index 0ba70a89be..38f4262fe4 100644
--- a/board/rambi/board.c
+++ b/board/rambi/board.c
@@ -76,7 +76,7 @@ const struct gpio_info gpio_list[] = {
{"ENTERING_RW", LM4_GPIO_D, (1<<6), GPIO_OUT_LOW, NULL},
{"LPC_CLKRUN_L", LM4_GPIO_M, (1<<2), GPIO_ODR_HIGH, NULL},
{"PCH_CORE_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
- {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL},
+ {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_ODR_HIGH, NULL},
{"PCH_RCIN_L", LM4_GPIO_F, (1<<3), GPIO_ODR_LOW, NULL},
{"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL},
{"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_ODR_HIGH, NULL},