cleanup: update comments with existing bug numbers

Some of the comments no longer apply.  Others needed more info.

No code changes; just comment changes.

BUG=none
BRANCH=none
TEST=build all platforms

Change-Id: I1d52aa9a98427a78c9d9a8cf44934fb04c3c00c8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174084
Reviewed-by: Bill Richardson <wfrichar@chromium.org>

4 files changed, 11 insertions, 25 deletions

diff --git a/board/daisy/board.h b/board/daisy/board.h
index 4cad8e7587..99fc555a9e 100644
--- a/board/daisy/board.h
+++ b/board/daisy/board.h
@@ -24,11 +24,8 @@
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
- * switch.
- *
- * TODO: (crosbug.com/p/9986) This is a serious security hole and should be
- * removed in mass production.  Acceptable here only because daisy isn't a
- * production board.
+ * switch.  This is a serious security hole, but is acceptable here because
+ * daisy isn't a production board.
  */
 #define CONFIG_SYSTEM_UNLOCKED
 
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index 8f24bb2ed2..587c79c22a 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -208,17 +208,10 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 	if (size > EC_PROTO2_MAX_PARAM_SIZE)
 		args->result = EC_RES_INVALID_RESPONSE;
 
-	/*
-	 * Write result to the data byte.  This sets the TOH bit in the
-	 * status byte and triggers an IRQ on the host so the host can read
-	 * the result.
-	 *
-	 * TODO: (crosbug.com/p/7496) or it would, if we actually set up host
-	 * IRQs
-	 */
+	/* Write result to the data byte.  This sets the TOH status bit. */
 	LPC_POOL_CMD[1] = args->result;
 
-	/* Clear the busy bit */
+	/* Clear the busy bit, so the host knows the EC is done. */
 	task_disable_irq(LM4_IRQ_LPC);
 	LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
 	task_enable_irq(LM4_IRQ_LPC);
@@ -230,17 +223,10 @@ static void lpc_send_response_packet(struct host_packet *pkt)
 	if (pkt->driver_result == EC_RES_IN_PROGRESS)
 		return;
 
-	/*
-	 * Write result to the data byte.  This sets the TOH bit in the
-	 * status byte and triggers an IRQ on the host so the host can read
-	 * the result.
-	 *
-	 * TODO: (crosbug.com/p/7496) or it would, if we actually set up host
-	 * IRQs
-	 */
+	/* Write result to the data byte.  This sets the TOH status bit. */
 	LPC_POOL_CMD[1] = pkt->driver_result;
 
-	/* Clear the busy bit */
+	/* Clear the busy bit, so the host knows the EC is done. */
 	task_disable_irq(LM4_IRQ_LPC);
 	LM4_LPC_ST(LPC_CH_CMD) &= ~LM4_LPC_ST_BUSY;
 	task_enable_irq(LM4_IRQ_LPC);
diff --git a/chip/stm32/clock-stm32f.c b/chip/stm32/clock-stm32f.c
index 11b426a42f..96218f115f 100644
--- a/chip/stm32/clock-stm32f.c
+++ b/chip/stm32/clock-stm32f.c
@@ -30,7 +30,10 @@
 /*
  * RTC clock frequency (connected to LSI clock)
  *
- * TODO: crosbug.com/p/12281 calibrate LSI frequency
+ * TODO(crosbug.com/p/12281): Calibrate LSI frequency on a per-chip basis.  The
+ * LSI on any given chip can be between 30 kHz to 60 kHz.  Without calibration,
+ * LSI frequency may be off by as much as 50%.  Fortunately, we don't do any
+ * high-precision delays based solely on LSI.
  */
 #define RTC_FREQ 40000 /* Hz */
 #define US_PER_RTC_TICK (1000000 / RTC_FREQ)
diff --git a/include/ec_commands.h b/include/ec_commands.h
index 0c38166a90..827119daeb 100644
--- a/include/ec_commands.h
+++ b/include/ec_commands.h
@@ -1684,7 +1684,7 @@ struct ec_response_i2c_passthru {
 
 
 /*****************************************************************************/
-/* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */
+/* Debug commands for battery charging */
 
 /*
  * Dump charge state machine context.