diff options
author | Vic (Chun-Ju) Yang <victoryang@chromium.org> | 2013-11-27 12:00:52 +0800 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-11-27 13:38:27 +0000 |
commit | a981a1fa1637196f486d2c067722ecc71edeb1b0 (patch) | |
tree | 5376d138b0e9440eee19287f12bfd69c03ed2122 | |
parent | 009dd17588c8b1f0160e1e7c2acf3a4a4bb9dd80 (diff) | |
download | chrome-ec-a981a1fa1637196f486d2c067722ecc71edeb1b0.tar.gz |
mec1322: Add more register address and IRQ numbers
No functional changes. Just adding more chip-specific constants.
BUG=chrome-os-partner:24107
TEST=Build mec1322_evb
BRANCH=None
Change-Id: I649ad2656da941c28a2a738007ced955cd25ea75
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178170
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
-rw-r--r-- | chip/mec1322/registers.h | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index 1e7634267f..18bf3ba936 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -16,6 +16,28 @@ #define MEC1322_CHIP_DEV_REV REG8(MEC1322_CHIP_BASE + 0x21) +/* Power/Clocks/Resets */ +#define MEC1322_PCR_BASE 0x40080100 +#define MEC1322_PCR_CHIP_SLP_EN REG32(MEC1322_PCR_BASE + 0x0) +#define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4) +#define MEC1322_PCR_EC_SLP_EN REG32(MEC1322_PCR_BASE + 0x8) +#define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc) +#define MEC1322_PCR_HOST_SLP_EN REG32(MEC1322_PCR_BASE + 0x10) +#define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14) +#define MEC1322_PCR_SYS_SLP_CTL REG32(MEC1322_PCR_BASE + 0x18) +#define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20) +#define MEC1322_PCR_EC_SLP_EN2 REG32(MEC1322_PCR_BASE + 0x24) +#define MEC1322_PCR_EC_CLK_REQ2 REG32(MEC1322_PCR_BASE + 0x28) +#define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c) +#define MEC1322_PCR_CHIP_OSC_ID REG32(MEC1322_PCR_BASE + 0x30) +#define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34) +#define MEC1322_PCR_CHIP_RST_EN REG32(MEC1322_PCR_BASE + 0x38) +#define MEC1322_PCR_HOST_RST_EN REG32(MEC1322_PCR_BASE + 0x3c) +#define MEC1322_PCR_EC_RST_EN REG32(MEC1322_PCR_BASE + 0x40) +#define MEC1322_PCR_EC_RST_EN2 REG32(MEC1322_PCR_BASE + 0x44) +#define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) + + /* EC Subsystem */ #define MEC1322_EC_BASE 0x4000fc00 #define MEC1322_EC_INT_CTRL REG32(MEC1322_EC_BASE + 0x18) @@ -101,6 +123,55 @@ static inline uintptr_t gpio_port_base(int port_id) #define MEC1322_VBAT_CE REG32(MEC1322_VBAT_BASE + 0x8) +/* LPC */ +#define MEC1322_LPC_CFG_BASE 0x400f3300 +#define MEC1322_LPC_ACT REG8(MEC1322_LPC_CFG_BASE + 0x30) +#define MEC1322_LPC_SIRQ(x) REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x)) +#define MEC1322_LPC_CFG_BAR REG32(MEC1322_LPC_CFG_BASE + 0x60) +#define MEC1322_LPC_EMI_BAR REG32(MEC1322_LPC_CFG_BASE + 0x64) +#define MEC1322_LPC_UART_BAR REG32(MEC1322_LPC_CFG_BASE + 0x68) +#define MEC1322_LPC_8042_BAR REG32(MEC1322_LPC_CFG_BASE + 0x78) +#define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88) +#define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c) +#define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90) +#define MEC1322_LPC_PORT92_BAR REG32(MEC1322_LPC_CFG_BASE + 0x94) +#define MEC1322_LPC_MAILBOX_BAR REG32(MEC1322_LPC_CFG_BASE + 0x98) +#define MEC1322_LPC_RTC_BAR REG32(MEC1322_LPC_CFG_BASE + 0x9c) +#define MEC1322_LPC_MEM_BAR REG32(MEC1322_LPC_CFG_BASE + 0xa0) +#define MEC1322_LPC_MEM_BAR_CFG REG32(MEC1322_LPC_CFG_BASE + 0xa4) + +#define MEC1322_LPC_RT_BASE 0x400f3100 +#define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc) + + +/* EMI */ +#define MEC1322_EMI_BASE 0x400f0100 +#define MEC1322_EMI_H2E_MBX REG8(MEC1322_EMI_BASE + 0x0) +#define MEC1322_EMI_E2H_MBX REG8(MEC1322_EMI_BASE + 0x1) +#define MEC1322_EMI_MBA0 REG32(MEC1322_EMI_BASE + 0x4) +#define MEC1322_EMI_MRL0 REG16(MEC1322_EMI_BASE + 0x8) +#define MEC1322_EMI_MWL0 REG16(MEC1322_EMI_BASE + 0xa) +#define MEC1322_EMI_MBA1 REG32(MEC1322_EMI_BASE + 0xc) +#define MEC1322_EMI_MRL1 REG16(MEC1322_EMI_BASE + 0x10) +#define MEC1322_EMI_MWL1 REG16(MEC1322_EMI_BASE + 0x12) +#define MEC1322_EMI_ISR REG16(MEC1322_EMI_BASE + 0x14) +#define MEC1322_EMI_HCE REG16(MEC1322_EMI_BASE + 0x16) + +#define MEC1322_EMI_RT_BASE 0x400f0000 +#define MEC1322_EMI_ISR_B0 REG8(MEC1322_EMI_RT_BASE + 0x8) +#define MEC1322_EMI_ISR_B1 REG8(MEC1322_EMI_RT_BASE + 0x9) +#define MEC1322_EMI_IMR_B0 REG8(MEC1322_EMI_RT_BASE + 0xa) +#define MEC1322_EMI_IMR_B1 REG8(MEC1322_EMI_RT_BASE + 0xb) + + +/* Mailbox */ +#define MEC1322_MBX_BASE 0x400f2500 +#define MEC1322_MBX_H2E_MBX REG8(MEC1322_MBX_BASE + 0x0) +#define MEC1322_MBX_E2H_MBX REG8(MEC1322_MBX_BASE + 0x4) +#define MEC1322_MBX_ISR REG8(MEC1322_MBX_BASE + 0x8) +#define MEC1322_MBX_IMR REG8(MEC1322_MBX_BASE + 0xc) +#define MEC1322_MBX_REG(x) REG8(MEC1322_MBX_BASE + 0x10 + (x)) + /* IRQ Numbers */ #define MEC1322_IRQ_I2C_0 0 #define MEC1322_IRQ_I2C_1 1 @@ -119,12 +190,36 @@ static inline uintptr_t gpio_port_base(int port_id) #define MEC1322_IRQ_EMI 14 #define MEC1322_IRQ_ACPIEC0_IBF 15 #define MEC1322_IRQ_ACPIEC0_OBF 16 +#define MEC1322_IRQ_ACPIEC1_IBF 17 +#define MEC1322_IRQ_ACPIEC1_OBF 18 +#define MEC1322_IRQ_ACPIPM1_CTL 19 +#define MEC1322_IRQ_ACPIPM1_EN 20 +#define MEC1322_IRQ_ACPIPM1_STS 21 +#define MEC1322_IRQ_8042EM_OBF 22 +#define MEC1322_IRQ_8042EM_IBF 23 +#define MEC1322_IRQ_MAILBOX 24 +#define MEC1322_IRQ_PECI_HOST 25 +#define MEC1322_IRQ_TACH_0 26 +#define MEC1322_IRQ_TACH_1 27 +#define MEC1322_IRQ_ADC_SNGL 28 +#define MEC1322_IRQ_ADC_RPT 29 +#define MEC1322_IRQ_PS2_0 32 +#define MEC1322_IRQ_PS2_1 33 +#define MEC1322_IRQ_PS2_2 34 +#define MEC1322_IRQ_PS2_3 35 +#define MEC1322_IRQ_SPI0_TX 36 +#define MEC1322_IRQ_SPI0_RX 37 +#define MEC1322_IRQ_HTIMER 38 +#define MEC1322_IRQ_KSC_INT 39 +#define MEC1322_IRQ_MAILBOX_DATA 40 #define MEC1322_IRQ_TIMER16_0 49 #define MEC1322_IRQ_TIMER16_1 50 #define MEC1322_IRQ_TIMER16_2 51 #define MEC1322_IRQ_TIMER16_3 52 #define MEC1322_IRQ_TIMER32_0 53 #define MEC1322_IRQ_TIMER32_1 54 +#define MEC1322_IRQ_SPI1_TX 55 +#define MEC1322_IRQ_SPI1_RX 56 #define MEC1322_IRQ_GIRQ8 57 #define MEC1322_IRQ_GIRQ9 58 #define MEC1322_IRQ_GIRQ10 59 |