Add a charger board

Using minimal runtime to fit the charger flash and RAM size.

It is currently more an experiment than the final layout written in the
stone.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=run on STM32F051 Discovery with
limited RAM and Flash to mimic STM32F031.

Change-Id: I10ee1decfd1f1448edbc909f0e997367921c4b53
Reviewed-on: https://chromium-review.googlesource.com/189405
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>

6 files changed, 343 insertions, 0 deletions

diff --git a/board/zinger/board.c b/board/zinger/board.c
new file mode 100644
index 0000000000..f48979dbd0
--- /dev/null
+++ b/board/zinger/board.c
@@ -0,0 +1,210 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Tiny charger configuration */
+
+#include "common.h"
+#include "debug.h"
+#include "registers.h"
+#include "timer.h"
+#include "util.h"
+
+static void clock_init(void)
+{
+	/* put 1 Wait-State for flash access to ensure proper reads at 48Mhz */
+	STM32_FLASH_ACR = 0x1001; /* 1 WS / Prefetch enabled */
+
+	/* Ensure that HSI8 is ON */
+	if (!(STM32_RCC_CR & (1 << 1))) {
+		/* Enable HSI */
+		STM32_RCC_CR |= 1 << 0;
+		/* Wait for HSI to be ready */
+		while (!(STM32_RCC_CR & (1 << 1)))
+			;
+	}
+	/* PLLSRC = HSI, PLLMUL = x12 (x HSI/2) = 48Mhz */
+	STM32_RCC_CFGR = 0x00288000;
+	/* Enable PLL */
+	STM32_RCC_CR |= 1 << 24;
+	/* Wait for PLL to be ready */
+	while (!(STM32_RCC_CR & (1 << 25)))
+			;
+
+	/* switch SYSCLK to PLL */
+	STM32_RCC_CFGR = 0x00288002;
+	/* wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+}
+
+static void power_init(void)
+{
+	/* enable SYSCFG, COMP, ADC, SPI1, USART1, TIM17 */
+	STM32_RCC_APB2ENR = 0x00045201;
+	/* enable TIM2, TIM14, PWR */
+	STM32_RCC_APB1ENR = 0x10000101;
+	/* enable DMA, SRAM, CRC, GPA, GPB, GPC, GPF */
+	STM32_RCC_AHBENR  = 0x4e0045;
+	/* TODO: remove GPC on real board */
+}
+
+/* GPIO setting helpers */
+#define OUT(n) (1 << ((n) * 2))
+#define AF(n) (2 << ((n) * 2))
+#define ANALOG(n) (3 << ((n) * 2))
+#define HIGH(n) (1 << (n))
+#define ODR(n) (1 << (n))
+#define HISPEED(n) (3 << ((n) * 2))
+#define AFx(n, x) (x << (((n) % 8) * 4))
+/* GPIO level setting helpers through BSRR register */
+#define GPIO_SET(n)   (1 << (n))
+#define GPIO_RESET(n) (1 << ((n) + 16))
+
+static void pins_init(void)
+{
+	/* Pin usage:
+	 * PA0  ()                 : Wakeup on Vnc / Threshold
+	 * PA1  (ANALOG - ADC_IN1) : CC sense
+	 * PA2  (ANALOG - ADC_IN2) : Current sense
+	 * PA3  (ANALOG - ADC_IN3) : Voltage sense
+	 * PA4  (OUT - OD GPIO)    : PD TX enable
+	 * PA5  (AF0 - SPI1_SCK)   : TX clock in
+	 * PA6  (AF0 - SPI1_MISO)  : PD TX
+	 * PA7  (AF5 - TIM17_CH1)  : PD RX
+	 * PA9  (AF1 - UART1_TX)   : [DEBUG] UART TX
+	 * PA10 (AF1 - UART1_RX)   : [DEBUG] UART RX
+	 * PA13 (OUT - GPIO)       : voltage select[0]
+	 * PA14 (OUT - GPIO)       : voltage select[1]
+	 * PB1  (AF0 - TIM14_CH1)  : TX clock out
+	 * PF0  (OUT - GPIO)       : LM5050 FET driver off
+	 * PF1  (OUT - GPIO)       : discharge FET
+	 */
+	STM32_GPIO_ODR(GPIO_A) = HIGH(4) | HIGH(6);
+	STM32_GPIO_AFRL(GPIO_A) = AFx(7, 5);
+	STM32_GPIO_AFRH(GPIO_A) = AFx(9, 1) | AFx(10, 1);
+	STM32_GPIO_OTYPER(GPIO_A) = ODR(4) | ODR(6);
+	STM32_GPIO_OSPEEDR(GPIO_A) = HISPEED(5) | HISPEED(6) | HISPEED(7);
+	STM32_GPIO_MODER(GPIO_A) = ANALOG(1) | ANALOG(2) | ANALOG(3) | OUT(4)
+				 | AF(5) /*| AF(6)*/ | AF(7) | AF(9) | AF(10)
+				 | OUT(13) | OUT(14);
+	/* set PF0 / PF1 as output, PF0 is open-drain, high by default */
+	STM32_GPIO_ODR(GPIO_F) = HIGH(0);
+	STM32_GPIO_MODER(GPIO_F) = OUT(0) | OUT(1);
+	STM32_GPIO_OTYPER(GPIO_F) = ODR(1);
+
+	/* Set PB1 as AF0 (TIM14_CH1) */
+	STM32_GPIO_OSPEEDR(GPIO_B) = HISPEED(1);
+	STM32_GPIO_MODER(GPIO_B) = AF(1);
+
+	/* --- dev board only --- */
+	/*
+	 * Blue LED    : PC8 (OUT)
+	 * Green LED   : PC9 (OUT)
+	 */
+	STM32_GPIO_ODR(GPIO_C) = HIGH(9);
+	STM32_GPIO_MODER(GPIO_C) = OUT(8) | OUT(9);
+}
+
+
+static void uart_init(void)
+{
+	/* set baudrate */
+	STM32_USART_BRR(UARTN) =
+		DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE);
+	/* UART enabled, 8 Data bits, oversampling x16, no parity */
+	STM32_USART_CR1(UARTN) =
+		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+	/* 1 stop bit, no fancy stuff */
+	STM32_USART_CR2(UARTN) = 0x0000;
+	/* DMA disabled, special modes disabled, error interrupt disabled */
+	STM32_USART_CR3(UARTN) = 0x0000;
+}
+
+static void timers_init(void)
+{
+	/* TIM2 is a 32-bit free running counter with 1Mhz frequency */
+	STM32_TIM_CR2(2) = 0x0000;
+	STM32_TIM32_ARR(2) = 0xFFFFFFFF;
+	STM32_TIM32_CNT(2) = 0;
+	STM32_TIM_PSC(2) = CPU_CLOCK / 1000000 - 1;
+	STM32_TIM_EGR(2) = 0x0001; /* Reload the pre-scaler */
+	STM32_TIM_CR1(2) = 1;
+}
+
+timestamp_t get_time(void)
+{
+	timestamp_t t;
+
+	t.le.lo = STM32_TIM32_CNT(2);
+	t.le.hi = 0;
+	return t;
+}
+
+void udelay(unsigned us)
+{
+	unsigned t0 = STM32_TIM32_CNT(2);
+	while ((STM32_TIM32_CNT(2) - t0) < us)
+		;
+}
+
+static void hardware_init(void)
+{
+	power_init();
+	clock_init();
+	pins_init();
+	uart_init();
+	timers_init();
+}
+
+/* ------------------------- Power supply control ------------------------ */
+
+/* Output voltage selection */
+enum volt {
+	VO_5V  = GPIO_RESET(13) | GPIO_RESET(14),
+	VO_12V = GPIO_SET(13)   | GPIO_RESET(14),
+	VO_13V = GPIO_RESET(13) | GPIO_SET(14),
+	VO_20V = GPIO_SET(13)   | GPIO_SET(14),
+};
+
+static inline void set_output_voltage(enum volt v)
+{
+	/* set voltage_select on PA13/PA14 */
+	STM32_GPIO_BSRR(GPIO_A) = v;
+}
+
+static inline void output_enable(void)
+{
+	/* GPF0 (FET driver shutdown) = 0 */
+	STM32_GPIO_BSRR(GPIO_F) = GPIO_RESET(0);
+}
+
+static inline void output_disable(void)
+{
+	/* GPF0 (FET driver shutdown) = 1 */
+	STM32_GPIO_BSRR(GPIO_F) = GPIO_SET(0);
+}
+
+/* default forced output voltage */
+#define VO_DEFAULT VO_12V
+
+int main(void)
+{
+	hardware_init();
+	debug_printf("Power supply started ...\n");
+
+	set_output_voltage(VO_DEFAULT);
+	debug_printf("set output voltage : " STRINGIFY(VO_DEFAULT) "\n");
+	output_enable();
+
+	while (1) {
+		/* magic LED blinker on the test board */
+		STM32_GPIO_BSRR(GPIO_C) = GPIO_SET(8);
+		udelay(200000);
+		STM32_GPIO_BSRR(GPIO_C) = GPIO_RESET(8);
+		udelay(750000);
+		debug_printf("%T ALIVE\n");
+	}
+	while (1)
+		;
+}
diff --git a/board/zinger/board.h b/board/zinger/board.h
new file mode 100644
index 0000000000..fccdb2a01e
--- /dev/null
+++ b/board/zinger/board.h
@@ -0,0 +1,43 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Tiny charger configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART1 (PA9/PA10) */
+#define CONFIG_UART_CONSOLE 1
+
+/* Optional features */
+#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TASK_PROFILING
+#undef CONFIG_COMMON_GPIO
+#undef CONFIG_COMMON_PANIC_OUTPUT
+#undef CONFIG_COMMON_RUNTIME
+#undef CONFIG_COMMON_TIMER
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_EXCEPTIONS
+#undef CONFIG_DEBUG_STACK_OVERFLOW
+#undef CONFIG_FLASH
+#undef CONFIG_FMAP
+
+/* debug printf flash footprinf is about 1400 bytes */
+#define CONFIG_DEBUG_PRINTF
+#define UARTN CONFIG_UART_CONSOLE
+
+#ifndef __ASSEMBLER__
+
+/* No GPIO abstraction layer */
+enum gpio_signal;
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
diff --git a/board/zinger/build.mk b/board/zinger/build.mk
new file mode 100644
index 0000000000..9a1249744a
--- /dev/null
+++ b/board/zinger/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F031F6
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f03x
+
+board-y=board.o
+board-$(CONFIG_DEBUG_PRINTF)+=debug.o
diff --git a/board/zinger/debug.c b/board/zinger/debug.c
new file mode 100644
index 0000000000..2cf62996bf
--- /dev/null
+++ b/board/zinger/debug.c
@@ -0,0 +1,41 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Synchronous UART debug printf */
+
+#include "common.h"
+#include "printf.h"
+#include "registers.h"
+#include "util.h"
+
+static int debug_txchar(void *context, int c)
+{
+	if (c == '\n') {
+		while (!(STM32_USART_SR(UARTN) & STM32_USART_SR_TXE))
+			;
+		STM32_USART_TDR(UARTN) = '\r';
+	}
+
+	/* Wait for space to transmit */
+	while (!(STM32_USART_SR(UARTN) & STM32_USART_SR_TXE))
+		;
+	STM32_USART_TDR(UARTN) = c;
+
+	return 0;
+}
+
+
+
+void debug_printf(const char *format, ...)
+{
+	va_list args;
+
+	va_start(args, format);
+	vfnprintf(debug_txchar, NULL, format, args);
+	va_end(args);
+}
+
+void panic(const char *msg)
+{
+}
diff --git a/board/zinger/debug.h b/board/zinger/debug.h
new file mode 100644
index 0000000000..fcc000a20d
--- /dev/null
+++ b/board/zinger/debug.h
@@ -0,0 +1,16 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Synchronous UART debug printf */
+
+#ifndef __BOARD_ZINGER_DEBUG_H
+#define __BOARD_ZINGER_DEBUG_H
+
+#ifdef CONFIG_DEBUG_PRINTF
+void debug_printf(const char *format, ...);
+#else
+#define debug_printf(...)
+#endif
+
+#endif /* __BOARD_ZINGER_DEBUG_H */
diff --git a/board/zinger/ec.tasklist b/board/zinger/ec.tasklist
new file mode 100644
index 0000000000..e8860b4ebb
--- /dev/null
+++ b/board/zinger/ec.tasklist
@@ -0,0 +1,19 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST