summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorBill Richardson <wfrichar@chromium.org>2014-05-15 12:56:30 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-07-16 07:16:51 +0000
commit41c749d9d829a601011d38bb93b546363d8f1758 (patch)
tree94ce7371de375f7304cfb0854d08e6bbd9af123e
parent241cc626850175acac7a2e95cddbeb269f75c1ba (diff)
downloadchrome-ec-41c749d9d829a601011d38bb93b546363d8f1758.tar.gz
Samus: Reduce S3S0 signal delay to 5ms.
With only mini-PCIe devices, we don't need to wait for the full 99ms that PCIe devices require. BUG=chrome-os-partner:25530 BRANCH=ToT TEST=manual Log in, connect to the web via WiFi. Close the lid, wait a bit, open the lid. WiFi should resume and still work. Change-Id: I24d6ae95607f8f9a0fa70aebf5eaa0ebd68260f6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200084 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--board/samus/power_sequence.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/board/samus/power_sequence.c b/board/samus/power_sequence.c
index 3f7b5578b5..aabb83d78d 100644
--- a/board/samus/power_sequence.c
+++ b/board/samus/power_sequence.c
@@ -340,8 +340,12 @@ enum power_state power_handle_state(enum power_state state)
*/
disable_sleep(SLEEP_MASK_AP_RUN);
- /* Wait 99ms after all voltages good */
- msleep(99);
+ /*
+ * Wait a bit for all voltages to be good. PCIe devices need
+ * 99ms, but mini-PCIe devices only need 1ms. Intel recommends
+ * at least 5ms between ALL_SYS_PWRGD and SYS_PWROK.
+ */
+ msleep(5);
/*
* Throttle CPU if necessary. This should only be asserted