stm32: change USART register macros to take a base address

Previously these macros took a small integer to identify the USART
to access.  This integer was token concatenated to form the macro
name that resolved to the base address.  This made it imposible to
use these macros in a driver that could manage more than one USART
because there was no runtime way to go from base address (or other
unique identifier) to register address.

This change makes it possible to pass either a static compile time
known base address or a runtime variable with the base address,
thus supporting either sort of driver.  The existing USART driver
has been updated to compute the base address of the console USART
and pass that at compile time, resulting in no increase in code
size.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=none
TEST=make buildall -j
     Followed by manual testing of console over UART functionality
     on the STM32F072 based discovery board.

Change-Id: I06547a173b1e5cf625a57019ea4b8a84d1768444
Reviewed-on: https://chromium-review.googlesource.com/208488
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>

2 files changed, 55 insertions, 56 deletions

diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 21a44caa78..c46f98bd72 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -145,15 +145,13 @@
 #define STM32_USART1_BASE          0x40013800
 #define STM32_USART2_BASE          0x40004400
 #define STM32_USART3_BASE          0x40004800
-#define STM32_UART4_BASE           0x40004c00 /* STM32F100 and STM32F10x */
-#define STM32_UART5_BASE           0x40005000 /* STM32F100 and STM32F10x */
+#define STM32_USART4_BASE          0x40004c00
 
-#define STM32_USART_BASE(n)        CONCAT3(STM32_USART, n, _BASE)
-
-#define STM32_USART_REG(n, offset) REG16(STM32_USART_BASE(n) + (offset))
+#define STM32_USART_BASE(n)           CONCAT3(STM32_USART, n, _BASE)
+#define STM32_USART_REG(base, offset) REG16((base) + (offset))
 
 #ifdef CHIP_FAMILY_STM32F0
-#define STM32_USART_CR1(n)         STM32_USART_REG(n, 0x00)
+#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
 #define STM32_USART_CR1_UE		(1 << 0)
 #define STM32_USART_CR1_RE		(1 << 2)
 #define STM32_USART_CR1_TE		(1 << 3)
@@ -161,32 +159,32 @@
 #define STM32_USART_CR1_TCIE		(1 << 6)
 #define STM32_USART_CR1_TXEIE		(1 << 7)
 #define STM32_USART_CR1_OVER8		(1 << 15)
-#define STM32_USART_CR2(n)         STM32_USART_REG(n, 0x04)
-#define STM32_USART_CR3(n)         STM32_USART_REG(n, 0x08)
+#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
 #define STM32_USART_CR3_DMAR		(1 << 6)
 #define STM32_USART_CR3_DMAT		(1 << 7)
 #define STM32_USART_CR3_ONEBIT		(1 << 11)
-#define STM32_USART_BRR(n)         STM32_USART_REG(n, 0x0C)
-#define STM32_USART_GTPR(n)        STM32_USART_REG(n, 0x10)
-#define STM32_USART_RTOR(n)        STM32_USART_REG(n, 0x14)
-#define STM32_USART_RQR(n)         STM32_USART_REG(n, 0x18)
-#define STM32_USART_ISR(n)         STM32_USART_REG(n, 0x1C)
-#define STM32_USART_ICR(n)         STM32_USART_REG(n, 0x20)
-#define STM32_USART_RDR(n)         STM32_USART_REG(n, 0x24)
-#define STM32_USART_TDR(n)         STM32_USART_REG(n, 0x28)
+#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
+#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
 /* register alias */
-#define STM32_USART_SR(n)          STM32_USART_ISR(n)
+#define STM32_USART_SR(base)       STM32_USART_ISR(base)
 #define STM32_USART_SR_RXNE		(1 << 5)
 #define STM32_USART_SR_TC		(1 << 6)
 #define STM32_USART_SR_TXE		(1 << 7)
 #else /* !CHIP_FAMILY_STM32F0 */
-#define STM32_USART_SR(n)          STM32_USART_REG(n, 0x00)
+#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
 #define STM32_USART_SR_RXNE		(1 << 5)
 #define STM32_USART_SR_TC		(1 << 6)
 #define STM32_USART_SR_TXE		(1 << 7)
-#define STM32_USART_DR(n)          STM32_USART_REG(n, 0x04)
-#define STM32_USART_BRR(n)         STM32_USART_REG(n, 0x08)
-#define STM32_USART_CR1(n)         STM32_USART_REG(n, 0x0C)
+#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
+#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
 #define STM32_USART_CR1_RE		(1 << 2)
 #define STM32_USART_CR1_TE		(1 << 3)
 #define STM32_USART_CR1_RXNEIE		(1 << 5)
@@ -194,15 +192,15 @@
 #define STM32_USART_CR1_TXEIE		(1 << 7)
 #define STM32_USART_CR1_UE		(1 << 13)
 #define STM32_USART_CR1_OVER8		(1 << 15) /* STM32L only */
-#define STM32_USART_CR2(n)         STM32_USART_REG(n, 0x10)
-#define STM32_USART_CR3(n)         STM32_USART_REG(n, 0x14)
+#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
+#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
 #define STM32_USART_CR3_DMAR		(1 << 6)
 #define STM32_USART_CR3_DMAT		(1 << 7)
 #define STM32_USART_CR3_ONEBIT		(1 << 11) /* STM32L only */
-#define STM32_USART_GTPR(n)        STM32_USART_REG(n, 0x18)
+#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
 /* register aliases */
-#define STM32_USART_TDR(n)         STM32_USART_DR(n)
-#define STM32_USART_RDR(n)         STM32_USART_DR(n)
+#define STM32_USART_TDR(base)      STM32_USART_DR(base)
+#define STM32_USART_RDR(base)      STM32_USART_DR(base)
 #endif /* !CHIP_FAMILY_STM32F0 */
 
 #define STM32_IRQ_USART(n)         CONCAT2(STM32_IRQ_USART, n)
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c
index 6221b62e9e..2e3d875243 100644
--- a/chip/stm32/uart.c
+++ b/chip/stm32/uart.c
@@ -17,14 +17,15 @@
 #include "util.h"
 
 /* Console USART index */
-#define UARTN CONFIG_UART_CONSOLE
+#define UARTN      CONFIG_UART_CONSOLE
+#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
 
 #ifdef CONFIG_UART_TX_DMA
 #define UART_TX_INT_ENABLE STM32_USART_CR1_TCIE
 
 /* DMA channel options; assumes UART1 */
 static const struct dma_option dma_tx_option = {
-	STM32_DMAC_USART1_TX, (void *)&STM32_USART_TDR(UARTN),
+	STM32_DMAC_USART1_TX, (void *)&STM32_USART_TDR(UARTN_BASE),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 };
 
@@ -35,7 +36,7 @@ static const struct dma_option dma_tx_option = {
 #ifdef CONFIG_UART_RX_DMA
 /* DMA channel options; assumes UART1 */
 static const struct dma_option dma_rx_option = {
-	STM32_DMAC_USART1_RX, (void *)&STM32_USART_RDR(UARTN),
+	STM32_DMAC_USART1_RX, (void *)&STM32_USART_RDR(UARTN_BASE),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
 	STM32_DMA_CCR_CIRC
 };
@@ -54,38 +55,38 @@ int uart_init_done(void)
 void uart_tx_start(void)
 {
 	/* If interrupt is already enabled, nothing to do */
-	if (STM32_USART_CR1(UARTN) & UART_TX_INT_ENABLE)
+	if (STM32_USART_CR1(UARTN_BASE) & UART_TX_INT_ENABLE)
 		return;
 
 	disable_sleep(SLEEP_MASK_UART);
 	should_stop = 0;
-	STM32_USART_CR1(UARTN) |= UART_TX_INT_ENABLE;
+	STM32_USART_CR1(UARTN_BASE) |= UART_TX_INT_ENABLE;
 	task_trigger_irq(STM32_IRQ_USART(UARTN));
 }
 
 void uart_tx_stop(void)
 {
-	STM32_USART_CR1(UARTN) &= ~UART_TX_INT_ENABLE;
+	STM32_USART_CR1(UARTN_BASE) &= ~UART_TX_INT_ENABLE;
 	should_stop = 1;
 	enable_sleep(SLEEP_MASK_UART);
 }
 
 void uart_tx_flush(void)
 {
-	while (!(STM32_USART_SR(UARTN) & STM32_USART_SR_TXE))
+	while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE))
 		;
 }
 
 int uart_tx_ready(void)
 {
-	return STM32_USART_SR(UARTN) & STM32_USART_SR_TXE;
+	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE;
 }
 
 #ifdef CONFIG_UART_TX_DMA
 
 int uart_tx_dma_ready(void)
 {
-	return STM32_USART_SR(UARTN) & STM32_USART_SR_TC;
+	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC;
 }
 
 void uart_tx_dma_start(const char *src, int len)
@@ -94,10 +95,10 @@ void uart_tx_dma_start(const char *src, int len)
 	dma_prepare_tx(&dma_tx_option, len, src);
 
 	/* Force clear TC so we don't re-interrupt */
-	STM32_USART_SR(UARTN) &= ~STM32_USART_SR_TC;
+	STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC;
 
 	/* Enable TCIE (chrome-os-partner:28837) */
-	STM32_USART_CR1(UARTN) |= STM32_USART_CR1_TCIE;
+	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TCIE;
 
 	/* Start DMA */
 	dma_go(dma_get_channel(dma_tx_option.channel));
@@ -107,7 +108,7 @@ void uart_tx_dma_start(const char *src, int len)
 
 int uart_rx_available(void)
 {
-	return STM32_USART_SR(UARTN) & STM32_USART_SR_RXNE;
+	return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_RXNE;
 }
 
 #ifdef CONFIG_UART_RX_DMA
@@ -133,12 +134,12 @@ void uart_write_char(char c)
 	while (!uart_tx_ready())
 		;
 
-	STM32_USART_TDR(UARTN) = c;
+	STM32_USART_TDR(UARTN_BASE) = c;
 }
 
 int uart_read_char(void)
 {
-	return STM32_USART_RDR(UARTN);
+	return STM32_USART_RDR(UARTN_BASE);
 }
 
 void uart_disable_interrupt(void)
@@ -156,14 +157,14 @@ void uart_interrupt(void)
 {
 #ifdef CONFIG_UART_TX_DMA
 	/* Disable transmission complete interrupt if DMA done */
-	if (STM32_USART_SR(UARTN) & STM32_USART_SR_TC)
-		STM32_USART_CR1(UARTN) &= ~STM32_USART_CR1_TCIE;
+	if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC)
+		STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE;
 #else
 	/*
 	 * Disable the TX empty interrupt before filling the TX buffer since it
 	 * needs an actual write to DR to be cleared.
 	 */
-	STM32_USART_CR1(UARTN) &= ~STM32_USART_CR1_TXEIE;
+	STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TXEIE;
 #endif
 
 #ifndef CONFIG_UART_RX_DMA
@@ -183,7 +184,7 @@ void uart_interrupt(void)
 	 * uart_process_output().
 	 */
 	if (!should_stop)
-		STM32_USART_CR1(UARTN) |= STM32_USART_CR1_TXEIE;
+		STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TXEIE;
 #endif
 }
 DECLARE_IRQ(STM32_IRQ_USART(UARTN), uart_interrupt, 2);
@@ -201,19 +202,19 @@ static void uart_freq_change(void)
 		 * CPU clock is high enough to support x16 oversampling.
 		 * BRR = (div mantissa)<<4 | (4-bit div fraction)
 		 */
-		STM32_USART_CR1(UARTN) &= ~STM32_USART_CR1_OVER8;
-		STM32_USART_BRR(UARTN) = div;
+		STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_OVER8;
+		STM32_USART_BRR(UARTN_BASE) = div;
 	} else {
 		/*
 		 * CPU clock is low; use x8 oversampling.
 		 * BRR = (div mantissa)<<4 | (3-bit div fraction)
 		 */
-		STM32_USART_BRR(UARTN) = ((div / 8) << 4) | (div & 7);
-		STM32_USART_CR1(UARTN) |= STM32_USART_CR1_OVER8;
+		STM32_USART_BRR(UARTN_BASE) = ((div / 8) << 4) | (div & 7);
+		STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_OVER8;
 	}
 #else
 	/* STM32F only supports x16 oversampling */
-	STM32_USART_BRR(UARTN) = div;
+	STM32_USART_BRR(UARTN_BASE) = div;
 #endif
 
 }
@@ -235,31 +236,31 @@ void uart_init(void)
 	 * UART enabled, 8 Data bits, oversampling x16, no parity,
 	 * TX and RX enabled.
 	 */
-	STM32_USART_CR1(UARTN) =
+	STM32_USART_CR1(UARTN_BASE) =
 		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
 
 	/* 1 stop bit, no fancy stuff */
-	STM32_USART_CR2(UARTN) = 0x0000;
+	STM32_USART_CR2(UARTN_BASE) = 0x0000;
 
 #ifdef CONFIG_UART_TX_DMA
 	/* Enable DMA transmitter */
-	STM32_USART_CR3(UARTN) |= STM32_USART_CR3_DMAT;
+	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAT;
 #else
 	/* DMA disabled, special modes disabled, error interrupt disabled */
-	STM32_USART_CR3(UARTN) = 0x0000;
+	STM32_USART_CR3(UARTN_BASE) = 0x0000;
 #endif
 
 #ifdef CONFIG_UART_RX_DMA
 	/* Enable DMA receiver */
-	STM32_USART_CR3(UARTN) |= STM32_USART_CR3_DMAR;
+	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAR;
 #else
 	/* Enable receive-not-empty interrupt */
-	STM32_USART_CR1(UARTN) |= STM32_USART_CR1_RXNEIE;
+	STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_RXNEIE;
 #endif
 
 #ifdef CHIP_FAMILY_STM32L
 	/* Use single-bit sampling */
-	STM32_USART_CR3(UARTN) |= STM32_USART_CR3_ONEBIT;
+	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_ONEBIT;
 #endif
 
 	/* Set initial baud rate */