cortex-m0: stm32f0: use RW vector table when running RW code

Currently, on stm32f cortex-m0 systems, interrupts are always being
directed to the RO vector table. This can cause strange problems when
running RW software because it is still calling IRQ handlers in the RO
code.

Unfortunately, on cortex-m0 the ability to specify the vector table
location in flash (VTOR register) is optional, and stm32f0 parts do not
have it. Instead, in order to run RW IRQ handlers, at init time, this
CL copies the vector table from flash to the base address of SRAM
(0x20000000), and then selects SRAM to be mapped to 0x00000000 where
the core looks to find the vector table.

BUG=none
BRANCH=none
TEST=Tested on zinger.
- Verified that vector table is copied to SRAM by printing out 48 words
from SRAM base address 0x20000000 in main() and verifying that it matches
the vector table in flash in the disassembly.
- Verified the vector table at SRAM 0x20000000 points to the RW handlers
when in RW and the RO handlers when in RO.
- Also printed out PC in one IRQ handler and verified it was in the
appropriate section of code.

Also, ran on samus_pd and did a sysjump RW to make sure at least one other
system works.

Change-Id: I22aff1b5e0de9b23fd3324f0cbe4f6c45a81967e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210063
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

2 files changed, 41 insertions, 12 deletions

diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index beb819afa6..0eb80252e1 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -153,14 +153,13 @@ SECTIONS
 
     .bss : {
 	/*
-	 * Align to 512 bytes. This is convenient when some memory block
-	 * need big alignment. When COMPILE_FOR_RAM is not set, this is the
-	 * beginning of the RAM, so there is usually no penalty on aligning
-	 * this.
+	 * Vector table must be at the beginning of bss section. The vector
+	 * table section contains a RAM copy of the vector table used on
+	 * STM chips for relocating the vector table.
 	 */
-        . = ALIGN(512);
-        __bss_start = .;
-	*(.bss.big_align)
+	. = ALIGN(8);
+	__bss_start = .;
+	*(.bss.vector_table)
 	/* Stacks must be 64-bit aligned */
         . = ALIGN(8);
         *(.bss.system_stack)
diff --git a/core/cortex-m0/init.S b/core/cortex-m0/init.S
index 92dc386959..040d61be96 100644
--- a/core/cortex-m0/init.S
+++ b/core/cortex-m0/init.S
@@ -72,6 +72,12 @@ vector_irq 29                     @ IRQ  29 handler
 vector_irq 30                     @ IRQ  30 handler
 vector_irq 31                     @ IRQ  31 handler
 
+#ifdef CHIP_FAMILY_STM32F0
+/* Allocate space for SRAM vector table at SRAM based address */
+.section .bss.vector_table
+sram_vtable: .skip (48*4)
+#endif
+
 .text
 .syntax unified
 .code 16
@@ -87,11 +93,6 @@ reset:
 	msr control, r0
 	isb                  @ ensure the write is done
 
-	/* Set the vector table on our current code */
-	ldr r1, =vectors
-	ldr r2, =0xE000ED08   /* VTABLE register in SCB*/
-	str r1, [r2]
-
 	/* Clear BSS */
 	movs r0, #0
 	ldr  r1,_bss_start
@@ -102,6 +103,35 @@ bss_loop:
 	cmp  r1, r2
 	blt bss_loop
 
+#ifdef CHIP_FAMILY_STM32F0
+	/*
+	 * STM32F0 parts don't have the VTOR register for relocating
+	 * the vector table. Instead, we must copy the vector table from
+	 * flash into SRAM.
+	 */
+	ldr r1, =vectors
+	ldr r2, =sram_vtable
+	movs r0, #0
+vtable_loop:
+	ldr r3, [r1]
+	str r3, [r2]
+	adds r1, #4
+	adds r2, #4
+	adds r0, #1
+	cmp r0, #48
+	blt vtable_loop
+
+	/* Set SYSCFG_CFGR1 mem_mode to load vector table from SRAM */
+	movs r0, #3
+	ldr r1, =0x40010000
+	str r0, [r1]
+#else
+	/* Set the vector table on our current code */
+	ldr r1, =vectors
+	ldr r2, =0xE000ED08   /* VTOR register in SCB*/
+	str r1, [r2]
+#endif
+
 #ifndef COMPILE_FOR_RAM
 	/* Copy initialized data to Internal RAM */
 	ldr r0,_ro_end