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authorVic Yang <victoryang@chromium.org>2014-07-25 17:05:16 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-07-29 00:02:47 +0000
commitf4ebbb821ba20340f98c4602d5034be44f53de6c (patch)
tree9b46df565759e0e2eba2fb70f9af4a036be50012
parentf307874380e972fba9e0e1bdd6a90f796a777290 (diff)
downloadchrome-ec-f4ebbb821ba20340f98c4602d5034be44f53de6c.tar.gz
stm32f0: Fix EC slave I2C interrupt
The interrupt handler is hardcoded to I2C1. We should choose between I2C1 and I2C2 based on I2C_PORT_EC. BUG=chrome-os-partner:30707 TEST=On Ryu, ectool hello and see ACK. BRANCH=None Change-Id: I07055b0ee7459e6cac5585737e200ff2d5814a34 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209960 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
-rw-r--r--chip/stm32/i2c-stm32f0.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c
index fb669a52c7..e042befa10 100644
--- a/chip/stm32/i2c-stm32f0.c
+++ b/chip/stm32/i2c-stm32f0.c
@@ -32,6 +32,14 @@
*/
#define I2C_MAX_HOST_PACKET_SIZE 128
+#ifdef HAS_TASK_HOSTCMD
+#if (I2C_PORT_EC == STM32_I2C1_PORT)
+#define IRQ_SLAVE STM32_IRQ_I2C1
+#else
+#define IRQ_SLAVE STM32_IRQ_I2C2
+#endif
+#endif
+
/**
* Wait for ISR register to contain the specified mask.
*
@@ -261,7 +269,7 @@ static void i2c_event_handler(int port)
}
}
void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
-DECLARE_IRQ(STM32_IRQ_I2C1, i2c2_event_interrupt, 2);
+DECLARE_IRQ(IRQ_SLAVE, i2c2_event_interrupt, 2);
#endif
/*****************************************************************************/
@@ -424,7 +432,7 @@ static void i2c_init(void)
STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE;
STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 | CONFIG_HOSTCMD_I2C_SLAVE_ADDR;
- task_enable_irq(STM32_IRQ_I2C1);
+ task_enable_irq(IRQ_SLAVE);
#endif
}
DECLARE_HOOK(HOOK_INIT, i2c_init, HOOK_PRIO_DEFAULT);