stm32f: Add DMA interrupt handlers for channel 1 to 3

We already have interrupt handlers for channel 4 to 7. We need channel 3
for the new Ryu boards. Add the handlers for channel 1 to 3. Also,
instead of copy-pasting interrupt handlers, define a macro and declare
interrupt handlers with it.

BRANCH=None
BUG=chrome-os-partner:32660
TEST=make buildall
TEST=Check PD communication on the new Ryu board (with other CLs to
enable the new boards.)

Change-Id: I51d6bd16739f31a7efbeb4ec19bb91a1546fe21d
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224175
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

4 files changed, 23 insertions, 33 deletions

diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c
index 290013ed8d..d151d3044f 100644
--- a/chip/stm32/dma.c
+++ b/chip/stm32/dma.c
@@ -292,36 +292,23 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 3);
 
 #else /* !CHIP_FAMILY_STM32F0 */
 
-void dma_event_interrupt_channel_4(void)
-{
-	dma_clear_isr(STM32_DMAC_CH4);
-	if (id[STM32_DMAC_CH4] != TASK_ID_INVALID)
-		task_wake(id[STM32_DMAC_CH4]);
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4, dma_event_interrupt_channel_4, 3);
-
-void dma_event_interrupt_channel_5(void)
-{
-	dma_clear_isr(STM32_DMAC_CH5);
-	if (id[STM32_DMAC_CH5] != TASK_ID_INVALID)
-		task_wake(id[STM32_DMAC_CH5]);
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_5, dma_event_interrupt_channel_5, 3);
+#define DECLARE_DMA_IRQ(x) \
+	void CONCAT2(dma_event_interrupt_channel_, x)(void) \
+	{ \
+		dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \
+		if (id[CONCAT2(STM32_DMAC_CH, x)] != TASK_ID_INVALID) \
+			task_wake(id[CONCAT2(STM32_DMAC_CH, x)]); \
+	} \
+	DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \
+		    CONCAT2(dma_event_interrupt_channel_, x), 3);
+
+DECLARE_DMA_IRQ(1);
+DECLARE_DMA_IRQ(2);
+DECLARE_DMA_IRQ(3);
+DECLARE_DMA_IRQ(4);
+DECLARE_DMA_IRQ(5);
+DECLARE_DMA_IRQ(6);
+DECLARE_DMA_IRQ(7);
 
-void dma_event_interrupt_channel_6(void)
-{
-	dma_clear_isr(STM32_DMAC_CH6);
-	if (id[STM32_DMAC_CH6] != TASK_ID_INVALID)
-		task_wake(id[STM32_DMAC_CH6]);
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_6, dma_event_interrupt_channel_6, 3);
-
-void dma_event_interrupt_channel_7(void)
-{
-	dma_clear_isr(STM32_DMAC_CH7);
-	if (id[STM32_DMAC_CH7] != TASK_ID_INVALID)
-		task_wake(id[STM32_DMAC_CH7]);
-}
-DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_7, dma_event_interrupt_channel_7, 3);
 #endif /* CHIP_FAMILY_STM32F0 */
 #endif /* CONFIG_DMA_DEFAULT_HANDLERS */
diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h
index 098e9850ef..2b49de15e1 100644
--- a/core/cortex-m/irq_handler.h
+++ b/core/cortex-m/irq_handler.h
@@ -21,7 +21,8 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)                     \
+#define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
+#define DECLARE_IRQ_(irq, routine, priority)                    \
 	void IRQ_HANDLER(irq)(void) __attribute__((naked));	\
 	void IRQ_HANDLER(irq)(void)				\
 	{							\
diff --git a/core/cortex-m0/irq_handler.h b/core/cortex-m0/irq_handler.h
index 77816949d0..442c20ac00 100644
--- a/core/cortex-m0/irq_handler.h
+++ b/core/cortex-m0/irq_handler.h
@@ -25,7 +25,8 @@ extern int need_resched_or_profiling;
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)                     \
+#define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
+#define DECLARE_IRQ_(irq, routine, priority)                    \
 	void IRQ_HANDLER(irq)(void) __attribute__((naked));	\
 	void IRQ_HANDLER(irq)(void)				\
 	{							\
diff --git a/include/task.h b/include/task.h
index 63986627c5..1ec546fdb1 100644
--- a/include/task.h
+++ b/include/task.h
@@ -240,7 +240,8 @@ struct irq_priority {
 #else
 #define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
 #define IRQ_HANDLER_OPT(irqname) CONCAT3(irq_, irqname, _handler_optional)
-#define DECLARE_IRQ(irq, routine, priority) \
+#define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
+#define DECLARE_IRQ_(irq, routine, priority) \
 	void IRQ_HANDLER_OPT(irq)(void) __attribute__((alias(#routine)));
 
 /* Include ec.irqlist here for compilation dependency */