diff options
| author | Vic Yang <victoryang@chromium.org> | 2014-10-29 11:36:05 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-30 00:05:33 +0000 |
| commit | cfbb9e51b2abfd562af865c0b11362d48d799cfd (patch) | |
| tree | bc012cac932b2068a63633636b2dc43f8b3dcd18 | |
| parent | e254b0a06f6c5387a77d5a391bf4f7c8016f84b6 (diff) | |
| download | chrome-ec-cfbb9e51b2abfd562af865c0b11362d48d799cfd.tar.gz | |
ryu: Enable low power idle for P2 boards
Now that the problem with UART in STOP mode is fixed, let's enable low
power idle for Ryu P2 boards.
BRANCH=None
BUG=chrome-os-partner:33219
TEST=Shut down the AP and unplug AC power. Check the EC goes into
deep-sleep by 'idlestat'.
TEST=Power up the AP and check the EC stays awake.
Change-Id: Ib8ad3763407315ec0f95551fa0fdd258a060e113
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226312
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
| -rw-r--r-- | board/ryu_p2/board.h | 2 | ||||
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 7 |
2 files changed, 7 insertions, 2 deletions
diff --git a/board/ryu_p2/board.h b/board/ryu_p2/board.h index 21118df836..8e708b97c4 100644 --- a/board/ryu_p2/board.h +++ b/board/ryu_p2/board.h @@ -19,6 +19,7 @@ #define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_USBPD)) /* Optional features */ +#define CONFIG_FORCE_CONSOLE_RESUME #define CONFIG_STM_HWTIMER32 #define CONFIG_USB_POWER_DELIVERY #define CONFIG_USB_PD_DUAL_ROLE @@ -30,6 +31,7 @@ #define CONFIG_HW_CRC #define CONFIG_I2C #define CONFIG_LID_SWITCH +#define CONFIG_LOW_POWER_IDLE #define CONFIG_VBOOT_HASH #define CONFIG_WATCHDOG_HELP #undef CONFIG_TASK_PROFILING diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 4272349971..81cea8c884 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -41,8 +41,12 @@ static int dsleep_recovery_margin_us = 1000000; * power mode is 5 us + PLL locking time is 200us. * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. if we set the alarm * in the past, it will never wake up and cause a watchdog. + * For STM32F3, we are using HSE, which requires additional time to start up. + * Therefore, the latency for STM32F3 is set longer. */ -#if (CPU_CLOCK == PLL_CLOCK) +#ifdef CHIP_VARIANT_STM32F373 +#define STOP_MODE_LATENCY 500 /* us */ +#elif (CPU_CLOCK == PLL_CLOCK) #define STOP_MODE_LATENCY 300 /* us */ #else #define STOP_MODE_LATENCY 50 /* us */ @@ -214,7 +218,6 @@ static void config_hispeed_clock(void) * ADCCLK = PCLK / 6 = 4MHz * USB uses SYSCLK = 48MHz */ - /*STM32_RCC_CFGR = 0x0041a400;*/ STM32_RCC_CFGR = 0x0041a400; /* Enable the PLL */ |