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authorAnton Staaf <robotboy@chromium.org>2014-12-02 10:42:22 -0800
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-12-08 21:51:59 +0000
commit9e1f4ed7015ac8543169fe41b74f1939a8b86f3b (patch)
tree96e0dbba21fffbb74f8c1b2420c58541501f5b0f
parent731a2e74872159ecfa910c3174e9d3ae50ff2dae (diff)
downloadchrome-ec-9e1f4ed7015ac8543169fe41b74f1939a8b86f3b.tar.gz
USB-SPI: Switch from task to deferred function
The task based approach made sense when it looked like there would be a case closed debugging task to handle multiple bridges (SPI/I2C/USART...). I'm not convinced anymore that that task will be needed, so this simplification seems good. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ic431c287c28d10252246fe9f507d9c5fcc64a077 Reviewed-on: https://chromium-review.googlesource.com/232733 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
-rw-r--r--board/discovery-stm32f072/board.c4
-rw-r--r--board/discovery-stm32f072/build.mk2
-rw-r--r--board/discovery-stm32f072/ec.tasklist1
-rw-r--r--board/discovery-stm32f072/spi.c29
-rw-r--r--chip/stm32/usb_spi.c15
-rw-r--r--chip/stm32/usb_spi.h35
6 files changed, 23 insertions, 63 deletions
diff --git a/board/discovery-stm32f072/board.c b/board/discovery-stm32f072/board.c
index 99e0af0b1d..c6a9b3c8a3 100644
--- a/board/discovery-stm32f072/board.c
+++ b/board/discovery-stm32f072/board.c
@@ -87,9 +87,13 @@ void usb_spi_board_disable(struct usb_spi_config const *config)
gpio_config_module(MODULE_SPI_MASTER, 0);
}
+USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI);
+
/* Initialize board. */
static void board_init(void)
{
gpio_enable_interrupt(GPIO_USER_BUTTON);
+
+ usb_spi_enable(&usb_spi, 1);
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/discovery-stm32f072/build.mk b/board/discovery-stm32f072/build.mk
index 7a40d5fc10..d8a22a6ad5 100644
--- a/board/discovery-stm32f072/build.mk
+++ b/board/discovery-stm32f072/build.mk
@@ -10,4 +10,4 @@ CHIP:=stm32
CHIP_FAMILY:=stm32f0
CHIP_VARIANT:=stm32f07x
-board-y=board.o echo.o spi.o
+board-y=board.o echo.o
diff --git a/board/discovery-stm32f072/ec.tasklist b/board/discovery-stm32f072/ec.tasklist
index 73f7aa6835..6a623f151c 100644
--- a/board/discovery-stm32f072/ec.tasklist
+++ b/board/discovery-stm32f072/ec.tasklist
@@ -19,5 +19,4 @@
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
- TASK_ALWAYS(USB_SPI, usb_spi_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(ECHO, echo_task, NULL, TASK_STACK_SIZE)
diff --git a/board/discovery-stm32f072/spi.c b/board/discovery-stm32f072/spi.c
deleted file mode 100644
index b768bb42bc..0000000000
--- a/board/discovery-stm32f072/spi.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "usb_spi.h"
-
-void usb_spi_ready(struct usb_spi_config const *config)
-{
- task_wake(TASK_ID_USB_SPI);
-}
-
-USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, usb_spi_ready)
-
-void usb_spi_task(void)
-{
- usb_spi_enable(&usb_spi. 1);
-
- while (1) {
- task_wait_event(-1);
-
- while (usb_spi_service_request(&usb_spi))
- ;
- }
-}
diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c
index f0e163cb1b..24b8a530d7 100644
--- a/chip/stm32/usb_spi.c
+++ b/chip/stm32/usb_spi.c
@@ -59,20 +59,12 @@ static void usb_spi_write_packet(struct usb_spi_config const *config,
STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0);
}
-static int rx_valid(struct usb_spi_config const *config)
-{
- return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) == EP_RX_VALID;
-}
-
-int usb_spi_service_request(struct usb_spi_config const *config)
+void usb_spi_deferred(struct usb_spi_config const *config)
{
uint8_t count;
uint8_t write_count;
uint8_t read_count;
- if (rx_valid(config))
- return 0;
-
count = usb_spi_read_packet(config);
write_count = (config->buffer[0] >> 0) & 0xff;
read_count = (config->buffer[0] >> 8) & 0xff;
@@ -93,8 +85,6 @@ int usb_spi_service_request(struct usb_spi_config const *config)
}
usb_spi_write_packet(config, read_count + 2);
-
- return 1;
}
void usb_spi_tx(struct usb_spi_config const *config)
@@ -105,7 +95,8 @@ void usb_spi_tx(struct usb_spi_config const *config)
void usb_spi_rx(struct usb_spi_config const *config)
{
STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_NAK, 0);
- config->ready(config);
+
+ hook_call_deferred(config->deferred, 0);
}
void usb_spi_reset(struct usb_spi_config const *config)
diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h
index 4917c16f0b..5da35c91f6 100644
--- a/chip/stm32/usb_spi.h
+++ b/chip/stm32/usb_spi.h
@@ -8,6 +8,7 @@
/* STM32 USB SPI driver for Chrome EC */
#include "compile_time_macros.h"
+#include "hooks.h"
#include "usb.h"
/*
@@ -95,18 +96,16 @@ struct usb_spi_config {
int endpoint;
/*
+ * Deferred function to call to handle SPI request.
+ */
+ void (*deferred)(void);
+
+ /*
* Pointers to USB packet RAM and bounce buffer.
*/
uint16_t *buffer;
usb_uint *rx_ram;
usb_uint *tx_ram;
-
- /*
- * Callback to notify managing task that a new SPI request has been
- * received. This should wake up a task that will eventually call
- * the usb_spi_service_request function.
- */
- void (*ready)(struct usb_spi_config const *config);
};
/*
@@ -120,16 +119,14 @@ struct usb_spi_config {
*
* ENDPOINT is the index of the USB bulk endpoint used for receiving and
* transmitting bytes.
- *
- * READY callback function for command reception notification.
*/
#define USB_SPI_CONFIG(NAME, \
INTERFACE, \
- ENDPOINT, \
- READY) \
+ ENDPOINT) \
static uint16_t CONCAT2(NAME, _buffer_)[USB_MAX_PACKET_SIZE / 2]; \
static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
+ static void CONCAT2(NAME, _deferred_)(void); \
struct usb_spi_state CONCAT2(NAME, _state_) = { \
.disabled = 1, \
.enabled = 0, \
@@ -138,10 +135,10 @@ struct usb_spi_config {
.state = &CONCAT2(NAME, _state_), \
.interface = INTERFACE, \
.endpoint = ENDPOINT, \
+ .deferred = CONCAT2(NAME, _deferred_), \
.buffer = CONCAT2(NAME, _buffer_), \
.rx_ram = CONCAT2(NAME, _ep_rx_buffer_), \
.tx_ram = CONCAT2(NAME, _ep_tx_buffer_), \
- .ready = READY, \
}; \
const struct usb_interface_descriptor \
USB_IFACE_DESC(INTERFACE) = { \
@@ -184,17 +181,15 @@ struct usb_spi_config {
usb_uint *tx_buf) \
{ return usb_spi_interface(&NAME, rx_buf, tx_buf); } \
USB_DECLARE_IFACE(INTERFACE, \
- CONCAT2(NAME, _interface_));
+ CONCAT2(NAME, _interface_)); \
+ static void CONCAT2(NAME, _deferred_)(void) \
+ { usb_spi_deferred(&NAME); } \
+ DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));
/*
- * Check for a new request and process it synchronously, the SPI transaction
- * will complete before this function returns.
- *
- * Returns:
- * 1: request serviced
- * 0: no request waiting
+ * Handle SPI request in a deferred callback.
*/
-int usb_spi_service_request(struct usb_spi_config const *config);
+void usb_spi_deferred(struct usb_spi_config const *config);
/*
* Set the enable state for the USB-SPI bridge.