diff options
| author | Alexandru M Stan <amstan@chromium.org> | 2014-12-16 12:50:42 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-12-18 00:46:20 +0000 |
| commit | d09526a63e019efa9c96ba446785bf4ac4c704bb (patch) | |
| tree | 03f7d4abbf0bb80d59ca5fb39ccad83bc0bdfa72 | |
| parent | 86835f7067b7ce26431ca459be3d59662736275f (diff) | |
| download | chrome-ec-d09526a63e019efa9c96ba446785bf4ac4c704bb.tar.gz | |
stm32f0: USART: Disable ORECF interrupt we never check for
When the EC is busy enough to start missing RX characters an ORECF might come
(Overrun error), we never check for this bit, so that means the interrupt
handler will be called in a loop because it never clears that bit.
This disables the overrun detection feature.
BUG=chrome-os-partner:33451
TEST=get firmware to poll the EC for keyboard presses, type really fast on the
keyboard, note how system does not watchdog reset anymore but loses the
occasional character instead.
BRANCH=None
Change-Id: I711483768e4ba80aaeb4a324c7dee790b3a23682
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236088
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 1 | ||||
| -rw-r--r-- | chip/stm32/uart.c | 8 | ||||
| -rw-r--r-- | chip/stm32/usart.c | 2 |
3 files changed, 9 insertions, 2 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index cc8f6598e5..a99852b73d 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -194,6 +194,7 @@ #define STM32_USART_CR3_DMAR (1 << 6) #define STM32_USART_CR3_DMAT (1 << 7) #define STM32_USART_CR3_ONEBIT (1 << 11) +#define STM32_USART_CR3_OVRDIS (1 << 12) #define STM32_USART_CR3_WUS_START_BIT (2 << 20) #define STM32_USART_CR3_WUFIE (1 << 22) #define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index d0240966f2..3544b95efe 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -288,7 +288,13 @@ void uart_init(void) * so clear UE first. */ STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UE; - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT; + + /* + * Also disable the RX overrun interrupt, since we don't care about it + * and we don't want to clear an extra flag in the interrupt + */ + STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT | + STM32_USART_CR3_OVRDIS; #endif /* diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c index 8affbebf08..264fa35a75 100644 --- a/chip/stm32/usart.c +++ b/chip/stm32/usart.c @@ -89,7 +89,7 @@ void usart_init(struct usart_config const *config) STM32_USART_CR1_RE | STM32_USART_CR1_RXNEIE); STM32_USART_CR2(base) = 0x0000; - STM32_USART_CR3(base) = 0x0000; + STM32_USART_CR3(base) = STM32_USART_CR3_OVRDIS; /* * Enable the variant specific HW. |