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| author | Myles Watson <mylesgw@chromium.org> | 2015-01-22 08:42:22 -0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-01-24 00:32:21 +0000 |
| commit | ad06ead062967be31d9474e202263bffe792dee6 (patch) | |
| tree | 7397b05a80112ae97558aa5639512d3993e9c908 | |
| parent | 35c00bf3d9a9dd5da6e797a189598ed4862626f5 (diff) | |
| download | chrome-ec-ad06ead062967be31d9474e202263bffe792dee6.tar.gz | |
nrf51: add the watchdog registers.
The definitions for the watchdog registers are needed for hard reset.
BRANCH=NONE
BUG=None
TEST=make buildall -j
Change-Id: Ief73b98fbe6fc198c3eda28394e76bdf05568fef
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/242900
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | chip/nrf51/registers.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h index 3e8180bd0a..0619c2b409 100644 --- a/chip/nrf51/registers.h +++ b/chip/nrf51/registers.h @@ -355,6 +355,36 @@ /* + * Watchdog Timer (WDT) + */ +#define NRF51_WDT_BASE 0x40010000 +/* Tasks */ +#define NRF51_WDT_START REG32(NRF51_WDT_BASE + 0x000) +/* Events */ +#define NRF51_WDT_TIMEOUT REG32(NRF51_WDT_BASE + 0x100) +/* Registers */ +#define NRF51_WDT_INTENSET REG32(NRF51_WDT_BASE + 0x304) +#define NRF51_WDT_INTENCLR REG32(NRF51_WDT_BASE + 0x308) +#define NRF51_WDT_RUNSTATUS REG32(NRF51_WDT_BASE + 0x400) +#define NRF51_WDT_REQSTATUS REG32(NRF51_WDT_BASE + 0x404) +#define NRF51_WDT_CRV REG32(NRF51_WDT_BASE + 0x504) +#define NRF51_WDT_RREN REG32(NRF51_WDT_BASE + 0x508) +#define NRF51_WDT_CONFIG REG32(NRF51_WDT_BASE + 0x50C) +#define NRF51_WDT_RR(n) REG32(NRF51_WDT_BASE + 0x600 + ((n) * 4)) +#define NRF51_WDT_POWER REG32(NRF51_WDT_BASE + 0xFFC) +/* Bitfields */ +#define NRF51_WDT_RUNSTATUS_RUNNING 1 +#define NRF51_WDT_REQSTATUS_BIT(n) (1<<(n)) +#define NRF51_WDT_RREN_BIT(n) (1<<(n)) +#define NRF51_WDT_CONFIG_SLEEP_PAUSE 0 +#define NRF51_WDT_CONFIG_SLEEP_RUN 1 +#define NRF51_WDT_CONFIG_HALT_PAUSE (0<<4) +#define NRF51_WDT_CONFIG_HALT_RUN (1<<4) + +#define NRF51_WDT_RELOAD_VAL 0x6E524635 + + +/* * GPIO */ #define NRF51_GPIO_BASE 0x50000000 |