Add CONFIG_FLASH_PSTATE option to enable persistent flash WP state

Previously, the flash module assumed it needed to emulate a SPI write
protect register using a bank of flash to hold the persistent flash
write protect state.  This is not true for mec and ncpx chips under
development, which use external SPI flash.  So, gate that code with
CONFIG_FLASH_PSTATE.  For compatibility, leave it on by default (as we
do with CONFIG_FLASH_MAPPED).

There is no change to the behavior of currently supported chips, since
all of them already assume pstate is present.  Removing this feature
from npcx will be done in a subsequent change.

BUG=chrome-os-partner:34346
BRANCH=strago
TEST=make buildall -j; verify flash wp and flashinfo work properly on samus

Change-Id: Ie044eb042863e4a7359ea540166ffd8d0089589d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/253632
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>

4 files changed, 41 insertions, 16 deletions

diff --git a/common/flash.c b/common/flash.c
index 5f4f5fc2d6..d41fb43398 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -23,6 +23,7 @@
 #define CONFIG_FLASH_ERASED_VALUE32 (-1U)
 #endif
 
+#ifdef CONFIG_FLASH_PSTATE
 /* Persistent protection state - emulates a SPI status register for flashrom */
 struct persist_state {
 	uint8_t version;            /* Version of this struct */
@@ -35,6 +36,7 @@ struct persist_state {
 /* Flags for persist_state.flags */
 /* Protect persist state and RO firmware at boot */
 #define PERSIST_FLAG_PROTECT_RO 0x02
+#endif
 
 int flash_range_ok(int offset, int size_req, int align)
 {
@@ -74,6 +76,7 @@ int flash_dataptr(int offset, int size_req, int align, const char **ptrp)
 }
 #endif
 
+#ifdef CONFIG_FLASH_PSTATE
 /**
  * Read persistent state into pstate.
  *
@@ -124,6 +127,7 @@ static int flash_write_pstate(const struct persist_state *pstate)
 	return flash_physical_write(PSTATE_OFFSET, sizeof(*pstate),
 				    (const char *)pstate);
 }
+#endif /* CONFIG_FLASH_PSTATE */
 
 int flash_is_erased(uint32_t offset, int size)
 {
@@ -204,6 +208,7 @@ int flash_erase(int offset, int size)
 
 int flash_protect_at_boot(enum flash_wp_range range)
 {
+#ifdef CONFIG_FLASH_PSTATE
 	struct persist_state pstate;
 	int new_flags = (range != FLASH_WP_NONE) ? PERSIST_FLAG_PROTECT_RO : 0;
 
@@ -243,11 +248,13 @@ int flash_protect_at_boot(enum flash_wp_range range)
 #endif
 
 	return EC_SUCCESS;
+#else
+	return flash_physical_protect_at_boot(range);
+#endif
 }
 
 uint32_t flash_get_protect(void)
 {
-	struct persist_state pstate;
 	uint32_t flags = 0;
 	int not_protected[2] = {0};
 	int i;
@@ -263,23 +270,30 @@ uint32_t flash_get_protect(void)
 		flags |= EC_FLASH_PROTECT_GPIO_ASSERTED;
 #endif
 
-	/* Read persistent state of RO-at-boot flag */
-	flash_read_pstate(&pstate);
-	if (pstate.flags & PERSIST_FLAG_PROTECT_RO)
-		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
+#ifdef CONFIG_FLASH_PSTATE
+	{
+		/* Read persistent state of RO-at-boot flag */
+		struct persist_state pstate;
+		flash_read_pstate(&pstate);
+		if (pstate.flags & PERSIST_FLAG_PROTECT_RO)
+			flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
+	}
+#endif
 
 	/* Scan flash protection */
 	for (i = 0; i < PHYSICAL_BANKS; i++) {
-		/*
-		 * Is this bank part of RO?  Needs to handle PSTATE not
-		 * immediately following RO code, since it doesn't on link.
-		 */
-		int is_ro = ((i >= RO_BANK_OFFSET &&
-			      i < RO_BANK_OFFSET + RO_BANK_COUNT) ||
-			     (i >= PSTATE_BANK &&
-			      i < PSTATE_BANK + PSTATE_BANK_COUNT)) ? 1 : 0;
-		int bank_flag = (is_ro ? EC_FLASH_PROTECT_RO_NOW :
-				 EC_FLASH_PROTECT_ALL_NOW);
+		/* Is this bank part of RO */
+		int is_ro = (i >= RO_BANK_OFFSET &&
+			     i < RO_BANK_OFFSET + RO_BANK_COUNT) ? 1 : 0;
+		int bank_flag;
+
+#ifdef CONFIG_FLASH_PSTATE
+		/* PSTATE acts like part of RO; protected at same time */
+		if (i >= PSTATE_BANK && i < PSTATE_BANK + PSTATE_BANK_COUNT)
+			is_ro = 1;
+#endif
+		bank_flag = (is_ro ? EC_FLASH_PROTECT_RO_NOW :
+			     EC_FLASH_PROTECT_ALL_NOW);
 
 		if (flash_physical_get_protect(i)) {
 			/* At least one bank in the region is protected */
diff --git a/include/config.h b/include/config.h
index f88b7fde54..dd5e836ede 100644
--- a/include/config.h
+++ b/include/config.h
@@ -587,6 +587,15 @@
 
 #undef CONFIG_FLASH_PHYSICAL_SIZE
 #undef CONFIG_FLASH_PROTECT_NEXT_BOOT
+
+/*
+ * Use a bank of flash to store its persistent write protect state.  This
+ * allows ECs with internal flash to emulate something closer to a SPI flash
+ * write protect register.  If this is not defined, write protect state is
+ * maintained solely by the physical flash driver.
+ */
+#define CONFIG_FLASH_PSTATE
+
 #undef CONFIG_FLASH_SIZE
 #undef CONFIG_FLASH_WRITE_IDEAL_SIZE
 #undef CONFIG_FLASH_WRITE_SIZE
diff --git a/include/ec_commands.h b/include/ec_commands.h
index d54feecbe8..c03a55af77 100644
--- a/include/ec_commands.h
+++ b/include/ec_commands.h
@@ -838,7 +838,7 @@ struct ec_params_flash_erase {
  * re-requesting the desired flags, or by a hard reset if that fails.
  */
 #define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5)
-/* Entile flash code protected when the EC boots */
+/* Entire flash code protected when the EC boots */
 #define EC_FLASH_PROTECT_ALL_AT_BOOT        (1 << 6)
 
 struct ec_params_flash_protect {
diff --git a/include/flash.h b/include/flash.h
index 3a4a120938..f2cc480dba 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -23,10 +23,12 @@
 #define RW_BANK_COUNT		(CONFIG_FW_RW_SIZE / CONFIG_FLASH_BANK_SIZE)
 
 /* Persistent protection state flash offset / size / bank */
+#ifdef CONFIG_FLASH_PSTATE
 #define PSTATE_OFFSET		CONFIG_FW_PSTATE_OFF
 #define PSTATE_SIZE		CONFIG_FW_PSTATE_SIZE
 #define PSTATE_BANK		(PSTATE_OFFSET / CONFIG_FLASH_BANK_SIZE)
 #define PSTATE_BANK_COUNT	(PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE)
+#endif
 
 /* Range of write protection */
 enum flash_wp_range {