diff options
| author | Sheng-Liang Song <ssl@chromium.org> | 2015-03-13 13:20:15 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-03-20 23:06:53 +0000 |
| commit | bdcc496b304ddc7e614de025a08133bbc152ba7f (patch) | |
| tree | 62898e8a6487d454efcf38cad40649a68c249a36 | |
| parent | 746debdf20a647fbe0e197f8a6c7b0597bc6a27f (diff) | |
| download | chrome-ec-bdcc496b304ddc7e614de025a08133bbc152ba7f.tar.gz | |
cr50: added cr50 a1 chip
cr50_a1 is for cr50 Rev A1 chip.
BUG=chrome-os-partner:33432
BRANCH=none
TEST=Compile Only
Change-Id: I5490d1a5b89fa66c8e8b969cff7538a293a7d053
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/259847
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
| -rw-r--r-- | board/cr50/build.mk | 2 | ||||
| l--------- | board/cr50_a1/Makefile | 1 | ||||
| -rw-r--r-- | board/cr50_a1/board.c | 51 | ||||
| -rw-r--r-- | board/cr50_a1/board.h | 38 | ||||
| -rw-r--r-- | board/cr50_a1/build.mk | 15 | ||||
| -rw-r--r-- | board/cr50_a1/dev_key.pem | 27 | ||||
| -rw-r--r-- | board/cr50_a1/ec.tasklist | 21 | ||||
| -rw-r--r-- | board/cr50_a1/gpio.inc | 65 | ||||
| -rw-r--r-- | chip/g/build.mk | 2 | ||||
| -rw-r--r-- | chip/g/cr50_a1_regdefs.h | 18363 | ||||
| -rw-r--r-- | chip/g/cr50_fpga_regdefs.h (renamed from chip/g/gc_regdefs.h) | 0 | ||||
| -rw-r--r-- | chip/g/registers.h | 15 | ||||
| -rw-r--r-- | chip/g/uart.c | 5 |
13 files changed, 18598 insertions, 7 deletions
diff --git a/board/cr50/build.mk b/board/cr50/build.mk index 4119804a2c..3e34de12f9 100644 --- a/board/cr50/build.mk +++ b/board/cr50/build.mk @@ -6,6 +6,8 @@ # Board specific files build CHIP:=g +CHIP_FAMILY:=cr50 +CHIP_VARIANT:=cr50_fpga board-y=board.o diff --git a/board/cr50_a1/Makefile b/board/cr50_a1/Makefile new file mode 120000 index 0000000000..94aaae2c4d --- /dev/null +++ b/board/cr50_a1/Makefile @@ -0,0 +1 @@ +../../Makefile
\ No newline at end of file diff --git a/board/cr50_a1/board.c b/board/cr50_a1/board.c new file mode 100644 index 0000000000..92a6808c11 --- /dev/null +++ b/board/cr50_a1/board.c @@ -0,0 +1,51 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "registers.h" +#include "task.h" +#include "util.h" + +/* + * There's no way to trigger on both rising and falling edges, so force a + * compiler error if we try. The workaround is to use the pinmux to connect + * two GPIOs to the same input and configure each one for a separate edge. + */ +#undef GPIO_INT_BOTH +#define GPIO_INT_BOTH NOT_SUPPORTED_ON_CR50 + +#include "gpio_list.h" + +/* Interrupt handler for button pushes */ +void button_event(enum gpio_signal signal) +{ + int v; + + /* We have two GPIOs on the same input (one rising edge, one falling + * edge), so de-alias them */ + if (signal >= GPIO_SW_N_) + signal -= (GPIO_SW_N_ - GPIO_SW_N); + + v = gpio_get_level(signal); + ccprintf("Button %d = %d\n", signal, v); + gpio_set_level(signal - GPIO_SW_N + GPIO_LED_4, v); +} + +/* Initialize board. */ +static void board_init(void) +{ + gpio_enable_interrupt(GPIO_SW_N); + gpio_enable_interrupt(GPIO_SW_S); + gpio_enable_interrupt(GPIO_SW_W); + gpio_enable_interrupt(GPIO_SW_E); + gpio_enable_interrupt(GPIO_SW_N_); + gpio_enable_interrupt(GPIO_SW_S_); + gpio_enable_interrupt(GPIO_SW_W_); + gpio_enable_interrupt(GPIO_SW_E_); +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/cr50_a1/board.h b/board/cr50_a1/board.h new file mode 100644 index 0000000000..e03544c8d5 --- /dev/null +++ b/board/cr50_a1/board.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __BOARD_H +#define __BOARD_H + +/* Features that we don't want just yet */ +#undef CONFIG_CMD_LID_ANGLE +#undef CONFIG_CMD_POWERINDEBUG +#undef CONFIG_DMA_DEFAULT_HANDLERS +#undef CONFIG_FLASH +#undef CONFIG_FMAP +#undef CONFIG_HIBERNATE +#undef CONFIG_LID_SWITCH + +/* + * Allow dangerous commands all the time, since we don't have a write protect + * switch. + */ +#define CONFIG_SYSTEM_UNLOCKED + +/* Not using software sync, so verify RW signature instead */ +#define CONFIG_RWSIG +#define CONFIG_RSA +#define CONFIG_SHA256 + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" + +/* user button interrupt handler */ +void button_event(enum gpio_signal signal); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __BOARD_H */ diff --git a/board/cr50_a1/build.mk b/board/cr50_a1/build.mk new file mode 100644 index 0000000000..9b0a26c13d --- /dev/null +++ b/board/cr50_a1/build.mk @@ -0,0 +1,15 @@ +# -*- makefile -*- +# Copyright (c) 2014 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +CHIP:=g +CHIP_FAMILY:=cr50 +CHIP_VARIANT:=cr50_a1 + +board-y=board.o + +# Need to generate a .hex file +all: hex diff --git a/board/cr50_a1/dev_key.pem b/board/cr50_a1/dev_key.pem new file mode 100644 index 0000000000..6f15b80652 --- /dev/null +++ b/board/cr50_a1/dev_key.pem @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEogIBAAKCAQEAsaHkxeqOorLS8/Ixp43ZnPnJ+ItBIbX4AkmKFLZyLus9NaFX +j2r+qIM0Daxsaq/qvtlnRNrQ313XH/F5e1xrdTcC4VovR8Q4wXh+hEw4Nhcz2U/c +daZMaBJUZlYEHpi2R9UXcflDS68oE5GNJT5EuGfqdpvStTFMU33Bv7cxgf3lQg2c +fhMoNNjTxzzR+ta0lmaQLZ7kh6IOIb0SoTmANvmtANPdIC4NTHk43KSRTShOTYRs +b7pbOrFq+7bmDWhgfHv7Y34Y2f0LouXlzJEfGnlpXYOX5WA9H9XMbBGwhjKNq5R6 +YHW069FyT6G28VceY+i3SMdgoEgyNPn/GHK02wIDAQABAoIBAAX35JHp0aUR0Ri1 +OInisD8f/XNGaofRb2XURrlvb+K3sLTOmPyOocPTtLoI4xOqmX6UG24q0/3NT18Z +Y/WLI2kq0gP0XcZRh36op8eWMAVRPkK89jFVxxdwFjniBf1pMCa1uDXyJBq05enS +aCWqM/DmPPCDR88iuufLP+lLJHSznt2vDjbONcU+MVtuymrBkYR/APPSl7CPNmF4 +WPhWoVbj5tgOO5XUTU/wFRLgnD2FfPiS0g26AKeriJWTeD2dZHFcmJAoFxs1du18 +1r4yAZveEcT+RgVsXa9L+/OTd+uuPVzlgEBhyP2xSiFN9TMPlpBdsWrDtx4ZFnQV +ajMVeGECgYEA11TbaI6G5xEhCaz+11v8UYIX1V9KXTJz1fuy4qyItduf27O3egAO +KhUu8nxTpj2JTj65ZPWlTahLF5UKuyAbOmyP5OZBSmZHqfATMh8jEz50mfTWgtew +KzswTtslXV8ekaVBta+aNUJrptqtpVK9PpE1yAOjmw42vk3YgbL4pzkCgYEA0y5P +R3u0pS9ZFfI7cFOFBZm2B+e6Md2P/8zmyzJakIQhHVbAWkhc6BIocUe0xSVG0ceq +3n2QPfkmWrZrUSp+5n9ouaC8ixqWrHU7xbGHLklWsq+WpI0PvNTftPS9akVJV4D9 +xD1K8lpPQuakuOmctUco2G4p1LSwbfQqwe48CLMCgYAanR5RGeyKeo9+xqborzHM +USvo71IdmrK+a9F8Op7a+z4SxW+T4JXflaarybn8/fYOeaooVEQOCRLe40jkP9+d +pPVT8TF4pJOO6WE1/Ks1Ia7/qEcq/MWFUldyJ5vCopMApVAtyHpiwsbTZIu5tzQ0 +m3XuNqTt8R/K/YwY26nn4QKBgB3gl2bNoakdIcVxF+e0aUV5kb9ckYMsjYrrOlvV +K+r2RpkYBO7A/iP3LbGZK4IY3AQh85K2wQmDjmGXHWfGU13Y+MAKdaJYiKitjV9S +1oU96v4syWtOacOVenDnj0TRuKagoUZ6RXg0PrKAXx2qL3mWL7kvHMvzJGLqAIKf +ae7xAoGAClWOT/hzzUROAVYIYszYUXrVAtCC896m8b8VRG1kL3GL/pOyKoqvVybi +Mx9V1mi/oFcBA2MGDAaJUJEQ7JYih/go3auzEmL3zQHzeLofaldFjOt2kN1ff6UF +HKyS+l/Ub1NVhHkXoVZpo6spKyMG/iPm4qr+rIvkwwfF1e2OADU= +-----END RSA PRIVATE KEY----- diff --git a/board/cr50_a1/ec.tasklist b/board/cr50_a1/ec.tasklist new file mode 100644 index 0000000000..8ff4e8234b --- /dev/null +++ b/board/cr50_a1/ec.tasklist @@ -0,0 +1,21 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) diff --git a/board/cr50_a1/gpio.inc b/board/cr50_a1/gpio.inc new file mode 100644 index 0000000000..8c518b8cf7 --- /dev/null +++ b/board/cr50_a1/gpio.inc @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Inputs with interrupt handlers are first for efficiency */ + +/* User Push buttons */ +GPIO(SW_N, 0, 0, GPIO_INT_RISING, button_event) +GPIO(SW_S, 0, 1, GPIO_INT_RISING, button_event) +GPIO(SW_W, 0, 2, GPIO_INT_RISING, button_event) +GPIO(SW_E, 0, 3, GPIO_INT_RISING, button_event) + +/* We can't trigger on both rising and falling edge, so attach each button + * to two input GPIOs. */ +GPIO(SW_N_, 1, 0, GPIO_INT_FALLING, button_event) +GPIO(SW_S_, 1, 1, GPIO_INT_FALLING, button_event) +GPIO(SW_W_, 1, 2, GPIO_INT_FALLING, button_event) +GPIO(SW_E_, 1, 3, GPIO_INT_FALLING, button_event) + +/* User GPIO LEDs */ +GPIO(LED_2, 0, 4, GPIO_OUT_LOW, NULL) +GPIO(LED_3, 0, 5, GPIO_OUT_LOW, NULL) +GPIO(LED_4, 0, 6, GPIO_OUT_LOW, NULL) +GPIO(LED_5, 0, 7, GPIO_OUT_LOW, NULL) +GPIO(LED_6, 0, 8, GPIO_OUT_LOW, NULL) +GPIO(LED_7, 0, 9, GPIO_OUT_LOW, NULL) + +/* Unimplemented signals which we need to emulate for now */ +UNIMPLEMENTED(ENTERING_RW) + +/* The Cr50 ARM core has no alternate functions, so we repurpose that + * macro to describe the PINMUX setup. The args are + * + * 1. The ARM core GPIO or SoC peripheral function to connect + * 2. The pinmux DIO pad to connect to + * 3. <ignored> + * 4. MODULE_GPIO, to prevent being called by gpio_config_module() + * 5. flags to specify the direction if the GPIO isn't enough + */ + +/* The serial port is one of the SoC peripheral functions */ +ALTERNATE(FUNC(UART0_TX), DIO(A0), 0, MODULE_GPIO, DIO_OUTPUT) +ALTERNATE(FUNC(UART0_RX), DIO(A1), 0, MODULE_GPIO, DIO_INPUT) + +/* Inputs */ +ALTERNATE(SW_N, DIO(M0), 0, MODULE_GPIO, 0) +ALTERNATE(SW_S, DIO(M1), 0, MODULE_GPIO, 0) +ALTERNATE(SW_W, DIO(M2), 0, MODULE_GPIO, 0) +ALTERNATE(SW_E, DIO(M3), 0, MODULE_GPIO, 0) + +/* Aliased Inputs, connected to the same pins */ +ALTERNATE(SW_N_, DIO(M0), 0, MODULE_GPIO, 0) +ALTERNATE(SW_S_, DIO(M1), 0, MODULE_GPIO, 0) +ALTERNATE(SW_W_, DIO(M2), 0, MODULE_GPIO, 0) +ALTERNATE(SW_E_, DIO(M3), 0, MODULE_GPIO, 0) + +/* Outputs - also mark as inputs so we can read back from the driven pin */ +ALTERNATE(LED_2, DIO(A9), 0, MODULE_GPIO, DIO_INPUT) +ALTERNATE(LED_3, DIO(A10), 0, MODULE_GPIO, DIO_INPUT) +ALTERNATE(LED_4, DIO(A11), 0, MODULE_GPIO, DIO_INPUT) +ALTERNATE(LED_5, DIO(A12), 0, MODULE_GPIO, DIO_INPUT) +ALTERNATE(LED_6, DIO(A13), 0, MODULE_GPIO, DIO_INPUT) +ALTERNATE(LED_7, DIO(A14), 0, MODULE_GPIO, DIO_INPUT) diff --git a/chip/g/build.mk b/chip/g/build.mk index 3b5c8627aa..5c5a9a1034 100644 --- a/chip/g/build.mk +++ b/chip/g/build.mk @@ -11,7 +11,7 @@ CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3 ver_defs := GC___MAJOR_REV__ GC___MINOR_REV__ bld_defs := GC_SWDP_BUILD_DATE_DEFAULT GC_SWDP_BUILD_TIME_DEFAULT ver_params := $(shell echo "$(ver_defs) $(bld_defs)" | $(CPP) $(CPPFLAGS) -P \ - -imacros chip/g/gc_regdefs.h | sed -e "s/__REV\([A-Z]\)__/\1/") + -imacros chip/g/${CHIP_VARIANT}_regdefs.h | sed -e "s/__REV\([A-Z]\)__/\1/") ver_str := $(shell printf "%s%s %d_%d" $(ver_params)) CPPFLAGS+= -DGC_REVISION="$(ver_str)" diff --git a/chip/g/cr50_a1_regdefs.h b/chip/g/cr50_a1_regdefs.h new file mode 100644 index 0000000000..da28c39076 --- /dev/null +++ b/chip/g/cr50_a1_regdefs.h @@ -0,0 +1,18363 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* This file is autogenerated. Do not edit. */ + +#ifndef GC_REGDEFS_H +#define GC_REGDEFS_H +#define GC___REVA__ 1 +#define GC___REVB__ 2 +#define GC___REVC__ 3 +#define GC___REVD__ 4 +#define GC___REVE__ 5 +#define GC___HAVEN__ 1 +#define GC___MAJOR_REV__ __REVA__ +#define GC___MINOR_REV__ 1 +#define GC_PINMUX_DIOA0_SEL 0x6 +#define GC_PINMUX_DIOA1_SEL 0x7 +#define GC_PINMUX_DIOA2_SEL 0x8 +#define GC_PINMUX_DIOA3_SEL 0x9 +#define GC_PINMUX_DIOA4_SEL 0xa +#define GC_PINMUX_DIOA5_SEL 0xb +#define GC_PINMUX_DIOA6_SEL 0xc +#define GC_PINMUX_DIOA7_SEL 0xd +#define GC_PINMUX_DIOA8_SEL 0xe +#define GC_PINMUX_DIOA9_SEL 0xf +#define GC_PINMUX_DIOA10_SEL 0x10 +#define GC_PINMUX_DIOA11_SEL 0x11 +#define GC_PINMUX_DIOA12_SEL 0x12 +#define GC_PINMUX_DIOA13_SEL 0x13 +#define GC_PINMUX_DIOA14_SEL 0x14 +#define GC_PINMUX_DIOB0_SEL 0x15 +#define GC_PINMUX_DIOB1_SEL 0x16 +#define GC_PINMUX_DIOB2_SEL 0x17 +#define GC_PINMUX_DIOB3_SEL 0x18 +#define GC_PINMUX_DIOB4_SEL 0x19 +#define GC_PINMUX_DIOB5_SEL 0x1a +#define GC_PINMUX_DIOB6_SEL 0x1b +#define GC_PINMUX_DIOB7_SEL 0x1c +#define GC_PINMUX_DIOB8_SEL 0x1d +#define GC_PINMUX_DIOM0_SEL 0x1 +#define GC_PINMUX_DIOM1_SEL 0x2 +#define GC_PINMUX_DIOM2_SEL 0x3 +#define GC_PINMUX_DIOM3_SEL 0x4 +#define GC_PINMUX_DIOM4_SEL 0x5 +#define GC_PINMUX_GPIO0_GPIO0_SEL 0x1 +#define GC_PINMUX_GPIO0_GPIO1_SEL 0x2 +#define GC_PINMUX_GPIO0_GPIO2_SEL 0x3 +#define GC_PINMUX_GPIO0_GPIO3_SEL 0x4 +#define GC_PINMUX_GPIO0_GPIO4_SEL 0x5 +#define GC_PINMUX_GPIO0_GPIO5_SEL 0x6 +#define GC_PINMUX_GPIO0_GPIO6_SEL 0x7 +#define GC_PINMUX_GPIO0_GPIO7_SEL 0x8 +#define GC_PINMUX_GPIO0_GPIO8_SEL 0x9 +#define GC_PINMUX_GPIO0_GPIO9_SEL 0xa +#define GC_PINMUX_GPIO0_GPIO10_SEL 0xb +#define GC_PINMUX_GPIO0_GPIO11_SEL 0xc +#define GC_PINMUX_GPIO0_GPIO12_SEL 0xd +#define GC_PINMUX_GPIO0_GPIO13_SEL 0xe +#define GC_PINMUX_GPIO0_GPIO14_SEL 0xf +#define GC_PINMUX_GPIO0_GPIO15_SEL 0x10 +#define GC_PINMUX_GPIO1_GPIO0_SEL 0x11 +#define GC_PINMUX_GPIO1_GPIO1_SEL 0x12 +#define GC_PINMUX_GPIO1_GPIO2_SEL 0x13 +#define GC_PINMUX_GPIO1_GPIO3_SEL 0x14 +#define GC_PINMUX_GPIO1_GPIO4_SEL 0x15 +#define GC_PINMUX_GPIO1_GPIO5_SEL 0x16 +#define GC_PINMUX_GPIO1_GPIO6_SEL 0x17 +#define GC_PINMUX_GPIO1_GPIO7_SEL 0x18 +#define GC_PINMUX_GPIO1_GPIO8_SEL 0x19 +#define GC_PINMUX_GPIO1_GPIO9_SEL 0x1a +#define GC_PINMUX_GPIO1_GPIO10_SEL 0x1b +#define GC_PINMUX_GPIO1_GPIO11_SEL 0x1c +#define GC_PINMUX_GPIO1_GPIO12_SEL 0x1d +#define GC_PINMUX_GPIO1_GPIO13_SEL 0x1e +#define GC_PINMUX_GPIO1_GPIO14_SEL 0x1f +#define GC_PINMUX_GPIO1_GPIO15_SEL 0x20 +#define GC_PINMUX_I2C0_SCL_SEL 0x23 +#define GC_PINMUX_I2C0_SDA_SEL 0x24 +#define GC_PINMUX_I2C1_SCL_SEL 0x25 +#define GC_PINMUX_I2C1_SDA_SEL 0x26 +#define GC_PINMUX_I2CS0_SCL_SEL 0x21 +#define GC_PINMUX_I2CS0_SDA_SEL 0x22 +#define GC_PINMUX_PMU_TESTBUS0_SEL 0x27 +#define GC_PINMUX_PMU_TESTBUS1_SEL 0x28 +#define GC_PINMUX_PMU_TESTBUS2_SEL 0x29 +#define GC_PINMUX_PMU_TESTBUS3_SEL 0x2a +#define GC_PINMUX_PMU_TESTBUS4_SEL 0x2b +#define GC_PINMUX_PMU_TESTBUS5_SEL 0x2c +#define GC_PINMUX_PMU_TESTBUS6_SEL 0x2d +#define GC_PINMUX_PMU_TESTBUS7_SEL 0x2e +#define GC_PINMUX_RBOX0_AC_PRESENT_SEL 0x2f +#define GC_PINMUX_RBOX0_BATT_EN_SEL 0x30 +#define GC_PINMUX_RBOX0_EC_IN_RW_SEL 0x31 +#define GC_PINMUX_RBOX0_EC_RST_L_SEL 0x32 +#define GC_PINMUX_RBOX0_EC_WP_L_SEL 0x33 +#define GC_PINMUX_RBOX0_ENTERING_RW_SEL 0x34 +#define GC_PINMUX_RBOX0_FW_WP_L_SEL 0x35 +#define GC_PINMUX_RBOX0_KSI_SEL 0x36 +#define GC_PINMUX_RBOX0_KSI_SW_SEL 0x37 +#define GC_PINMUX_RBOX0_KSO_INV_SEL 0x38 +#define GC_PINMUX_RBOX0_KSO_SW_SEL 0x39 +#define GC_PINMUX_RBOX0_PWR_BTNO_L_SEL 0x3b +#define GC_PINMUX_RBOX0_PWR_BTN_L_SEL 0x3a +#define GC_PINMUX_RTC0_X_RTC_CLK_SEL 0x3c +#define GC_PINMUX_RTCXOP_SEL 0x1e +#define GC_PINMUX_SPI0_SPICLK_SEL 0x3d +#define GC_PINMUX_SPI0_SPICSB_SEL 0x3e +#define GC_PINMUX_SPI0_SPIMISO_SEL 0x3f +#define GC_PINMUX_SPI0_SPIMOSI_SEL 0x40 +#define GC_PINMUX_SPS0_SPICLK_SEL 0x41 +#define GC_PINMUX_SPS0_SPICSB_SEL 0x42 +#define GC_PINMUX_SPS0_SPIMISO_SEL 0x43 +#define GC_PINMUX_SPS0_SPIMOSI_SEL 0x44 +#define GC_PINMUX_SWDP0_TRACE2_SEL 0x46 +#define GC_PINMUX_SWDP0_TRACE_SEL 0x45 +#define GC_PINMUX_SWDPDATA_SEL 0x20 +#define GC_PINMUX_SWDPTRACE_SEL 0x1f +#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL 0x47 +#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL 0x48 +#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL 0x49 +#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL 0x4a +#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL 0x4b +#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL 0x4c +#define GC_PINMUX_UART0_CTS_SEL 0x4d +#define GC_PINMUX_UART0_RTS_SEL 0x4e +#define GC_PINMUX_UART0_RX_SEL 0x4f +#define GC_PINMUX_UART0_TX_SEL 0x50 +#define GC_PINMUX_UART1_CTS_SEL 0x51 +#define GC_PINMUX_UART1_RTS_SEL 0x52 +#define GC_PINMUX_UART1_RX_SEL 0x53 +#define GC_PINMUX_UART1_TX_SEL 0x54 +#define GC_PINMUX_UART2_CTS_SEL 0x55 +#define GC_PINMUX_UART2_RTS_SEL 0x56 +#define GC_PINMUX_UART2_RX_SEL 0x57 +#define GC_PINMUX_UART2_TX_SEL 0x58 +#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x59 +#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x5a +#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x5b +#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x5c +#define GC_PINMUX_USB0_EXT_RX_DMI_SEL 0x5d +#define GC_PINMUX_USB0_EXT_RX_DPI_SEL 0x5e +#define GC_PINMUX_USB0_EXT_RX_RCV_SEL 0x5f +#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL 0x60 +#define GC_PINMUX_USB0_EXT_TX_DMO_SEL 0x61 +#define GC_PINMUX_USB0_EXT_TX_DPO_SEL 0x62 +#define GC_PINMUX_USB0_EXT_TX_OEB_SEL 0x63 +#define GC_PINMUX_VIO0_SEL 0x21 +#define GC_PINMUX_VIO1_SEL 0x22 +#define GC_PINMUX_XO0_TESTCLK_SEL 0x64 +#define GC_EXCEPTNUM_RESET 0x1 +#define GC_EXCEPTNUM_NMI 0x2 +#define GC_EXCEPTNUM_HARDFAULT 0x3 +#define GC_EXCEPTNUM_MEMORYMANAGEMENT 0x4 +#define GC_EXCEPTNUM_BUSFAULT 0x5 +#define GC_EXCEPTNUM_USAGEFAULT 0x6 +#define GC_EXCEPTNUM_RESERVED7 0x7 +#define GC_EXCEPTNUM_RESERVED8 0x8 +#define GC_EXCEPTNUM_RESERVED9 0x9 +#define GC_EXCEPTNUM_RESERVED10 0xa +#define GC_EXCEPTNUM_SVCALL 0xb +#define GC_EXCEPTNUM_DEBUGMONITOR 0xc +#define GC_EXCEPTNUM_RESERVED13 0xd +#define GC_EXCEPTNUM_PENDSV 0xe +#define GC_EXCEPTNUM_SYSTICK 0xf +#define GC_EXCEPTNUM_CAMO0_BREACH_INT 0x10 +#define GC_EXCEPTNUM_FLASH0_EDONEINT 0x11 +#define GC_EXCEPTNUM_FLASH0_PDONEINT 0x12 +#define GC_EXCEPTNUM_GPIO0_GPIO0INT 0x14 +#define GC_EXCEPTNUM_GPIO0_GPIO1INT 0x15 +#define GC_EXCEPTNUM_GPIO0_GPIO2INT 0x16 +#define GC_EXCEPTNUM_GPIO0_GPIO3INT 0x17 +#define GC_EXCEPTNUM_GPIO0_GPIO4INT 0x18 +#define GC_EXCEPTNUM_GPIO0_GPIO5INT 0x19 +#define GC_EXCEPTNUM_GPIO0_GPIO6INT 0x1a +#define GC_EXCEPTNUM_GPIO0_GPIO7INT 0x1b +#define GC_EXCEPTNUM_GPIO0_GPIO8INT 0x1c +#define GC_EXCEPTNUM_GPIO0_GPIO9INT 0x1d +#define GC_EXCEPTNUM_GPIO0_GPIO10INT 0x1e +#define GC_EXCEPTNUM_GPIO0_GPIO11INT 0x1f +#define GC_EXCEPTNUM_GPIO0_GPIO12INT 0x20 +#define GC_EXCEPTNUM_GPIO0_GPIO13INT 0x21 +#define GC_EXCEPTNUM_GPIO0_GPIO14INT 0x22 +#define GC_EXCEPTNUM_GPIO0_GPIO15INT 0x23 +#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT 0x13 +#define GC_EXCEPTNUM_GPIO1_GPIO0INT 0x25 +#define GC_EXCEPTNUM_GPIO1_GPIO1INT 0x26 +#define GC_EXCEPTNUM_GPIO1_GPIO2INT 0x27 +#define GC_EXCEPTNUM_GPIO1_GPIO3INT 0x28 +#define GC_EXCEPTNUM_GPIO1_GPIO4INT 0x29 +#define GC_EXCEPTNUM_GPIO1_GPIO5INT 0x2a +#define GC_EXCEPTNUM_GPIO1_GPIO6INT 0x2b +#define GC_EXCEPTNUM_GPIO1_GPIO7INT 0x2c +#define GC_EXCEPTNUM_GPIO1_GPIO8INT 0x2d +#define GC_EXCEPTNUM_GPIO1_GPIO9INT 0x2e +#define GC_EXCEPTNUM_GPIO1_GPIO10INT 0x2f +#define GC_EXCEPTNUM_GPIO1_GPIO11INT 0x30 +#define GC_EXCEPTNUM_GPIO1_GPIO12INT 0x31 +#define GC_EXCEPTNUM_GPIO1_GPIO13INT 0x32 +#define GC_EXCEPTNUM_GPIO1_GPIO14INT 0x33 +#define GC_EXCEPTNUM_GPIO1_GPIO15INT 0x34 +#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT 0x24 +#define GC_EXCEPTNUM_I2C0_I2CINT 0x38 +#define GC_EXCEPTNUM_I2C1_I2CINT 0x39 +#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT 0x35 +#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x36 +#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x37 +#define GC_EXCEPTNUM_PMU_PMUINT 0x3a +#define GC_EXCEPTNUM_SHA0_DSHA_INT 0x3b +#define GC_EXCEPTNUM_SPI0_SPITXINT 0x3c +#define GC_EXCEPTNUM_SPS0_REGION0_BUF_LVL 0x3f +#define GC_EXCEPTNUM_SPS0_REGION1_BUF_LVL 0x40 +#define GC_EXCEPTNUM_SPS0_REGION2_BUF_LVL 0x41 +#define GC_EXCEPTNUM_SPS0_REGION3_BUF_LVL 0x42 +#define GC_EXCEPTNUM_SPS0_ROM_CMD_END 0x43 +#define GC_EXCEPTNUM_SPS0_ROM_CMD_START 0x44 +#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR 0x3d +#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR 0x3e +#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR 0x45 +#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR 0x46 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0 0x47 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1 0x48 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2 0x49 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3 0x4a +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4 0x4b +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5 0x4c +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6 0x4d +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7 0x4e +#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR 0x4f +#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR 0x50 +#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR 0x51 +#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT 0x52 +#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT 0x53 +#define GC_EXCEPTNUM_TEMP0_MAX_TEMP_DIFF_INT 0x54 +#define GC_EXCEPTNUM_TEMP0_MAX_TEMP_INT 0x55 +#define GC_EXCEPTNUM_TEMP0_MIN_TEMP_INT 0x56 +#define GC_EXCEPTNUM_TIMEHS0_TIMINT1 0x58 +#define GC_EXCEPTNUM_TIMEHS0_TIMINT2 0x59 +#define GC_EXCEPTNUM_TIMEHS0_TIMINTC 0x57 +#define GC_EXCEPTNUM_TIMEHS1_TIMINT1 0x5b +#define GC_EXCEPTNUM_TIMEHS1_TIMINT2 0x5c +#define GC_EXCEPTNUM_TIMEHS1_TIMINTC 0x5a +#define GC_EXCEPTNUM_TIMELS0_TIMINT0 0x5d +#define GC_EXCEPTNUM_TIMELS0_TIMINT1 0x5e +#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT 0x5f +#define GC_EXCEPTNUM_TRNG0_INTR_CALC_DONE_INT 0x60 +#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0x61 +#define GC_EXCEPTNUM_TRNG0_INTR_STAT_30_70_INT 0x62 +#define GC_EXCEPTNUM_TRNG0_INTR_STAT_40_60_INT 0x63 +#define GC_EXCEPTNUM_TRNG0_INTR_TIMEOUT_INT 0x64 +#define GC_EXCEPTNUM_UART0_RXBINT 0x65 +#define GC_EXCEPTNUM_UART0_RXFINT 0x66 +#define GC_EXCEPTNUM_UART0_RXINT 0x67 +#define GC_EXCEPTNUM_UART0_RXOVINT 0x68 +#define GC_EXCEPTNUM_UART0_RXTOINT 0x69 +#define GC_EXCEPTNUM_UART0_TXINT 0x6a +#define GC_EXCEPTNUM_UART0_TXOVINT 0x6b +#define GC_EXCEPTNUM_UART1_RXBINT 0x6c +#define GC_EXCEPTNUM_UART1_RXFINT 0x6d +#define GC_EXCEPTNUM_UART1_RXINT 0x6e +#define GC_EXCEPTNUM_UART1_RXOVINT 0x6f +#define GC_EXCEPTNUM_UART1_RXTOINT 0x70 +#define GC_EXCEPTNUM_UART1_TXINT 0x71 +#define GC_EXCEPTNUM_UART1_TXOVINT 0x72 +#define GC_EXCEPTNUM_UART2_RXBINT 0x73 +#define GC_EXCEPTNUM_UART2_RXFINT 0x74 +#define GC_EXCEPTNUM_UART2_RXINT 0x75 +#define GC_EXCEPTNUM_UART2_RXOVINT 0x76 +#define GC_EXCEPTNUM_UART2_RXTOINT 0x77 +#define GC_EXCEPTNUM_UART2_TXINT 0x78 +#define GC_EXCEPTNUM_UART2_TXOVINT 0x79 +#define GC_EXCEPTNUM_USB0_USBINTR 0x7a +#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT 0x7b +#define GC_IRQNUM_RESET 0 +#define GC_IRQNUM_NMI 0 +#define GC_IRQNUM_HARDFAULT 0 +#define GC_IRQNUM_MEMORYMANAGEMENT 0 +#define GC_IRQNUM_BUSFAULT 0 +#define GC_IRQNUM_USAGEFAULT 0 +#define GC_IRQNUM_RESERVED7 0 +#define GC_IRQNUM_RESERVED8 0 +#define GC_IRQNUM_RESERVED9 0 +#define GC_IRQNUM_RESERVED10 0 +#define GC_IRQNUM_SVCALL 0 +#define GC_IRQNUM_DEBUGMONITOR 0 +#define GC_IRQNUM_RESERVED13 0 +#define GC_IRQNUM_PENDSV 0 +#define GC_IRQNUM_SYSTICK 0 +#define GC_IRQNUM_CAMO0_BREACH_INT 0 +#define GC_IRQNUM_FLASH0_EDONEINT 1 +#define GC_IRQNUM_FLASH0_PDONEINT 2 +#define GC_IRQNUM_GPIO0_GPIO0INT 4 +#define GC_IRQNUM_GPIO0_GPIO1INT 5 +#define GC_IRQNUM_GPIO0_GPIO2INT 6 +#define GC_IRQNUM_GPIO0_GPIO3INT 7 +#define GC_IRQNUM_GPIO0_GPIO4INT 8 +#define GC_IRQNUM_GPIO0_GPIO5INT 9 +#define GC_IRQNUM_GPIO0_GPIO6INT 10 +#define GC_IRQNUM_GPIO0_GPIO7INT 11 +#define GC_IRQNUM_GPIO0_GPIO8INT 12 +#define GC_IRQNUM_GPIO0_GPIO9INT 13 +#define GC_IRQNUM_GPIO0_GPIO10INT 14 +#define GC_IRQNUM_GPIO0_GPIO11INT 15 +#define GC_IRQNUM_GPIO0_GPIO12INT 16 +#define GC_IRQNUM_GPIO0_GPIO13INT 17 +#define GC_IRQNUM_GPIO0_GPIO14INT 18 +#define GC_IRQNUM_GPIO0_GPIO15INT 19 +#define GC_IRQNUM_GPIO0_GPIOCOMBINT 3 +#define GC_IRQNUM_GPIO1_GPIO0INT 21 +#define GC_IRQNUM_GPIO1_GPIO1INT 22 +#define GC_IRQNUM_GPIO1_GPIO2INT 23 +#define GC_IRQNUM_GPIO1_GPIO3INT 24 +#define GC_IRQNUM_GPIO1_GPIO4INT 25 +#define GC_IRQNUM_GPIO1_GPIO5INT 26 +#define GC_IRQNUM_GPIO1_GPIO6INT 27 +#define GC_IRQNUM_GPIO1_GPIO7INT 28 +#define GC_IRQNUM_GPIO1_GPIO8INT 29 +#define GC_IRQNUM_GPIO1_GPIO9INT 30 +#define GC_IRQNUM_GPIO1_GPIO10INT 31 +#define GC_IRQNUM_GPIO1_GPIO11INT 32 +#define GC_IRQNUM_GPIO1_GPIO12INT 33 +#define GC_IRQNUM_GPIO1_GPIO13INT 34 +#define GC_IRQNUM_GPIO1_GPIO14INT 35 +#define GC_IRQNUM_GPIO1_GPIO15INT 36 +#define GC_IRQNUM_GPIO1_GPIOCOMBINT 20 +#define GC_IRQNUM_I2C0_I2CINT 40 +#define GC_IRQNUM_I2C1_I2CINT 41 +#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT 37 +#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT 38 +#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT 39 +#define GC_IRQNUM_PMU_PMUINT 42 +#define GC_IRQNUM_SHA0_DSHA_INT 43 +#define GC_IRQNUM_SPI0_SPITXINT 44 +#define GC_IRQNUM_SPS0_REGION0_BUF_LVL 47 +#define GC_IRQNUM_SPS0_REGION1_BUF_LVL 48 +#define GC_IRQNUM_SPS0_REGION2_BUF_LVL 49 +#define GC_IRQNUM_SPS0_REGION3_BUF_LVL 50 +#define GC_IRQNUM_SPS0_ROM_CMD_END 51 +#define GC_IRQNUM_SPS0_ROM_CMD_START 52 +#define GC_IRQNUM_SPS0_CS_ASSERT_INTR 45 +#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR 46 +#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR 53 +#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR 54 +#define GC_IRQNUM_SPS0_SPSCTRLINT0 55 +#define GC_IRQNUM_SPS0_SPSCTRLINT1 56 +#define GC_IRQNUM_SPS0_SPSCTRLINT2 57 +#define GC_IRQNUM_SPS0_SPSCTRLINT3 58 +#define GC_IRQNUM_SPS0_SPSCTRLINT4 59 +#define GC_IRQNUM_SPS0_SPSCTRLINT5 60 +#define GC_IRQNUM_SPS0_SPSCTRLINT6 61 +#define GC_IRQNUM_SPS0_SPSCTRLINT7 62 +#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR 63 +#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR 64 +#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR 65 +#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT 66 +#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT 67 +#define GC_IRQNUM_TEMP0_MAX_TEMP_DIFF_INT 68 +#define GC_IRQNUM_TEMP0_MAX_TEMP_INT 69 +#define GC_IRQNUM_TEMP0_MIN_TEMP_INT 70 +#define GC_IRQNUM_TIMEHS0_TIMINT1 72 +#define GC_IRQNUM_TIMEHS0_TIMINT2 73 +#define GC_IRQNUM_TIMEHS0_TIMINTC 71 +#define GC_IRQNUM_TIMEHS1_TIMINT1 75 +#define GC_IRQNUM_TIMEHS1_TIMINT2 76 +#define GC_IRQNUM_TIMEHS1_TIMINTC 74 +#define GC_IRQNUM_TIMELS0_TIMINT0 77 +#define GC_IRQNUM_TIMELS0_TIMINT1 78 +#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT 79 +#define GC_IRQNUM_TRNG0_INTR_CALC_DONE_INT 80 +#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 81 +#define GC_IRQNUM_TRNG0_INTR_STAT_30_70_INT 82 +#define GC_IRQNUM_TRNG0_INTR_STAT_40_60_INT 83 +#define GC_IRQNUM_TRNG0_INTR_TIMEOUT_INT 84 +#define GC_IRQNUM_UART0_RXBINT 85 +#define GC_IRQNUM_UART0_RXFINT 86 +#define GC_IRQNUM_UART0_RXINT 87 +#define GC_IRQNUM_UART0_RXOVINT 88 +#define GC_IRQNUM_UART0_RXTOINT 89 +#define GC_IRQNUM_UART0_TXINT 90 +#define GC_IRQNUM_UART0_TXOVINT 91 +#define GC_IRQNUM_UART1_RXBINT 92 +#define GC_IRQNUM_UART1_RXFINT 93 +#define GC_IRQNUM_UART1_RXINT 94 +#define GC_IRQNUM_UART1_RXOVINT 95 +#define GC_IRQNUM_UART1_RXTOINT 96 +#define GC_IRQNUM_UART1_TXINT 97 +#define GC_IRQNUM_UART1_TXOVINT 98 +#define GC_IRQNUM_UART2_RXBINT 99 +#define GC_IRQNUM_UART2_RXFINT 100 +#define GC_IRQNUM_UART2_RXINT 101 +#define GC_IRQNUM_UART2_RXOVINT 102 +#define GC_IRQNUM_UART2_RXTOINT 103 +#define GC_IRQNUM_UART2_TXINT 104 +#define GC_IRQNUM_UART2_TXOVINT 105 +#define GC_IRQNUM_USB0_USBINTR 106 +#define GC_IRQNUM_WATCHDOG0_WDOGINT 107 +#define GC_AES0_BASE_ADDR 0x40440000 +#define GC_AES1_BASE_ADDR 0x40450000 +#define GC_CAMO0_BASE_ADDR 0x40470000 +#define GC_FLASH0_BASE_ADDR 0x40710000 +#define GC_GLOBALSEC0_BASE_ADDR 0x404b0000 +#define GC_GPIO0_BASE_ADDR 0x40200000 +#define GC_GPIO1_BASE_ADDR 0x40210000 +#define GC_I2C0_BASE_ADDR 0x40520000 +#define GC_I2C1_BASE_ADDR 0x40530000 +#define GC_I2CS0_BASE_ADDR 0x40480000 +#define GC_MAU_BASE_ADDR 0x40080000 +#define GC_PAU_BASE_ADDR 0x40090000 +#define GC_PINMUX_BASE_ADDR 0x40060000 +#define GC_PMU_BASE_ADDR 0x40000000 +#define GC_M3_BASE_ADDR 0xe0000000 +#define GC_RBOX0_BASE_ADDR 0x40460000 +#define GC_RTC0_BASE_ADDR 0x40400000 +#define GC_SHA0_BASE_ADDR 0x40700000 +#define GC_SPI0_BASE_ADDR 0x40500000 +#define GC_SPS0_BASE_ADDR 0x40510000 +#define GC_SWDP0_BASE_ADDR 0x40590000 +#define GC_TEMP0_BASE_ADDR 0x40490000 +#define GC_TIMEHS0_BASE_ADDR 0x40570000 +#define GC_TIMEHS1_BASE_ADDR 0x40580000 +#define GC_TIMELS0_BASE_ADDR 0x40430000 +#define GC_TRNG0_BASE_ADDR 0x404a0000 +#define GC_UART0_BASE_ADDR 0x40540000 +#define GC_UART1_BASE_ADDR 0x40550000 +#define GC_UART2_BASE_ADDR 0x40560000 +#define GC_USB0_BASE_ADDR 0x40300000 +#define GC_WATCHDOG0_BASE_ADDR 0x40410000 +#define GC_XO0_BASE_ADDR 0x40420000 +#define GC_AES_CTRL_OFFSET 0x0 +#define GC_AES_CTRL_DEFAULT 0x0 +#define GC_AES_B0_START_OFFSET 0x4 +#define GC_AES_B0_START_DEFAULT 0x0 +#define GC_AES_B0_DATA0_OFFSET 0x8 +#define GC_AES_B0_DATA0_DEFAULT 0x0 +#define GC_AES_B0_DATA1_OFFSET 0xc +#define GC_AES_B0_DATA1_DEFAULT 0x0 +#define GC_AES_B0_DATA2_OFFSET 0x10 +#define GC_AES_B0_DATA2_DEFAULT 0x0 +#define GC_AES_B0_DATA3_OFFSET 0x14 +#define GC_AES_B0_DATA3_DEFAULT 0x0 +#define GC_AES_B1_START_OFFSET 0x18 +#define GC_AES_B1_START_DEFAULT 0x0 +#define GC_AES_B1_DATA0_OFFSET 0x1c +#define GC_AES_B1_DATA0_DEFAULT 0x0 +#define GC_AES_B1_DATA1_OFFSET 0x20 +#define GC_AES_B1_DATA1_DEFAULT 0x0 +#define GC_AES_B1_DATA2_OFFSET 0x24 +#define GC_AES_B1_DATA2_DEFAULT 0x0 +#define GC_AES_B1_DATA3_OFFSET 0x28 +#define GC_AES_B1_DATA3_DEFAULT 0x0 +#define GC_AES_KEY0_OFFSET 0x2c +#define GC_AES_KEY0_DEFAULT 0x0 +#define GC_AES_KEY1_OFFSET 0x30 +#define GC_AES_KEY1_DEFAULT 0x0 +#define GC_AES_KEY2_OFFSET 0x34 +#define GC_AES_KEY2_DEFAULT 0x0 +#define GC_AES_KEY3_OFFSET 0x38 +#define GC_AES_KEY3_DEFAULT 0x0 +#define GC_AES_KEY4_OFFSET 0x3c +#define GC_AES_KEY4_DEFAULT 0x0 +#define GC_AES_KEY5_OFFSET 0x40 +#define GC_AES_KEY5_DEFAULT 0x0 +#define GC_AES_KEY6_OFFSET 0x44 +#define GC_AES_KEY6_DEFAULT 0x0 +#define GC_AES_KEY7_OFFSET 0x48 +#define GC_AES_KEY7_DEFAULT 0x0 +#define GC_AES_KEY_START_OFFSET 0x4c +#define GC_AES_KEY_START_DEFAULT 0x0 +#define GC_AES_CTR0_OFFSET 0x50 +#define GC_AES_CTR0_DEFAULT 0x0 +#define GC_AES_CTR1_OFFSET 0x54 +#define GC_AES_CTR1_DEFAULT 0x0 +#define GC_AES_CTR2_OFFSET 0x58 +#define GC_AES_CTR2_DEFAULT 0x0 +#define GC_AES_CTR3_OFFSET 0x5c +#define GC_AES_CTR3_DEFAULT 0x0 +#define GC_AES_LFSR_CTL_OFFSET 0x60 +#define GC_AES_LFSR_CTL_DEFAULT 0x1f +#define GC_AES_VERSION_OFFSET 0x64 +#define GC_AES_VERSION_DEFAULT 0x800be5c +#define GC_CAMO_CLKPERIOD_X256_OFFSET 0x0 +#define GC_CAMO_CLKPERIOD_X256_DEFAULT 0x4 +#define GC_CAMO_RESTART_PRBS_OFFSET 0x4 +#define GC_CAMO_RESTART_PRBS_DEFAULT 0x0 +#define GC_CAMO_INT_ENABLE_OFFSET 0x8 +#define GC_CAMO_INT_ENABLE_DEFAULT 0x0 +#define GC_CAMO_INT_STATE_OFFSET 0xc +#define GC_CAMO_INT_STATE_DEFAULT 0x0 +#define GC_CAMO_INT_TEST_OFFSET 0x10 +#define GC_CAMO_INT_TEST_DEFAULT 0x0 +#define GC_CAMO_BREACH_COUNT_OFFSET 0x14 +#define GC_CAMO_BREACH_COUNT_DEFAULT 0x0 +#define GC_CAMO_CUR_VAL0_OFFSET 0x18 +#define GC_CAMO_CUR_VAL0_DEFAULT 0x0 +#define GC_CAMO_CUR_VAL1_OFFSET 0x1c +#define GC_CAMO_CUR_VAL1_DEFAULT 0x0 +#define GC_CAMO_CUR_VAL2_OFFSET 0x20 +#define GC_CAMO_CUR_VAL2_DEFAULT 0x0 +#define GC_CAMO_CUR_VAL3_OFFSET 0x24 +#define GC_CAMO_CUR_VAL3_DEFAULT 0x0 +#define GC_CAMO_VERSION_OFFSET 0x28 +#define GC_CAMO_VERSION_DEFAULT 0x500ba73 +#define GC_FLASH_FSH_PE_CONTROL0_OFFSET 0x0 +#define GC_FLASH_FSH_PE_CONTROL0_DEFAULT 0x0 +#define GC_FLASH_FSH_PE_CONTROL0_PROG 0x27182818 +#define GC_FLASH_FSH_PE_CONTROL0_ERASE 0x31415927 +#define GC_FLASH_FSH_PE_CONTROL0_BULKERASE 0x1d1e2bad +#define GC_FLASH_FSH_PE_CONTROL0_READ 0x16021765 +#define GC_FLASH_FSH_PE_CONTROL1_OFFSET 0x4 +#define GC_FLASH_FSH_PE_CONTROL1_DEFAULT 0x0 +#define GC_FLASH_FSH_PE_CONTROL1_PROG 0x27182818 +#define GC_FLASH_FSH_PE_CONTROL1_ERASE 0x31415927 +#define GC_FLASH_FSH_PE_CONTROL1_BULKERASE 0x1d1e2bad +#define GC_FLASH_FSH_PE_CONTROL1_READ 0x16021765 +#define GC_FLASH_FSH_TRANS_OFFSET 0x8 +#define GC_FLASH_FSH_TRANS_DEFAULT 0x0 +#define GC_FLASH_FSH_ICTRL_OFFSET 0xc +#define GC_FLASH_FSH_ICTRL_DEFAULT 0x0 +#define GC_FLASH_FSH_ISTATE_OFFSET 0x10 +#define GC_FLASH_FSH_ISTATE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD0_UNLOCK_OFFSET 0x14 +#define GC_FLASH_FSH_OVRD0_UNLOCK_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD0_UNLOCK_KEY 0x13806488 +#define GC_FLASH_FSH_OVRD1_UNLOCK_OFFSET 0x18 +#define GC_FLASH_FSH_OVRD1_UNLOCK_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD1_UNLOCK_KEY 0x13806488 +#define GC_FLASH_FSH_OVRD_SIGVAL_DIN_OFFSET 0x1c +#define GC_FLASH_FSH_OVRD_SIGVAL_DIN_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_OFFSET 0x20 +#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_DEFAULT 0x0 +#define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_OFFSET 0x2c +#define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_DEFAULT 0x0 +#define GC_FLASH_FSH_DOUT_VAL0_OFFSET 0x30 +#define GC_FLASH_FSH_DOUT_VAL0_DEFAULT 0x0 +#define GC_FLASH_FSH_DOUT_VAL1_OFFSET 0x34 +#define GC_FLASH_FSH_DOUT_VAL1_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA0_OFFSET 0x38 +#define GC_FLASH_FSH_WR_DATA0_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA1_OFFSET 0x3c +#define GC_FLASH_FSH_WR_DATA1_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA2_OFFSET 0x40 +#define GC_FLASH_FSH_WR_DATA2_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA3_OFFSET 0x44 +#define GC_FLASH_FSH_WR_DATA3_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA4_OFFSET 0x48 +#define GC_FLASH_FSH_WR_DATA4_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA5_OFFSET 0x4c +#define GC_FLASH_FSH_WR_DATA5_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA6_OFFSET 0x50 +#define GC_FLASH_FSH_WR_DATA6_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA7_OFFSET 0x54 +#define GC_FLASH_FSH_WR_DATA7_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA8_OFFSET 0x58 +#define GC_FLASH_FSH_WR_DATA8_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA9_OFFSET 0x5c +#define GC_FLASH_FSH_WR_DATA9_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA10_OFFSET 0x60 +#define GC_FLASH_FSH_WR_DATA10_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA11_OFFSET 0x64 +#define GC_FLASH_FSH_WR_DATA11_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA12_OFFSET 0x68 +#define GC_FLASH_FSH_WR_DATA12_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA13_OFFSET 0x6c +#define GC_FLASH_FSH_WR_DATA13_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA14_OFFSET 0x70 +#define GC_FLASH_FSH_WR_DATA14_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA15_OFFSET 0x74 +#define GC_FLASH_FSH_WR_DATA15_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA16_OFFSET 0x78 +#define GC_FLASH_FSH_WR_DATA16_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA17_OFFSET 0x7c +#define GC_FLASH_FSH_WR_DATA17_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA18_OFFSET 0x80 +#define GC_FLASH_FSH_WR_DATA18_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA19_OFFSET 0x84 +#define GC_FLASH_FSH_WR_DATA19_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA20_OFFSET 0x88 +#define GC_FLASH_FSH_WR_DATA20_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA21_OFFSET 0x8c +#define GC_FLASH_FSH_WR_DATA21_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA22_OFFSET 0x90 +#define GC_FLASH_FSH_WR_DATA22_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA23_OFFSET 0x94 +#define GC_FLASH_FSH_WR_DATA23_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA24_OFFSET 0x98 +#define GC_FLASH_FSH_WR_DATA24_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA25_OFFSET 0x9c +#define GC_FLASH_FSH_WR_DATA25_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA26_OFFSET 0xa0 +#define GC_FLASH_FSH_WR_DATA26_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA27_OFFSET 0xa4 +#define GC_FLASH_FSH_WR_DATA27_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA28_OFFSET 0xa8 +#define GC_FLASH_FSH_WR_DATA28_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA29_OFFSET 0xac +#define GC_FLASH_FSH_WR_DATA29_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA30_OFFSET 0xb0 +#define GC_FLASH_FSH_WR_DATA30_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA31_OFFSET 0xb4 +#define GC_FLASH_FSH_WR_DATA31_DEFAULT 0x0 +#define GC_FLASH_FSH_PE_EN_OFFSET 0xb8 +#define GC_FLASH_FSH_PE_EN_DEFAULT 0x0 +#define GC_FLASH_FSH_PE_EN_KEY 0xb11924e1 +#define GC_FLASH_FSH_REDUN0_OFFSET 0xbc +#define GC_FLASH_FSH_REDUN0_DEFAULT 0x0 +#define GC_FLASH_FSH_REDUN1_OFFSET 0xc0 +#define GC_FLASH_FSH_REDUN1_DEFAULT 0x0 +#define GC_FLASH_FSH_ERROR_OFFSET 0xc4 +#define GC_FLASH_FSH_ERROR_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_OFFSET 0xc8 +#define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_DEFAULT 0x1 +#define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_OFFSET 0xcc +#define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_OFFSET 0xd0 +#define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_OFFSET 0xd4 +#define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_OFFSET 0xd8 +#define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_OFFSET 0xdc +#define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_OFFSET 0xe0 +#define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_OFFSET 0xe4 +#define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_OFFSET 0xe8 +#define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_OFFSET 0xec +#define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_OFFSET 0xf0 +#define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_OFFSET 0xf4 +#define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_DEFAULT 0x1 +#define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_OFFSET 0xf8 +#define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_DEFAULT 0x30e +#define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_OFFSET 0xfc +#define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_OFFSET 0x100 +#define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_DEFAULT 0x21b +#define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_OFFSET 0x104 +#define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_DEFAULT 0x16e +#define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_OFFSET 0x108 +#define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_DEFAULT 0x19f +#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_OFFSET 0x10c +#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_DEFAULT 0x16d +#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_OFFSET 0x110 +#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_DEFAULT 0x1a0 +#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_OFFSET 0x114 +#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_DEFAULT 0x1 +#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_OFFSET 0x118 +#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_DEFAULT 0x1a0 +#define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_OFFSET 0x11c +#define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_DEFAULT 0x7a +#define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_OFFSET 0x120 +#define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_DEFAULT 0x21a +#define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_OFFSET 0x124 +#define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_DEFAULT 0x1 +#define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_OFFSET 0x128 +#define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_DEFAULT 0xc075 +#define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_OFFSET 0x12c +#define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_OFFSET 0x130 +#define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_DEFAULT 0xbf82 +#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_OFFSET 0x134 +#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_DEFAULT 0x1 +#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_OFFSET 0x138 +#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_DEFAULT 0xbf07 +#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_OFFSET 0x13c +#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_DEFAULT 0x7a +#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_OFFSET 0x140 +#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_DEFAULT 0xbf81 +#define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_OFFSET 0x144 +#define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_DEFAULT 0x1 +#define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_OFFSET 0x148 +#define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_DEFAULT 0xc982 +#define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_OFFSET 0x14c +#define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_OFFSET 0x150 +#define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_DEFAULT 0xc88f +#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_OFFSET 0x154 +#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_DEFAULT 0x1 +#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_OFFSET 0x158 +#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_DEFAULT 0xbf07 +#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_OFFSET 0x15c +#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_DEFAULT 0x0 +#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_OFFSET 0x160 +#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_DEFAULT 0xc88f +#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_OFFSET 0x164 +#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_DEFAULT 0x7a +#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_OFFSET 0x168 +#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_DEFAULT 0xc88e +#define GC_FLASH_FSH_DBG_OFFSET 0x16c +#define GC_FLASH_FSH_DBG_DEFAULT 0x0 +#define GC_FLASH_FSH_ITCR_OFFSET 0xf00 +#define GC_FLASH_FSH_ITCR_DEFAULT 0x0 +#define GC_FLASH_FSH_ITOP_OFFSET 0xf04 +#define GC_FLASH_FSH_ITOP_DEFAULT 0x0 +#define GC_GLOBALSEC_NEED_ZERO_REG_OFFSET 0x0 +#define GC_GLOBALSEC_NEED_ZERO_REG_DEFAULT 0x0 +#define GC_GLOBALSEC_DUMMYKEY0_OFFSET 0x1598 +#define GC_GLOBALSEC_DUMMYKEY0_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_DEFAULT 0x0 +#define GC_GLOBALSEC_LFSR_WR_DATA_OFFSET 0x317c +#define GC_GLOBALSEC_LFSR_WR_DATA_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_MONITOR_OFFSET 0x3724 +#define GC_GLOBALSEC_SEC_MONITOR_DEFAULT 0x0 +#define GC_GLOBALSEC_PERR_OFFSET 0x49a8 +#define GC_GLOBALSEC_PERR_DEFAULT 0x0 +#define GC_GLOBALSEC_INTERNAL_STATE0_OFFSET 0x4ee8 +#define GC_GLOBALSEC_INTERNAL_STATE0_DEFAULT 0x0 +#define GC_GLOBALSEC_INTERNAL_STATE1_OFFSET 0x6614 +#define GC_GLOBALSEC_INTERNAL_STATE1_DEFAULT 0x0 +#define GC_GLOBALSEC_INTERNAL_STATE2_OFFSET 0x6fe4 +#define GC_GLOBALSEC_INTERNAL_STATE2_DEFAULT 0x0 +#define GC_GLOBALSEC_INTERNAL_STATE3_OFFSET 0x77fc +#define GC_GLOBALSEC_INTERNAL_STATE3_DEFAULT 0x0 +#define GC_GLOBALSEC_INTERNAL_STATE4_OFFSET 0x8284 +#define GC_GLOBALSEC_INTERNAL_STATE4_DEFAULT 0x0 +#define GC_GLOBALSEC_DUMMYKEY1_OFFSET 0xaf04 +#define GC_GLOBALSEC_DUMMYKEY1_DEFAULT 0x0 +#define GC_GLOBALSEC_DBG_CONTROL_OFFSET 0xb1dc +#define GC_GLOBALSEC_DBG_CONTROL_DEFAULT 0x0 +#define GC_GLOBALSEC_DUMMYKEY2_OFFSET 0xb2ac +#define GC_GLOBALSEC_DUMMYKEY2_DEFAULT 0x0 +#define GC_GLOBALSEC_VERSION_OFFSET 0xb2b0 +#define GC_GLOBALSEC_VERSION_DEFAULT 0x100b407 +#define GC_GPIO_DATAIN_OFFSET 0x0 +#define GC_GPIO_DATAIN_DEFAULT 0x0 +#define GC_GPIO_DOUT_OFFSET 0x4 +#define GC_GPIO_DOUT_DEFAULT 0x0 +#define GC_GPIO_SETDOUTEN_OFFSET 0x10 +#define GC_GPIO_SETDOUTEN_DEFAULT 0x0 +#define GC_GPIO_CLRDOUTEN_OFFSET 0x14 +#define GC_GPIO_CLRDOUTEN_DEFAULT 0x0 +#define GC_GPIO_RESERVED0_OFFSET 0x18 +#define GC_GPIO_RESERVED0_DEFAULT 0x0 +#define GC_GPIO_RESERVED1_OFFSET 0x1c +#define GC_GPIO_RESERVED1_DEFAULT 0x0 +#define GC_GPIO_SETINTEN_OFFSET 0x20 +#define GC_GPIO_SETINTEN_DEFAULT 0x0 +#define GC_GPIO_CLRINTEN_OFFSET 0x24 +#define GC_GPIO_CLRINTEN_DEFAULT 0x0 +#define GC_GPIO_SETINTTYPE_OFFSET 0x28 +#define GC_GPIO_SETINTTYPE_DEFAULT 0x0 +#define GC_GPIO_CLRINTTYPE_OFFSET 0x2c +#define GC_GPIO_CLRINTTYPE_DEFAULT 0x0 +#define GC_GPIO_SETINTPOL_OFFSET 0x30 +#define GC_GPIO_SETINTPOL_DEFAULT 0x0 +#define GC_GPIO_CLRINTPOL_OFFSET 0x34 +#define GC_GPIO_CLRINTPOL_DEFAULT 0x0 +#define GC_GPIO_CLRINTSTAT_OFFSET 0x38 +#define GC_GPIO_CLRINTSTAT_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_400_OFFSET 0x400 +#define GC_GPIO_MASKLOWBYTE_400_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_404_OFFSET 0x404 +#define GC_GPIO_MASKLOWBYTE_404_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_408_OFFSET 0x408 +#define GC_GPIO_MASKLOWBYTE_408_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_40C_OFFSET 0x40c +#define GC_GPIO_MASKLOWBYTE_40C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_410_OFFSET 0x410 +#define GC_GPIO_MASKLOWBYTE_410_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_414_OFFSET 0x414 +#define GC_GPIO_MASKLOWBYTE_414_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_418_OFFSET 0x418 +#define GC_GPIO_MASKLOWBYTE_418_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_41C_OFFSET 0x41c +#define GC_GPIO_MASKLOWBYTE_41C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_420_OFFSET 0x420 +#define GC_GPIO_MASKLOWBYTE_420_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_424_OFFSET 0x424 +#define GC_GPIO_MASKLOWBYTE_424_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_428_OFFSET 0x428 +#define GC_GPIO_MASKLOWBYTE_428_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_42C_OFFSET 0x42c +#define GC_GPIO_MASKLOWBYTE_42C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_430_OFFSET 0x430 +#define GC_GPIO_MASKLOWBYTE_430_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_434_OFFSET 0x434 +#define GC_GPIO_MASKLOWBYTE_434_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_438_OFFSET 0x438 +#define GC_GPIO_MASKLOWBYTE_438_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_43C_OFFSET 0x43c +#define GC_GPIO_MASKLOWBYTE_43C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_440_OFFSET 0x440 +#define GC_GPIO_MASKLOWBYTE_440_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_444_OFFSET 0x444 +#define GC_GPIO_MASKLOWBYTE_444_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_448_OFFSET 0x448 +#define GC_GPIO_MASKLOWBYTE_448_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_44C_OFFSET 0x44c +#define GC_GPIO_MASKLOWBYTE_44C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_450_OFFSET 0x450 +#define GC_GPIO_MASKLOWBYTE_450_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_454_OFFSET 0x454 +#define GC_GPIO_MASKLOWBYTE_454_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_458_OFFSET 0x458 +#define GC_GPIO_MASKLOWBYTE_458_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_45C_OFFSET 0x45c +#define GC_GPIO_MASKLOWBYTE_45C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_460_OFFSET 0x460 +#define GC_GPIO_MASKLOWBYTE_460_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_464_OFFSET 0x464 +#define GC_GPIO_MASKLOWBYTE_464_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_468_OFFSET 0x468 +#define GC_GPIO_MASKLOWBYTE_468_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_46C_OFFSET 0x46c +#define GC_GPIO_MASKLOWBYTE_46C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_470_OFFSET 0x470 +#define GC_GPIO_MASKLOWBYTE_470_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_474_OFFSET 0x474 +#define GC_GPIO_MASKLOWBYTE_474_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_478_OFFSET 0x478 +#define GC_GPIO_MASKLOWBYTE_478_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_47C_OFFSET 0x47c +#define GC_GPIO_MASKLOWBYTE_47C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_480_OFFSET 0x480 +#define GC_GPIO_MASKLOWBYTE_480_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_484_OFFSET 0x484 +#define GC_GPIO_MASKLOWBYTE_484_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_488_OFFSET 0x488 +#define GC_GPIO_MASKLOWBYTE_488_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_48C_OFFSET 0x48c +#define GC_GPIO_MASKLOWBYTE_48C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_490_OFFSET 0x490 +#define GC_GPIO_MASKLOWBYTE_490_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_494_OFFSET 0x494 +#define GC_GPIO_MASKLOWBYTE_494_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_498_OFFSET 0x498 +#define GC_GPIO_MASKLOWBYTE_498_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_49C_OFFSET 0x49c +#define GC_GPIO_MASKLOWBYTE_49C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4A0_OFFSET 0x4a0 +#define GC_GPIO_MASKLOWBYTE_4A0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4A4_OFFSET 0x4a4 +#define GC_GPIO_MASKLOWBYTE_4A4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4A8_OFFSET 0x4a8 +#define GC_GPIO_MASKLOWBYTE_4A8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4AC_OFFSET 0x4ac +#define GC_GPIO_MASKLOWBYTE_4AC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4B0_OFFSET 0x4b0 +#define GC_GPIO_MASKLOWBYTE_4B0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4B4_OFFSET 0x4b4 +#define GC_GPIO_MASKLOWBYTE_4B4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4B8_OFFSET 0x4b8 +#define GC_GPIO_MASKLOWBYTE_4B8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4BC_OFFSET 0x4bc +#define GC_GPIO_MASKLOWBYTE_4BC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4C0_OFFSET 0x4c0 +#define GC_GPIO_MASKLOWBYTE_4C0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4C4_OFFSET 0x4c4 +#define GC_GPIO_MASKLOWBYTE_4C4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4C8_OFFSET 0x4c8 +#define GC_GPIO_MASKLOWBYTE_4C8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4CC_OFFSET 0x4cc +#define GC_GPIO_MASKLOWBYTE_4CC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4D0_OFFSET 0x4d0 +#define GC_GPIO_MASKLOWBYTE_4D0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4D4_OFFSET 0x4d4 +#define GC_GPIO_MASKLOWBYTE_4D4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4D8_OFFSET 0x4d8 +#define GC_GPIO_MASKLOWBYTE_4D8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4DC_OFFSET 0x4dc +#define GC_GPIO_MASKLOWBYTE_4DC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4E0_OFFSET 0x4e0 +#define GC_GPIO_MASKLOWBYTE_4E0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4E4_OFFSET 0x4e4 +#define GC_GPIO_MASKLOWBYTE_4E4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4E8_OFFSET 0x4e8 +#define GC_GPIO_MASKLOWBYTE_4E8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4EC_OFFSET 0x4ec +#define GC_GPIO_MASKLOWBYTE_4EC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4F0_OFFSET 0x4f0 +#define GC_GPIO_MASKLOWBYTE_4F0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4F4_OFFSET 0x4f4 +#define GC_GPIO_MASKLOWBYTE_4F4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4F8_OFFSET 0x4f8 +#define GC_GPIO_MASKLOWBYTE_4F8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_4FC_OFFSET 0x4fc +#define GC_GPIO_MASKLOWBYTE_4FC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_500_OFFSET 0x500 +#define GC_GPIO_MASKLOWBYTE_500_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_504_OFFSET 0x504 +#define GC_GPIO_MASKLOWBYTE_504_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_508_OFFSET 0x508 +#define GC_GPIO_MASKLOWBYTE_508_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_50C_OFFSET 0x50c +#define GC_GPIO_MASKLOWBYTE_50C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_510_OFFSET 0x510 +#define GC_GPIO_MASKLOWBYTE_510_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_514_OFFSET 0x514 +#define GC_GPIO_MASKLOWBYTE_514_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_518_OFFSET 0x518 +#define GC_GPIO_MASKLOWBYTE_518_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_51C_OFFSET 0x51c +#define GC_GPIO_MASKLOWBYTE_51C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_520_OFFSET 0x520 +#define GC_GPIO_MASKLOWBYTE_520_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_524_OFFSET 0x524 +#define GC_GPIO_MASKLOWBYTE_524_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_528_OFFSET 0x528 +#define GC_GPIO_MASKLOWBYTE_528_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_52C_OFFSET 0x52c +#define GC_GPIO_MASKLOWBYTE_52C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_530_OFFSET 0x530 +#define GC_GPIO_MASKLOWBYTE_530_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_534_OFFSET 0x534 +#define GC_GPIO_MASKLOWBYTE_534_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_538_OFFSET 0x538 +#define GC_GPIO_MASKLOWBYTE_538_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_53C_OFFSET 0x53c +#define GC_GPIO_MASKLOWBYTE_53C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_540_OFFSET 0x540 +#define GC_GPIO_MASKLOWBYTE_540_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_544_OFFSET 0x544 +#define GC_GPIO_MASKLOWBYTE_544_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_548_OFFSET 0x548 +#define GC_GPIO_MASKLOWBYTE_548_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_54C_OFFSET 0x54c +#define GC_GPIO_MASKLOWBYTE_54C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_550_OFFSET 0x550 +#define GC_GPIO_MASKLOWBYTE_550_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_554_OFFSET 0x554 +#define GC_GPIO_MASKLOWBYTE_554_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_558_OFFSET 0x558 +#define GC_GPIO_MASKLOWBYTE_558_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_55C_OFFSET 0x55c +#define GC_GPIO_MASKLOWBYTE_55C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_560_OFFSET 0x560 +#define GC_GPIO_MASKLOWBYTE_560_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_564_OFFSET 0x564 +#define GC_GPIO_MASKLOWBYTE_564_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_568_OFFSET 0x568 +#define GC_GPIO_MASKLOWBYTE_568_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_56C_OFFSET 0x56c +#define GC_GPIO_MASKLOWBYTE_56C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_570_OFFSET 0x570 +#define GC_GPIO_MASKLOWBYTE_570_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_574_OFFSET 0x574 +#define GC_GPIO_MASKLOWBYTE_574_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_578_OFFSET 0x578 +#define GC_GPIO_MASKLOWBYTE_578_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_57C_OFFSET 0x57c +#define GC_GPIO_MASKLOWBYTE_57C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_580_OFFSET 0x580 +#define GC_GPIO_MASKLOWBYTE_580_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_584_OFFSET 0x584 +#define GC_GPIO_MASKLOWBYTE_584_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_588_OFFSET 0x588 +#define GC_GPIO_MASKLOWBYTE_588_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_58C_OFFSET 0x58c +#define GC_GPIO_MASKLOWBYTE_58C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_590_OFFSET 0x590 +#define GC_GPIO_MASKLOWBYTE_590_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_594_OFFSET 0x594 +#define GC_GPIO_MASKLOWBYTE_594_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_598_OFFSET 0x598 +#define GC_GPIO_MASKLOWBYTE_598_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_59C_OFFSET 0x59c +#define GC_GPIO_MASKLOWBYTE_59C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5A0_OFFSET 0x5a0 +#define GC_GPIO_MASKLOWBYTE_5A0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5A4_OFFSET 0x5a4 +#define GC_GPIO_MASKLOWBYTE_5A4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5A8_OFFSET 0x5a8 +#define GC_GPIO_MASKLOWBYTE_5A8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5AC_OFFSET 0x5ac +#define GC_GPIO_MASKLOWBYTE_5AC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5B0_OFFSET 0x5b0 +#define GC_GPIO_MASKLOWBYTE_5B0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5B4_OFFSET 0x5b4 +#define GC_GPIO_MASKLOWBYTE_5B4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5B8_OFFSET 0x5b8 +#define GC_GPIO_MASKLOWBYTE_5B8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5BC_OFFSET 0x5bc +#define GC_GPIO_MASKLOWBYTE_5BC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5C0_OFFSET 0x5c0 +#define GC_GPIO_MASKLOWBYTE_5C0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5C4_OFFSET 0x5c4 +#define GC_GPIO_MASKLOWBYTE_5C4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5C8_OFFSET 0x5c8 +#define GC_GPIO_MASKLOWBYTE_5C8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5CC_OFFSET 0x5cc +#define GC_GPIO_MASKLOWBYTE_5CC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5D0_OFFSET 0x5d0 +#define GC_GPIO_MASKLOWBYTE_5D0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5D4_OFFSET 0x5d4 +#define GC_GPIO_MASKLOWBYTE_5D4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5D8_OFFSET 0x5d8 +#define GC_GPIO_MASKLOWBYTE_5D8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5DC_OFFSET 0x5dc +#define GC_GPIO_MASKLOWBYTE_5DC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5E0_OFFSET 0x5e0 +#define GC_GPIO_MASKLOWBYTE_5E0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5E4_OFFSET 0x5e4 +#define GC_GPIO_MASKLOWBYTE_5E4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5E8_OFFSET 0x5e8 +#define GC_GPIO_MASKLOWBYTE_5E8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5EC_OFFSET 0x5ec +#define GC_GPIO_MASKLOWBYTE_5EC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5F0_OFFSET 0x5f0 +#define GC_GPIO_MASKLOWBYTE_5F0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5F4_OFFSET 0x5f4 +#define GC_GPIO_MASKLOWBYTE_5F4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5F8_OFFSET 0x5f8 +#define GC_GPIO_MASKLOWBYTE_5F8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_5FC_OFFSET 0x5fc +#define GC_GPIO_MASKLOWBYTE_5FC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_600_OFFSET 0x600 +#define GC_GPIO_MASKLOWBYTE_600_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_604_OFFSET 0x604 +#define GC_GPIO_MASKLOWBYTE_604_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_608_OFFSET 0x608 +#define GC_GPIO_MASKLOWBYTE_608_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_60C_OFFSET 0x60c +#define GC_GPIO_MASKLOWBYTE_60C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_610_OFFSET 0x610 +#define GC_GPIO_MASKLOWBYTE_610_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_614_OFFSET 0x614 +#define GC_GPIO_MASKLOWBYTE_614_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_618_OFFSET 0x618 +#define GC_GPIO_MASKLOWBYTE_618_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_61C_OFFSET 0x61c +#define GC_GPIO_MASKLOWBYTE_61C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_620_OFFSET 0x620 +#define GC_GPIO_MASKLOWBYTE_620_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_624_OFFSET 0x624 +#define GC_GPIO_MASKLOWBYTE_624_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_628_OFFSET 0x628 +#define GC_GPIO_MASKLOWBYTE_628_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_62C_OFFSET 0x62c +#define GC_GPIO_MASKLOWBYTE_62C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_630_OFFSET 0x630 +#define GC_GPIO_MASKLOWBYTE_630_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_634_OFFSET 0x634 +#define GC_GPIO_MASKLOWBYTE_634_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_638_OFFSET 0x638 +#define GC_GPIO_MASKLOWBYTE_638_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_63C_OFFSET 0x63c +#define GC_GPIO_MASKLOWBYTE_63C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_640_OFFSET 0x640 +#define GC_GPIO_MASKLOWBYTE_640_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_644_OFFSET 0x644 +#define GC_GPIO_MASKLOWBYTE_644_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_648_OFFSET 0x648 +#define GC_GPIO_MASKLOWBYTE_648_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_64C_OFFSET 0x64c +#define GC_GPIO_MASKLOWBYTE_64C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_650_OFFSET 0x650 +#define GC_GPIO_MASKLOWBYTE_650_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_654_OFFSET 0x654 +#define GC_GPIO_MASKLOWBYTE_654_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_658_OFFSET 0x658 +#define GC_GPIO_MASKLOWBYTE_658_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_65C_OFFSET 0x65c +#define GC_GPIO_MASKLOWBYTE_65C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_660_OFFSET 0x660 +#define GC_GPIO_MASKLOWBYTE_660_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_664_OFFSET 0x664 +#define GC_GPIO_MASKLOWBYTE_664_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_668_OFFSET 0x668 +#define GC_GPIO_MASKLOWBYTE_668_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_66C_OFFSET 0x66c +#define GC_GPIO_MASKLOWBYTE_66C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_670_OFFSET 0x670 +#define GC_GPIO_MASKLOWBYTE_670_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_674_OFFSET 0x674 +#define GC_GPIO_MASKLOWBYTE_674_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_678_OFFSET 0x678 +#define GC_GPIO_MASKLOWBYTE_678_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_67C_OFFSET 0x67c +#define GC_GPIO_MASKLOWBYTE_67C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_680_OFFSET 0x680 +#define GC_GPIO_MASKLOWBYTE_680_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_684_OFFSET 0x684 +#define GC_GPIO_MASKLOWBYTE_684_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_688_OFFSET 0x688 +#define GC_GPIO_MASKLOWBYTE_688_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_68C_OFFSET 0x68c +#define GC_GPIO_MASKLOWBYTE_68C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_690_OFFSET 0x690 +#define GC_GPIO_MASKLOWBYTE_690_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_694_OFFSET 0x694 +#define GC_GPIO_MASKLOWBYTE_694_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_698_OFFSET 0x698 +#define GC_GPIO_MASKLOWBYTE_698_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_69C_OFFSET 0x69c +#define GC_GPIO_MASKLOWBYTE_69C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6A0_OFFSET 0x6a0 +#define GC_GPIO_MASKLOWBYTE_6A0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6A4_OFFSET 0x6a4 +#define GC_GPIO_MASKLOWBYTE_6A4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6A8_OFFSET 0x6a8 +#define GC_GPIO_MASKLOWBYTE_6A8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6AC_OFFSET 0x6ac +#define GC_GPIO_MASKLOWBYTE_6AC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6B0_OFFSET 0x6b0 +#define GC_GPIO_MASKLOWBYTE_6B0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6B4_OFFSET 0x6b4 +#define GC_GPIO_MASKLOWBYTE_6B4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6B8_OFFSET 0x6b8 +#define GC_GPIO_MASKLOWBYTE_6B8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6BC_OFFSET 0x6bc +#define GC_GPIO_MASKLOWBYTE_6BC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6C0_OFFSET 0x6c0 +#define GC_GPIO_MASKLOWBYTE_6C0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6C4_OFFSET 0x6c4 +#define GC_GPIO_MASKLOWBYTE_6C4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6C8_OFFSET 0x6c8 +#define GC_GPIO_MASKLOWBYTE_6C8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6CC_OFFSET 0x6cc +#define GC_GPIO_MASKLOWBYTE_6CC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6D0_OFFSET 0x6d0 +#define GC_GPIO_MASKLOWBYTE_6D0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6D4_OFFSET 0x6d4 +#define GC_GPIO_MASKLOWBYTE_6D4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6D8_OFFSET 0x6d8 +#define GC_GPIO_MASKLOWBYTE_6D8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6DC_OFFSET 0x6dc +#define GC_GPIO_MASKLOWBYTE_6DC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6E0_OFFSET 0x6e0 +#define GC_GPIO_MASKLOWBYTE_6E0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6E4_OFFSET 0x6e4 +#define GC_GPIO_MASKLOWBYTE_6E4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6E8_OFFSET 0x6e8 +#define GC_GPIO_MASKLOWBYTE_6E8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6EC_OFFSET 0x6ec +#define GC_GPIO_MASKLOWBYTE_6EC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6F0_OFFSET 0x6f0 +#define GC_GPIO_MASKLOWBYTE_6F0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6F4_OFFSET 0x6f4 +#define GC_GPIO_MASKLOWBYTE_6F4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6F8_OFFSET 0x6f8 +#define GC_GPIO_MASKLOWBYTE_6F8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_6FC_OFFSET 0x6fc +#define GC_GPIO_MASKLOWBYTE_6FC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_700_OFFSET 0x700 +#define GC_GPIO_MASKLOWBYTE_700_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_704_OFFSET 0x704 +#define GC_GPIO_MASKLOWBYTE_704_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_708_OFFSET 0x708 +#define GC_GPIO_MASKLOWBYTE_708_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_70C_OFFSET 0x70c +#define GC_GPIO_MASKLOWBYTE_70C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_710_OFFSET 0x710 +#define GC_GPIO_MASKLOWBYTE_710_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_714_OFFSET 0x714 +#define GC_GPIO_MASKLOWBYTE_714_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_718_OFFSET 0x718 +#define GC_GPIO_MASKLOWBYTE_718_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_71C_OFFSET 0x71c +#define GC_GPIO_MASKLOWBYTE_71C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_720_OFFSET 0x720 +#define GC_GPIO_MASKLOWBYTE_720_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_724_OFFSET 0x724 +#define GC_GPIO_MASKLOWBYTE_724_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_728_OFFSET 0x728 +#define GC_GPIO_MASKLOWBYTE_728_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_72C_OFFSET 0x72c +#define GC_GPIO_MASKLOWBYTE_72C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_730_OFFSET 0x730 +#define GC_GPIO_MASKLOWBYTE_730_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_734_OFFSET 0x734 +#define GC_GPIO_MASKLOWBYTE_734_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_738_OFFSET 0x738 +#define GC_GPIO_MASKLOWBYTE_738_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_73C_OFFSET 0x73c +#define GC_GPIO_MASKLOWBYTE_73C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_740_OFFSET 0x740 +#define GC_GPIO_MASKLOWBYTE_740_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_744_OFFSET 0x744 +#define GC_GPIO_MASKLOWBYTE_744_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_748_OFFSET 0x748 +#define GC_GPIO_MASKLOWBYTE_748_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_74C_OFFSET 0x74c +#define GC_GPIO_MASKLOWBYTE_74C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_750_OFFSET 0x750 +#define GC_GPIO_MASKLOWBYTE_750_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_754_OFFSET 0x754 +#define GC_GPIO_MASKLOWBYTE_754_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_758_OFFSET 0x758 +#define GC_GPIO_MASKLOWBYTE_758_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_75C_OFFSET 0x75c +#define GC_GPIO_MASKLOWBYTE_75C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_760_OFFSET 0x760 +#define GC_GPIO_MASKLOWBYTE_760_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_764_OFFSET 0x764 +#define GC_GPIO_MASKLOWBYTE_764_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_768_OFFSET 0x768 +#define GC_GPIO_MASKLOWBYTE_768_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_76C_OFFSET 0x76c +#define GC_GPIO_MASKLOWBYTE_76C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_770_OFFSET 0x770 +#define GC_GPIO_MASKLOWBYTE_770_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_774_OFFSET 0x774 +#define GC_GPIO_MASKLOWBYTE_774_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_778_OFFSET 0x778 +#define GC_GPIO_MASKLOWBYTE_778_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_77C_OFFSET 0x77c +#define GC_GPIO_MASKLOWBYTE_77C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_780_OFFSET 0x780 +#define GC_GPIO_MASKLOWBYTE_780_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_784_OFFSET 0x784 +#define GC_GPIO_MASKLOWBYTE_784_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_788_OFFSET 0x788 +#define GC_GPIO_MASKLOWBYTE_788_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_78C_OFFSET 0x78c +#define GC_GPIO_MASKLOWBYTE_78C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_790_OFFSET 0x790 +#define GC_GPIO_MASKLOWBYTE_790_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_794_OFFSET 0x794 +#define GC_GPIO_MASKLOWBYTE_794_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_798_OFFSET 0x798 +#define GC_GPIO_MASKLOWBYTE_798_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_79C_OFFSET 0x79c +#define GC_GPIO_MASKLOWBYTE_79C_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7A0_OFFSET 0x7a0 +#define GC_GPIO_MASKLOWBYTE_7A0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7A4_OFFSET 0x7a4 +#define GC_GPIO_MASKLOWBYTE_7A4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7A8_OFFSET 0x7a8 +#define GC_GPIO_MASKLOWBYTE_7A8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7AC_OFFSET 0x7ac +#define GC_GPIO_MASKLOWBYTE_7AC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7B0_OFFSET 0x7b0 +#define GC_GPIO_MASKLOWBYTE_7B0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7B4_OFFSET 0x7b4 +#define GC_GPIO_MASKLOWBYTE_7B4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7B8_OFFSET 0x7b8 +#define GC_GPIO_MASKLOWBYTE_7B8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7BC_OFFSET 0x7bc +#define GC_GPIO_MASKLOWBYTE_7BC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7C0_OFFSET 0x7c0 +#define GC_GPIO_MASKLOWBYTE_7C0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7C4_OFFSET 0x7c4 +#define GC_GPIO_MASKLOWBYTE_7C4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7C8_OFFSET 0x7c8 +#define GC_GPIO_MASKLOWBYTE_7C8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7CC_OFFSET 0x7cc +#define GC_GPIO_MASKLOWBYTE_7CC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7D0_OFFSET 0x7d0 +#define GC_GPIO_MASKLOWBYTE_7D0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7D4_OFFSET 0x7d4 +#define GC_GPIO_MASKLOWBYTE_7D4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7D8_OFFSET 0x7d8 +#define GC_GPIO_MASKLOWBYTE_7D8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7DC_OFFSET 0x7dc +#define GC_GPIO_MASKLOWBYTE_7DC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7E0_OFFSET 0x7e0 +#define GC_GPIO_MASKLOWBYTE_7E0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7E4_OFFSET 0x7e4 +#define GC_GPIO_MASKLOWBYTE_7E4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7E8_OFFSET 0x7e8 +#define GC_GPIO_MASKLOWBYTE_7E8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7EC_OFFSET 0x7ec +#define GC_GPIO_MASKLOWBYTE_7EC_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7F0_OFFSET 0x7f0 +#define GC_GPIO_MASKLOWBYTE_7F0_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7F4_OFFSET 0x7f4 +#define GC_GPIO_MASKLOWBYTE_7F4_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7F8_OFFSET 0x7f8 +#define GC_GPIO_MASKLOWBYTE_7F8_DEFAULT 0x0 +#define GC_GPIO_MASKLOWBYTE_7FC_OFFSET 0x7fc +#define GC_GPIO_MASKLOWBYTE_7FC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_800_OFFSET 0x800 +#define GC_GPIO_MASKHIGHBYTE_800_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_804_OFFSET 0x804 +#define GC_GPIO_MASKHIGHBYTE_804_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_808_OFFSET 0x808 +#define GC_GPIO_MASKHIGHBYTE_808_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_80C_OFFSET 0x80c +#define GC_GPIO_MASKHIGHBYTE_80C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_810_OFFSET 0x810 +#define GC_GPIO_MASKHIGHBYTE_810_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_814_OFFSET 0x814 +#define GC_GPIO_MASKHIGHBYTE_814_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_818_OFFSET 0x818 +#define GC_GPIO_MASKHIGHBYTE_818_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_81C_OFFSET 0x81c +#define GC_GPIO_MASKHIGHBYTE_81C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_820_OFFSET 0x820 +#define GC_GPIO_MASKHIGHBYTE_820_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_824_OFFSET 0x824 +#define GC_GPIO_MASKHIGHBYTE_824_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_828_OFFSET 0x828 +#define GC_GPIO_MASKHIGHBYTE_828_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_82C_OFFSET 0x82c +#define GC_GPIO_MASKHIGHBYTE_82C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_830_OFFSET 0x830 +#define GC_GPIO_MASKHIGHBYTE_830_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_834_OFFSET 0x834 +#define GC_GPIO_MASKHIGHBYTE_834_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_838_OFFSET 0x838 +#define GC_GPIO_MASKHIGHBYTE_838_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_83C_OFFSET 0x83c +#define GC_GPIO_MASKHIGHBYTE_83C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_840_OFFSET 0x840 +#define GC_GPIO_MASKHIGHBYTE_840_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_844_OFFSET 0x844 +#define GC_GPIO_MASKHIGHBYTE_844_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_848_OFFSET 0x848 +#define GC_GPIO_MASKHIGHBYTE_848_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_84C_OFFSET 0x84c +#define GC_GPIO_MASKHIGHBYTE_84C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_850_OFFSET 0x850 +#define GC_GPIO_MASKHIGHBYTE_850_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_854_OFFSET 0x854 +#define GC_GPIO_MASKHIGHBYTE_854_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_858_OFFSET 0x858 +#define GC_GPIO_MASKHIGHBYTE_858_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_85C_OFFSET 0x85c +#define GC_GPIO_MASKHIGHBYTE_85C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_860_OFFSET 0x860 +#define GC_GPIO_MASKHIGHBYTE_860_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_864_OFFSET 0x864 +#define GC_GPIO_MASKHIGHBYTE_864_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_868_OFFSET 0x868 +#define GC_GPIO_MASKHIGHBYTE_868_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_86C_OFFSET 0x86c +#define GC_GPIO_MASKHIGHBYTE_86C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_870_OFFSET 0x870 +#define GC_GPIO_MASKHIGHBYTE_870_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_874_OFFSET 0x874 +#define GC_GPIO_MASKHIGHBYTE_874_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_878_OFFSET 0x878 +#define GC_GPIO_MASKHIGHBYTE_878_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_87C_OFFSET 0x87c +#define GC_GPIO_MASKHIGHBYTE_87C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_880_OFFSET 0x880 +#define GC_GPIO_MASKHIGHBYTE_880_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_884_OFFSET 0x884 +#define GC_GPIO_MASKHIGHBYTE_884_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_888_OFFSET 0x888 +#define GC_GPIO_MASKHIGHBYTE_888_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_88C_OFFSET 0x88c +#define GC_GPIO_MASKHIGHBYTE_88C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_890_OFFSET 0x890 +#define GC_GPIO_MASKHIGHBYTE_890_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_894_OFFSET 0x894 +#define GC_GPIO_MASKHIGHBYTE_894_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_898_OFFSET 0x898 +#define GC_GPIO_MASKHIGHBYTE_898_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_89C_OFFSET 0x89c +#define GC_GPIO_MASKHIGHBYTE_89C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8A0_OFFSET 0x8a0 +#define GC_GPIO_MASKHIGHBYTE_8A0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8A4_OFFSET 0x8a4 +#define GC_GPIO_MASKHIGHBYTE_8A4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8A8_OFFSET 0x8a8 +#define GC_GPIO_MASKHIGHBYTE_8A8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8AC_OFFSET 0x8ac +#define GC_GPIO_MASKHIGHBYTE_8AC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8B0_OFFSET 0x8b0 +#define GC_GPIO_MASKHIGHBYTE_8B0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8B4_OFFSET 0x8b4 +#define GC_GPIO_MASKHIGHBYTE_8B4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8B8_OFFSET 0x8b8 +#define GC_GPIO_MASKHIGHBYTE_8B8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8BC_OFFSET 0x8bc +#define GC_GPIO_MASKHIGHBYTE_8BC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8C0_OFFSET 0x8c0 +#define GC_GPIO_MASKHIGHBYTE_8C0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8C4_OFFSET 0x8c4 +#define GC_GPIO_MASKHIGHBYTE_8C4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8C8_OFFSET 0x8c8 +#define GC_GPIO_MASKHIGHBYTE_8C8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8CC_OFFSET 0x8cc +#define GC_GPIO_MASKHIGHBYTE_8CC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8D0_OFFSET 0x8d0 +#define GC_GPIO_MASKHIGHBYTE_8D0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8D4_OFFSET 0x8d4 +#define GC_GPIO_MASKHIGHBYTE_8D4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8D8_OFFSET 0x8d8 +#define GC_GPIO_MASKHIGHBYTE_8D8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8DC_OFFSET 0x8dc +#define GC_GPIO_MASKHIGHBYTE_8DC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8E0_OFFSET 0x8e0 +#define GC_GPIO_MASKHIGHBYTE_8E0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8E4_OFFSET 0x8e4 +#define GC_GPIO_MASKHIGHBYTE_8E4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8E8_OFFSET 0x8e8 +#define GC_GPIO_MASKHIGHBYTE_8E8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8EC_OFFSET 0x8ec +#define GC_GPIO_MASKHIGHBYTE_8EC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8F0_OFFSET 0x8f0 +#define GC_GPIO_MASKHIGHBYTE_8F0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8F4_OFFSET 0x8f4 +#define GC_GPIO_MASKHIGHBYTE_8F4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8F8_OFFSET 0x8f8 +#define GC_GPIO_MASKHIGHBYTE_8F8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_8FC_OFFSET 0x8fc +#define GC_GPIO_MASKHIGHBYTE_8FC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_900_OFFSET 0x900 +#define GC_GPIO_MASKHIGHBYTE_900_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_904_OFFSET 0x904 +#define GC_GPIO_MASKHIGHBYTE_904_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_908_OFFSET 0x908 +#define GC_GPIO_MASKHIGHBYTE_908_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_90C_OFFSET 0x90c +#define GC_GPIO_MASKHIGHBYTE_90C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_910_OFFSET 0x910 +#define GC_GPIO_MASKHIGHBYTE_910_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_914_OFFSET 0x914 +#define GC_GPIO_MASKHIGHBYTE_914_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_918_OFFSET 0x918 +#define GC_GPIO_MASKHIGHBYTE_918_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_91C_OFFSET 0x91c +#define GC_GPIO_MASKHIGHBYTE_91C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_920_OFFSET 0x920 +#define GC_GPIO_MASKHIGHBYTE_920_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_924_OFFSET 0x924 +#define GC_GPIO_MASKHIGHBYTE_924_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_928_OFFSET 0x928 +#define GC_GPIO_MASKHIGHBYTE_928_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_92C_OFFSET 0x92c +#define GC_GPIO_MASKHIGHBYTE_92C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_930_OFFSET 0x930 +#define GC_GPIO_MASKHIGHBYTE_930_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_934_OFFSET 0x934 +#define GC_GPIO_MASKHIGHBYTE_934_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_938_OFFSET 0x938 +#define GC_GPIO_MASKHIGHBYTE_938_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_93C_OFFSET 0x93c +#define GC_GPIO_MASKHIGHBYTE_93C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_940_OFFSET 0x940 +#define GC_GPIO_MASKHIGHBYTE_940_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_944_OFFSET 0x944 +#define GC_GPIO_MASKHIGHBYTE_944_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_948_OFFSET 0x948 +#define GC_GPIO_MASKHIGHBYTE_948_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_94C_OFFSET 0x94c +#define GC_GPIO_MASKHIGHBYTE_94C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_950_OFFSET 0x950 +#define GC_GPIO_MASKHIGHBYTE_950_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_954_OFFSET 0x954 +#define GC_GPIO_MASKHIGHBYTE_954_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_958_OFFSET 0x958 +#define GC_GPIO_MASKHIGHBYTE_958_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_95C_OFFSET 0x95c +#define GC_GPIO_MASKHIGHBYTE_95C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_960_OFFSET 0x960 +#define GC_GPIO_MASKHIGHBYTE_960_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_964_OFFSET 0x964 +#define GC_GPIO_MASKHIGHBYTE_964_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_968_OFFSET 0x968 +#define GC_GPIO_MASKHIGHBYTE_968_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_96C_OFFSET 0x96c +#define GC_GPIO_MASKHIGHBYTE_96C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_970_OFFSET 0x970 +#define GC_GPIO_MASKHIGHBYTE_970_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_974_OFFSET 0x974 +#define GC_GPIO_MASKHIGHBYTE_974_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_978_OFFSET 0x978 +#define GC_GPIO_MASKHIGHBYTE_978_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_97C_OFFSET 0x97c +#define GC_GPIO_MASKHIGHBYTE_97C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_980_OFFSET 0x980 +#define GC_GPIO_MASKHIGHBYTE_980_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_984_OFFSET 0x984 +#define GC_GPIO_MASKHIGHBYTE_984_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_988_OFFSET 0x988 +#define GC_GPIO_MASKHIGHBYTE_988_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_98C_OFFSET 0x98c +#define GC_GPIO_MASKHIGHBYTE_98C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_990_OFFSET 0x990 +#define GC_GPIO_MASKHIGHBYTE_990_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_994_OFFSET 0x994 +#define GC_GPIO_MASKHIGHBYTE_994_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_998_OFFSET 0x998 +#define GC_GPIO_MASKHIGHBYTE_998_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_99C_OFFSET 0x99c +#define GC_GPIO_MASKHIGHBYTE_99C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9A0_OFFSET 0x9a0 +#define GC_GPIO_MASKHIGHBYTE_9A0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9A4_OFFSET 0x9a4 +#define GC_GPIO_MASKHIGHBYTE_9A4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9A8_OFFSET 0x9a8 +#define GC_GPIO_MASKHIGHBYTE_9A8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9AC_OFFSET 0x9ac +#define GC_GPIO_MASKHIGHBYTE_9AC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9B0_OFFSET 0x9b0 +#define GC_GPIO_MASKHIGHBYTE_9B0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9B4_OFFSET 0x9b4 +#define GC_GPIO_MASKHIGHBYTE_9B4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9B8_OFFSET 0x9b8 +#define GC_GPIO_MASKHIGHBYTE_9B8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9BC_OFFSET 0x9bc +#define GC_GPIO_MASKHIGHBYTE_9BC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9C0_OFFSET 0x9c0 +#define GC_GPIO_MASKHIGHBYTE_9C0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9C4_OFFSET 0x9c4 +#define GC_GPIO_MASKHIGHBYTE_9C4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9C8_OFFSET 0x9c8 +#define GC_GPIO_MASKHIGHBYTE_9C8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9CC_OFFSET 0x9cc +#define GC_GPIO_MASKHIGHBYTE_9CC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9D0_OFFSET 0x9d0 +#define GC_GPIO_MASKHIGHBYTE_9D0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9D4_OFFSET 0x9d4 +#define GC_GPIO_MASKHIGHBYTE_9D4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9D8_OFFSET 0x9d8 +#define GC_GPIO_MASKHIGHBYTE_9D8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9DC_OFFSET 0x9dc +#define GC_GPIO_MASKHIGHBYTE_9DC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9E0_OFFSET 0x9e0 +#define GC_GPIO_MASKHIGHBYTE_9E0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9E4_OFFSET 0x9e4 +#define GC_GPIO_MASKHIGHBYTE_9E4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9E8_OFFSET 0x9e8 +#define GC_GPIO_MASKHIGHBYTE_9E8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9EC_OFFSET 0x9ec +#define GC_GPIO_MASKHIGHBYTE_9EC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9F0_OFFSET 0x9f0 +#define GC_GPIO_MASKHIGHBYTE_9F0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9F4_OFFSET 0x9f4 +#define GC_GPIO_MASKHIGHBYTE_9F4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9F8_OFFSET 0x9f8 +#define GC_GPIO_MASKHIGHBYTE_9F8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_9FC_OFFSET 0x9fc +#define GC_GPIO_MASKHIGHBYTE_9FC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A00_OFFSET 0xa00 +#define GC_GPIO_MASKHIGHBYTE_A00_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A04_OFFSET 0xa04 +#define GC_GPIO_MASKHIGHBYTE_A04_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A08_OFFSET 0xa08 +#define GC_GPIO_MASKHIGHBYTE_A08_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A0C_OFFSET 0xa0c +#define GC_GPIO_MASKHIGHBYTE_A0C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A10_OFFSET 0xa10 +#define GC_GPIO_MASKHIGHBYTE_A10_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A14_OFFSET 0xa14 +#define GC_GPIO_MASKHIGHBYTE_A14_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A18_OFFSET 0xa18 +#define GC_GPIO_MASKHIGHBYTE_A18_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A1C_OFFSET 0xa1c +#define GC_GPIO_MASKHIGHBYTE_A1C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A20_OFFSET 0xa20 +#define GC_GPIO_MASKHIGHBYTE_A20_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A24_OFFSET 0xa24 +#define GC_GPIO_MASKHIGHBYTE_A24_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A28_OFFSET 0xa28 +#define GC_GPIO_MASKHIGHBYTE_A28_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A2C_OFFSET 0xa2c +#define GC_GPIO_MASKHIGHBYTE_A2C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A30_OFFSET 0xa30 +#define GC_GPIO_MASKHIGHBYTE_A30_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A34_OFFSET 0xa34 +#define GC_GPIO_MASKHIGHBYTE_A34_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A38_OFFSET 0xa38 +#define GC_GPIO_MASKHIGHBYTE_A38_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A3C_OFFSET 0xa3c +#define GC_GPIO_MASKHIGHBYTE_A3C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A40_OFFSET 0xa40 +#define GC_GPIO_MASKHIGHBYTE_A40_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A44_OFFSET 0xa44 +#define GC_GPIO_MASKHIGHBYTE_A44_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A48_OFFSET 0xa48 +#define GC_GPIO_MASKHIGHBYTE_A48_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A4C_OFFSET 0xa4c +#define GC_GPIO_MASKHIGHBYTE_A4C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A50_OFFSET 0xa50 +#define GC_GPIO_MASKHIGHBYTE_A50_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A54_OFFSET 0xa54 +#define GC_GPIO_MASKHIGHBYTE_A54_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A58_OFFSET 0xa58 +#define GC_GPIO_MASKHIGHBYTE_A58_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A5C_OFFSET 0xa5c +#define GC_GPIO_MASKHIGHBYTE_A5C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A60_OFFSET 0xa60 +#define GC_GPIO_MASKHIGHBYTE_A60_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A64_OFFSET 0xa64 +#define GC_GPIO_MASKHIGHBYTE_A64_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A68_OFFSET 0xa68 +#define GC_GPIO_MASKHIGHBYTE_A68_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A6C_OFFSET 0xa6c +#define GC_GPIO_MASKHIGHBYTE_A6C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A70_OFFSET 0xa70 +#define GC_GPIO_MASKHIGHBYTE_A70_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A74_OFFSET 0xa74 +#define GC_GPIO_MASKHIGHBYTE_A74_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A78_OFFSET 0xa78 +#define GC_GPIO_MASKHIGHBYTE_A78_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A7C_OFFSET 0xa7c +#define GC_GPIO_MASKHIGHBYTE_A7C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A80_OFFSET 0xa80 +#define GC_GPIO_MASKHIGHBYTE_A80_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A84_OFFSET 0xa84 +#define GC_GPIO_MASKHIGHBYTE_A84_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A88_OFFSET 0xa88 +#define GC_GPIO_MASKHIGHBYTE_A88_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A8C_OFFSET 0xa8c +#define GC_GPIO_MASKHIGHBYTE_A8C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A90_OFFSET 0xa90 +#define GC_GPIO_MASKHIGHBYTE_A90_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A94_OFFSET 0xa94 +#define GC_GPIO_MASKHIGHBYTE_A94_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A98_OFFSET 0xa98 +#define GC_GPIO_MASKHIGHBYTE_A98_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_A9C_OFFSET 0xa9c +#define GC_GPIO_MASKHIGHBYTE_A9C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AA0_OFFSET 0xaa0 +#define GC_GPIO_MASKHIGHBYTE_AA0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AA4_OFFSET 0xaa4 +#define GC_GPIO_MASKHIGHBYTE_AA4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AA8_OFFSET 0xaa8 +#define GC_GPIO_MASKHIGHBYTE_AA8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AAC_OFFSET 0xaac +#define GC_GPIO_MASKHIGHBYTE_AAC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AB0_OFFSET 0xab0 +#define GC_GPIO_MASKHIGHBYTE_AB0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AB4_OFFSET 0xab4 +#define GC_GPIO_MASKHIGHBYTE_AB4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AB8_OFFSET 0xab8 +#define GC_GPIO_MASKHIGHBYTE_AB8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_ABC_OFFSET 0xabc +#define GC_GPIO_MASKHIGHBYTE_ABC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AC0_OFFSET 0xac0 +#define GC_GPIO_MASKHIGHBYTE_AC0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AC4_OFFSET 0xac4 +#define GC_GPIO_MASKHIGHBYTE_AC4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AC8_OFFSET 0xac8 +#define GC_GPIO_MASKHIGHBYTE_AC8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_ACC_OFFSET 0xacc +#define GC_GPIO_MASKHIGHBYTE_ACC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AD0_OFFSET 0xad0 +#define GC_GPIO_MASKHIGHBYTE_AD0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AD4_OFFSET 0xad4 +#define GC_GPIO_MASKHIGHBYTE_AD4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AD8_OFFSET 0xad8 +#define GC_GPIO_MASKHIGHBYTE_AD8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_ADC_OFFSET 0xadc +#define GC_GPIO_MASKHIGHBYTE_ADC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AE0_OFFSET 0xae0 +#define GC_GPIO_MASKHIGHBYTE_AE0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AE4_OFFSET 0xae4 +#define GC_GPIO_MASKHIGHBYTE_AE4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AE8_OFFSET 0xae8 +#define GC_GPIO_MASKHIGHBYTE_AE8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AEC_OFFSET 0xaec +#define GC_GPIO_MASKHIGHBYTE_AEC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AF0_OFFSET 0xaf0 +#define GC_GPIO_MASKHIGHBYTE_AF0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AF4_OFFSET 0xaf4 +#define GC_GPIO_MASKHIGHBYTE_AF4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AF8_OFFSET 0xaf8 +#define GC_GPIO_MASKHIGHBYTE_AF8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_AFC_OFFSET 0xafc +#define GC_GPIO_MASKHIGHBYTE_AFC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B00_OFFSET 0xb00 +#define GC_GPIO_MASKHIGHBYTE_B00_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B04_OFFSET 0xb04 +#define GC_GPIO_MASKHIGHBYTE_B04_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B08_OFFSET 0xb08 +#define GC_GPIO_MASKHIGHBYTE_B08_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B0C_OFFSET 0xb0c +#define GC_GPIO_MASKHIGHBYTE_B0C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B10_OFFSET 0xb10 +#define GC_GPIO_MASKHIGHBYTE_B10_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B14_OFFSET 0xb14 +#define GC_GPIO_MASKHIGHBYTE_B14_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B18_OFFSET 0xb18 +#define GC_GPIO_MASKHIGHBYTE_B18_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B1C_OFFSET 0xb1c +#define GC_GPIO_MASKHIGHBYTE_B1C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B20_OFFSET 0xb20 +#define GC_GPIO_MASKHIGHBYTE_B20_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B24_OFFSET 0xb24 +#define GC_GPIO_MASKHIGHBYTE_B24_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B28_OFFSET 0xb28 +#define GC_GPIO_MASKHIGHBYTE_B28_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B2C_OFFSET 0xb2c +#define GC_GPIO_MASKHIGHBYTE_B2C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B30_OFFSET 0xb30 +#define GC_GPIO_MASKHIGHBYTE_B30_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B34_OFFSET 0xb34 +#define GC_GPIO_MASKHIGHBYTE_B34_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B38_OFFSET 0xb38 +#define GC_GPIO_MASKHIGHBYTE_B38_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B3C_OFFSET 0xb3c +#define GC_GPIO_MASKHIGHBYTE_B3C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B40_OFFSET 0xb40 +#define GC_GPIO_MASKHIGHBYTE_B40_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B44_OFFSET 0xb44 +#define GC_GPIO_MASKHIGHBYTE_B44_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B48_OFFSET 0xb48 +#define GC_GPIO_MASKHIGHBYTE_B48_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B4C_OFFSET 0xb4c +#define GC_GPIO_MASKHIGHBYTE_B4C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B50_OFFSET 0xb50 +#define GC_GPIO_MASKHIGHBYTE_B50_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B54_OFFSET 0xb54 +#define GC_GPIO_MASKHIGHBYTE_B54_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B58_OFFSET 0xb58 +#define GC_GPIO_MASKHIGHBYTE_B58_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B5C_OFFSET 0xb5c +#define GC_GPIO_MASKHIGHBYTE_B5C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B60_OFFSET 0xb60 +#define GC_GPIO_MASKHIGHBYTE_B60_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B64_OFFSET 0xb64 +#define GC_GPIO_MASKHIGHBYTE_B64_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B68_OFFSET 0xb68 +#define GC_GPIO_MASKHIGHBYTE_B68_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B6C_OFFSET 0xb6c +#define GC_GPIO_MASKHIGHBYTE_B6C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B70_OFFSET 0xb70 +#define GC_GPIO_MASKHIGHBYTE_B70_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B74_OFFSET 0xb74 +#define GC_GPIO_MASKHIGHBYTE_B74_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B78_OFFSET 0xb78 +#define GC_GPIO_MASKHIGHBYTE_B78_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B7C_OFFSET 0xb7c +#define GC_GPIO_MASKHIGHBYTE_B7C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B80_OFFSET 0xb80 +#define GC_GPIO_MASKHIGHBYTE_B80_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B84_OFFSET 0xb84 +#define GC_GPIO_MASKHIGHBYTE_B84_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B88_OFFSET 0xb88 +#define GC_GPIO_MASKHIGHBYTE_B88_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B8C_OFFSET 0xb8c +#define GC_GPIO_MASKHIGHBYTE_B8C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B90_OFFSET 0xb90 +#define GC_GPIO_MASKHIGHBYTE_B90_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B94_OFFSET 0xb94 +#define GC_GPIO_MASKHIGHBYTE_B94_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B98_OFFSET 0xb98 +#define GC_GPIO_MASKHIGHBYTE_B98_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_B9C_OFFSET 0xb9c +#define GC_GPIO_MASKHIGHBYTE_B9C_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BA0_OFFSET 0xba0 +#define GC_GPIO_MASKHIGHBYTE_BA0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BA4_OFFSET 0xba4 +#define GC_GPIO_MASKHIGHBYTE_BA4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BA8_OFFSET 0xba8 +#define GC_GPIO_MASKHIGHBYTE_BA8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BAC_OFFSET 0xbac +#define GC_GPIO_MASKHIGHBYTE_BAC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BB0_OFFSET 0xbb0 +#define GC_GPIO_MASKHIGHBYTE_BB0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BB4_OFFSET 0xbb4 +#define GC_GPIO_MASKHIGHBYTE_BB4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BB8_OFFSET 0xbb8 +#define GC_GPIO_MASKHIGHBYTE_BB8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BBC_OFFSET 0xbbc +#define GC_GPIO_MASKHIGHBYTE_BBC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BC0_OFFSET 0xbc0 +#define GC_GPIO_MASKHIGHBYTE_BC0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BC4_OFFSET 0xbc4 +#define GC_GPIO_MASKHIGHBYTE_BC4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BC8_OFFSET 0xbc8 +#define GC_GPIO_MASKHIGHBYTE_BC8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BCC_OFFSET 0xbcc +#define GC_GPIO_MASKHIGHBYTE_BCC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BD0_OFFSET 0xbd0 +#define GC_GPIO_MASKHIGHBYTE_BD0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BD4_OFFSET 0xbd4 +#define GC_GPIO_MASKHIGHBYTE_BD4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BD8_OFFSET 0xbd8 +#define GC_GPIO_MASKHIGHBYTE_BD8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BDC_OFFSET 0xbdc +#define GC_GPIO_MASKHIGHBYTE_BDC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BE0_OFFSET 0xbe0 +#define GC_GPIO_MASKHIGHBYTE_BE0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BE4_OFFSET 0xbe4 +#define GC_GPIO_MASKHIGHBYTE_BE4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BE8_OFFSET 0xbe8 +#define GC_GPIO_MASKHIGHBYTE_BE8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BEC_OFFSET 0xbec +#define GC_GPIO_MASKHIGHBYTE_BEC_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BF0_OFFSET 0xbf0 +#define GC_GPIO_MASKHIGHBYTE_BF0_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BF4_OFFSET 0xbf4 +#define GC_GPIO_MASKHIGHBYTE_BF4_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BF8_OFFSET 0xbf8 +#define GC_GPIO_MASKHIGHBYTE_BF8_DEFAULT 0x0 +#define GC_GPIO_MASKHIGHBYTE_BFC_OFFSET 0xbfc +#define GC_GPIO_MASKHIGHBYTE_BFC_DEFAULT 0x0 +#define GC_GPIO_ARMPID4_OFFSET 0xfd0 +#define GC_GPIO_ARMPID4_DEFAULT 0x4 +#define GC_GPIO_ARMPID5_OFFSET 0xfd4 +#define GC_GPIO_ARMPID5_DEFAULT 0x0 +#define GC_GPIO_ARMPID6_OFFSET 0xfd8 +#define GC_GPIO_ARMPID6_DEFAULT 0x0 +#define GC_GPIO_ARMPID7_OFFSET 0xfdc +#define GC_GPIO_ARMPID7_DEFAULT 0x0 +#define GC_GPIO_ARMPID0_OFFSET 0xfe0 +#define GC_GPIO_ARMPID0_DEFAULT 0x20 +#define GC_GPIO_ARMPID1_OFFSET 0xfe4 +#define GC_GPIO_ARMPID1_DEFAULT 0xb8 +#define GC_GPIO_ARMPID2_OFFSET 0xfe8 +#define GC_GPIO_ARMPID2_DEFAULT 0xb +#define GC_GPIO_ARMPID3_OFFSET 0xfec +#define GC_GPIO_ARMPID3_DEFAULT 0x0 +#define GC_GPIO_ARMCID0_OFFSET 0xff0 +#define GC_GPIO_ARMCID0_DEFAULT 0xd +#define GC_GPIO_ARMCID1_OFFSET 0xff4 +#define GC_GPIO_ARMCID1_DEFAULT 0xf0 +#define GC_GPIO_ARMCID2_OFFSET 0xff8 +#define GC_GPIO_ARMCID2_DEFAULT 0x5 +#define GC_GPIO_ARMCID3_OFFSET 0xffc +#define GC_GPIO_ARMCID3_DEFAULT 0xb1 +#define GC_I2C_CTRL_MODE_OFFSET 0x0 +#define GC_I2C_CTRL_MODE_DEFAULT 0x0 +#define GC_I2C_CTRL_CLKDIV_OFFSET 0x4 +#define GC_I2C_CTRL_CLKDIV_DEFAULT 0xa +#define GC_I2C_CTRL_PHASESTEPS_OFFSET 0x8 +#define GC_I2C_CTRL_PHASESTEPS_DEFAULT 0x188186 +#define GC_I2C_CTRL_SDA_VAL_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_DEFAULT 0x1897f0f +#define GC_I2C_CTRL_SDA_OVRD_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_DEFAULT 0x300 +#define GC_I2C_CTRL_SCL_VAL_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_DEFAULT 0x67666e +#define GC_I2C_CTRL_SCL_OVRD_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_DEFAULT 0x600 +#define GC_I2C_CTRL_INT_EN_OFFSET 0x1c +#define GC_I2C_CTRL_INT_EN_DEFAULT 0x1 +#define GC_I2C_CTRL_AL_OFFSET 0x20 +#define GC_I2C_CTRL_AL_DEFAULT 0x1f +#define GC_I2C_CTRL_CS_OFFSET 0x24 +#define GC_I2C_CTRL_CS_DEFAULT 0x13883 +#define GC_I2C_INST_OFFSET 0x28 +#define GC_I2C_INST_DEFAULT 0x0 +#define GC_I2C_STATUS_OFFSET 0x2c +#define GC_I2C_STATUS_DEFAULT 0x0 +#define GC_I2C_FW_OFFSET 0x30 +#define GC_I2C_FW_DEFAULT 0x0 +#define GC_I2C_RW_PTR_OFFSET 0x34 +#define GC_I2C_RW_PTR_DEFAULT 0x0 +#define GC_I2C_RW0_OFFSET 0x38 +#define GC_I2C_RW0_DEFAULT 0x0 +#define GC_I2C_RW1_OFFSET 0x3c +#define GC_I2C_RW1_DEFAULT 0x0 +#define GC_I2C_RW2_OFFSET 0x40 +#define GC_I2C_RW2_DEFAULT 0x0 +#define GC_I2C_RW3_OFFSET 0x44 +#define GC_I2C_RW3_DEFAULT 0x0 +#define GC_I2C_RW4_OFFSET 0x48 +#define GC_I2C_RW4_DEFAULT 0x0 +#define GC_I2C_RW5_OFFSET 0x4c +#define GC_I2C_RW5_DEFAULT 0x0 +#define GC_I2C_RW6_OFFSET 0x50 +#define GC_I2C_RW6_DEFAULT 0x0 +#define GC_I2C_RW7_OFFSET 0x54 +#define GC_I2C_RW7_DEFAULT 0x0 +#define GC_I2C_RW8_OFFSET 0x58 +#define GC_I2C_RW8_DEFAULT 0x0 +#define GC_I2C_RW9_OFFSET 0x5c +#define GC_I2C_RW9_DEFAULT 0x0 +#define GC_I2C_RW10_OFFSET 0x60 +#define GC_I2C_RW10_DEFAULT 0x0 +#define GC_I2C_RW11_OFFSET 0x64 +#define GC_I2C_RW11_DEFAULT 0x0 +#define GC_I2C_RW12_OFFSET 0x68 +#define GC_I2C_RW12_DEFAULT 0x0 +#define GC_I2C_RW13_OFFSET 0x6c +#define GC_I2C_RW13_DEFAULT 0x0 +#define GC_I2C_RW14_OFFSET 0x70 +#define GC_I2C_RW14_DEFAULT 0x0 +#define GC_I2C_RW15_OFFSET 0x74 +#define GC_I2C_RW15_DEFAULT 0x0 +#define GC_I2C_READVAL_OFFSET 0x78 +#define GC_I2C_READVAL_DEFAULT 0x0 +#define GC_I2C_CTRL_MSR_OFFSET 0x7c +#define GC_I2C_CTRL_MSR_DEFAULT 0xa +#define GC_I2C_ITCR_OFFSET 0xf00 +#define GC_I2C_ITCR_DEFAULT 0x0 +#define GC_I2C_ITOP_OFFSET 0xf04 +#define GC_I2C_ITOP_DEFAULT 0x0 +#define GC_I2CS_VERSION_OFFSET 0x0 +#define GC_I2CS_VERSION_DEFAULT 0x400b99f +#define GC_I2CS_INT_ENABLE_OFFSET 0x4 +#define GC_I2CS_INT_ENABLE_DEFAULT 0x0 +#define GC_I2CS_INT_STATE_OFFSET 0x8 +#define GC_I2CS_INT_STATE_DEFAULT 0x0 +#define GC_I2CS_INT_TEST_OFFSET 0xc +#define GC_I2CS_INT_TEST_DEFAULT 0x0 +#define GC_I2CS_CTRL_SDA_VAL_OFFSET 0x10 +#define GC_I2CS_CTRL_SDA_VAL_DEFAULT 0x3d +#define GC_I2CS_SLAVE_DEVADDRVAL_OFFSET 0x14 +#define GC_I2CS_SLAVE_DEVADDRVAL_DEFAULT 0x0 +#define GC_I2CS_READ_PTR_OFFSET 0x18 +#define GC_I2CS_READ_PTR_DEFAULT 0x0 +#define GC_I2CS_WRITE_PTR_OFFSET 0x1c +#define GC_I2CS_WRITE_PTR_DEFAULT 0x0 +#define GC_I2CS_READVAL_OFFSET 0x20 +#define GC_I2CS_READVAL_DEFAULT 0x0 +#define GC_I2CS_CTRL_MSR_OFFSET 0x24 +#define GC_I2CS_CTRL_MSR_DEFAULT 0xa +#define GC_I2CS_READ_BUFFER0_OFFSET 0x28 +#define GC_I2CS_READ_BUFFER0_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER1_OFFSET 0x2c +#define GC_I2CS_READ_BUFFER1_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER2_OFFSET 0x30 +#define GC_I2CS_READ_BUFFER2_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER3_OFFSET 0x34 +#define GC_I2CS_READ_BUFFER3_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER4_OFFSET 0x38 +#define GC_I2CS_READ_BUFFER4_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER5_OFFSET 0x3c +#define GC_I2CS_READ_BUFFER5_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER6_OFFSET 0x40 +#define GC_I2CS_READ_BUFFER6_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER7_OFFSET 0x44 +#define GC_I2CS_READ_BUFFER7_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER8_OFFSET 0x48 +#define GC_I2CS_READ_BUFFER8_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER9_OFFSET 0x4c +#define GC_I2CS_READ_BUFFER9_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER10_OFFSET 0x50 +#define GC_I2CS_READ_BUFFER10_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER11_OFFSET 0x54 +#define GC_I2CS_READ_BUFFER11_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER12_OFFSET 0x58 +#define GC_I2CS_READ_BUFFER12_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER13_OFFSET 0x5c +#define GC_I2CS_READ_BUFFER13_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER14_OFFSET 0x60 +#define GC_I2CS_READ_BUFFER14_DEFAULT 0x0 +#define GC_I2CS_READ_BUFFER15_OFFSET 0x64 +#define GC_I2CS_READ_BUFFER15_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER0_OFFSET 0x68 +#define GC_I2CS_WRITE_BUFFER0_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER1_OFFSET 0x6c +#define GC_I2CS_WRITE_BUFFER1_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER2_OFFSET 0x70 +#define GC_I2CS_WRITE_BUFFER2_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER3_OFFSET 0x74 +#define GC_I2CS_WRITE_BUFFER3_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER4_OFFSET 0x78 +#define GC_I2CS_WRITE_BUFFER4_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER5_OFFSET 0x7c +#define GC_I2CS_WRITE_BUFFER5_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER6_OFFSET 0x80 +#define GC_I2CS_WRITE_BUFFER6_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER7_OFFSET 0x84 +#define GC_I2CS_WRITE_BUFFER7_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER8_OFFSET 0x88 +#define GC_I2CS_WRITE_BUFFER8_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER9_OFFSET 0x8c +#define GC_I2CS_WRITE_BUFFER9_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER10_OFFSET 0x90 +#define GC_I2CS_WRITE_BUFFER10_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER11_OFFSET 0x94 +#define GC_I2CS_WRITE_BUFFER11_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER12_OFFSET 0x98 +#define GC_I2CS_WRITE_BUFFER12_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER13_OFFSET 0x9c +#define GC_I2CS_WRITE_BUFFER13_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER14_OFFSET 0xa0 +#define GC_I2CS_WRITE_BUFFER14_DEFAULT 0x0 +#define GC_I2CS_WRITE_BUFFER15_OFFSET 0xa4 +#define GC_I2CS_WRITE_BUFFER15_DEFAULT 0x0 +#define GC_MAU_EN_OFFSET 0x0 +#define GC_MAU_EN_DEFAULT 0x3 +#define GC_MAU_TRACECLR_OFFSET 0x4 +#define GC_MAU_TRACECLR_DEFAULT 0x3 +#define GC_MAU_TRACEIDX_OFFSET 0x8 +#define GC_MAU_TRACEIDX_DEFAULT 0x3 +#define GC_MAU_TRACE_SYSIBUS_OFFSET 0xc +#define GC_MAU_TRACE_SYSIBUS_DEFAULT 0x0 +#define GC_MAU_TRACE_SYSDBUS_OFFSET 0x10 +#define GC_MAU_TRACE_SYSDBUS_DEFAULT 0x0 +#define GC_PAU_EN_OFFSET 0x0 +#define GC_PAU_EN_DEFAULT 0x1 +#define GC_PAU_TRACECLR_OFFSET 0x4 +#define GC_PAU_TRACECLR_DEFAULT 0x1 +#define GC_PAU_TRACEIDX_OFFSET 0x8 +#define GC_PAU_TRACEIDX_DEFAULT 0x1 +#define GC_PAU_TRACE_SYSSBUS_OFFSET 0xc +#define GC_PAU_TRACE_SYSSBUS_DEFAULT 0x0 +#define GC_PINMUX_DIOM0_SEL_OFFSET 0x0 +#define GC_PINMUX_DIOM0_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOM0_CTL_OFFSET 0x4 +#define GC_PINMUX_DIOM0_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOM1_SEL_OFFSET 0x8 +#define GC_PINMUX_DIOM1_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOM1_CTL_OFFSET 0xc +#define GC_PINMUX_DIOM1_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOM2_SEL_OFFSET 0x10 +#define GC_PINMUX_DIOM2_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOM2_CTL_OFFSET 0x14 +#define GC_PINMUX_DIOM2_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOM3_SEL_OFFSET 0x18 +#define GC_PINMUX_DIOM3_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOM3_CTL_OFFSET 0x1c +#define GC_PINMUX_DIOM3_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOM4_SEL_OFFSET 0x20 +#define GC_PINMUX_DIOM4_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOM4_CTL_OFFSET 0x24 +#define GC_PINMUX_DIOM4_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA0_SEL_OFFSET 0x28 +#define GC_PINMUX_DIOA0_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA0_CTL_OFFSET 0x2c +#define GC_PINMUX_DIOA0_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA1_SEL_OFFSET 0x30 +#define GC_PINMUX_DIOA1_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA1_CTL_OFFSET 0x34 +#define GC_PINMUX_DIOA1_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA2_SEL_OFFSET 0x38 +#define GC_PINMUX_DIOA2_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA2_CTL_OFFSET 0x3c +#define GC_PINMUX_DIOA2_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA3_SEL_OFFSET 0x40 +#define GC_PINMUX_DIOA3_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA3_CTL_OFFSET 0x44 +#define GC_PINMUX_DIOA3_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA4_SEL_OFFSET 0x48 +#define GC_PINMUX_DIOA4_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA4_CTL_OFFSET 0x4c +#define GC_PINMUX_DIOA4_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA5_SEL_OFFSET 0x50 +#define GC_PINMUX_DIOA5_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA5_CTL_OFFSET 0x54 +#define GC_PINMUX_DIOA5_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA6_SEL_OFFSET 0x58 +#define GC_PINMUX_DIOA6_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA6_CTL_OFFSET 0x5c +#define GC_PINMUX_DIOA6_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA7_SEL_OFFSET 0x60 +#define GC_PINMUX_DIOA7_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA7_CTL_OFFSET 0x64 +#define GC_PINMUX_DIOA7_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA8_SEL_OFFSET 0x68 +#define GC_PINMUX_DIOA8_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA8_CTL_OFFSET 0x6c +#define GC_PINMUX_DIOA8_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA9_SEL_OFFSET 0x70 +#define GC_PINMUX_DIOA9_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA9_CTL_OFFSET 0x74 +#define GC_PINMUX_DIOA9_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA10_SEL_OFFSET 0x78 +#define GC_PINMUX_DIOA10_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA10_CTL_OFFSET 0x7c +#define GC_PINMUX_DIOA10_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA11_SEL_OFFSET 0x80 +#define GC_PINMUX_DIOA11_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA11_CTL_OFFSET 0x84 +#define GC_PINMUX_DIOA11_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA12_SEL_OFFSET 0x88 +#define GC_PINMUX_DIOA12_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA12_CTL_OFFSET 0x8c +#define GC_PINMUX_DIOA12_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA13_SEL_OFFSET 0x90 +#define GC_PINMUX_DIOA13_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA13_CTL_OFFSET 0x94 +#define GC_PINMUX_DIOA13_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOA14_SEL_OFFSET 0x98 +#define GC_PINMUX_DIOA14_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOA14_CTL_OFFSET 0x9c +#define GC_PINMUX_DIOA14_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB0_SEL_OFFSET 0xa0 +#define GC_PINMUX_DIOB0_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB0_CTL_OFFSET 0xa4 +#define GC_PINMUX_DIOB0_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB1_SEL_OFFSET 0xa8 +#define GC_PINMUX_DIOB1_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB1_CTL_OFFSET 0xac +#define GC_PINMUX_DIOB1_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB2_SEL_OFFSET 0xb0 +#define GC_PINMUX_DIOB2_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB2_CTL_OFFSET 0xb4 +#define GC_PINMUX_DIOB2_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB3_SEL_OFFSET 0xb8 +#define GC_PINMUX_DIOB3_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB3_CTL_OFFSET 0xbc +#define GC_PINMUX_DIOB3_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB4_SEL_OFFSET 0xc0 +#define GC_PINMUX_DIOB4_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB4_CTL_OFFSET 0xc4 +#define GC_PINMUX_DIOB4_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB5_SEL_OFFSET 0xc8 +#define GC_PINMUX_DIOB5_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB5_CTL_OFFSET 0xcc +#define GC_PINMUX_DIOB5_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB6_SEL_OFFSET 0xd0 +#define GC_PINMUX_DIOB6_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB6_CTL_OFFSET 0xd4 +#define GC_PINMUX_DIOB6_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB7_SEL_OFFSET 0xd8 +#define GC_PINMUX_DIOB7_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB7_CTL_OFFSET 0xdc +#define GC_PINMUX_DIOB7_CTL_DEFAULT 0x3 +#define GC_PINMUX_DIOB8_SEL_OFFSET 0xe0 +#define GC_PINMUX_DIOB8_SEL_DEFAULT 0x0 +#define GC_PINMUX_DIOB8_CTL_OFFSET 0xe4 +#define GC_PINMUX_DIOB8_CTL_DEFAULT 0x3 +#define GC_PINMUX_RTCXOP_SEL_OFFSET 0xe8 +#define GC_PINMUX_RTCXOP_SEL_DEFAULT 0x0 +#define GC_PINMUX_RTCXOP_CTL_OFFSET 0xec +#define GC_PINMUX_RTCXOP_CTL_DEFAULT 0x3 +#define GC_PINMUX_SWDPTRACE_SEL_OFFSET 0xf0 +#define GC_PINMUX_SWDPTRACE_SEL_DEFAULT 0x0 +#define GC_PINMUX_SWDPTRACE_CTL_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_DEFAULT 0x3 +#define GC_PINMUX_SWDPDATA_SEL_OFFSET 0xf8 +#define GC_PINMUX_SWDPDATA_SEL_DEFAULT 0x0 +#define GC_PINMUX_SWDPDATA_CTL_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_DEFAULT 0x7 +#define GC_PINMUX_TESTMODE_SEL_OFFSET 0x100 +#define GC_PINMUX_TESTMODE_SEL_DEFAULT 0x0 +#define GC_PINMUX_TESTMODE_CTL_OFFSET 0x104 +#define GC_PINMUX_TESTMODE_CTL_DEFAULT 0x7 +#define GC_PINMUX_RESETB_SEL_OFFSET 0x108 +#define GC_PINMUX_RESETB_SEL_DEFAULT 0x0 +#define GC_PINMUX_RESETB_CTL_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_DEFAULT 0x7 +#define GC_PINMUX_VIO0_SEL_OFFSET 0x110 +#define GC_PINMUX_VIO0_SEL_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_OFFSET 0x114 +#define GC_PINMUX_VIO0_CTL_DEFAULT 0x3 +#define GC_PINMUX_VIO1_SEL_OFFSET 0x118 +#define GC_PINMUX_VIO1_SEL_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_OFFSET 0x11c +#define GC_PINMUX_VIO1_CTL_DEFAULT 0x3 +#define GC_PINMUX_TDI_SEL_OFFSET 0x120 +#define GC_PINMUX_TDI_SEL_DEFAULT 0x0 +#define GC_PINMUX_TDI_CTL_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_DEFAULT 0x3 +#define GC_PINMUX_TMS_SEL_OFFSET 0x128 +#define GC_PINMUX_TMS_SEL_DEFAULT 0x0 +#define GC_PINMUX_TMS_CTL_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_DEFAULT 0x3 +#define GC_PINMUX_TCK_SEL_OFFSET 0x130 +#define GC_PINMUX_TCK_SEL_DEFAULT 0x0 +#define GC_PINMUX_TCK_CTL_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_DEFAULT 0x3 +#define GC_PINMUX_TDO_SEL_OFFSET 0x138 +#define GC_PINMUX_TDO_SEL_DEFAULT 0x0 +#define GC_PINMUX_TDO_CTL_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_DEFAULT 0x3 +#define GC_PINMUX_SETHOLD0_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD1_OFFSET 0x144 +#define GC_PINMUX_SETHOLD1_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD1_OFFSET 0x14c +#define GC_PINMUX_CLRHOLD1_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO0_SEL_OFFSET 0x150 +#define GC_PINMUX_GPIO0_GPIO0_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO1_SEL_OFFSET 0x154 +#define GC_PINMUX_GPIO0_GPIO1_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO2_SEL_OFFSET 0x158 +#define GC_PINMUX_GPIO0_GPIO2_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO3_SEL_OFFSET 0x15c +#define GC_PINMUX_GPIO0_GPIO3_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO4_SEL_OFFSET 0x160 +#define GC_PINMUX_GPIO0_GPIO4_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO5_SEL_OFFSET 0x164 +#define GC_PINMUX_GPIO0_GPIO5_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO6_SEL_OFFSET 0x168 +#define GC_PINMUX_GPIO0_GPIO6_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO7_SEL_OFFSET 0x16c +#define GC_PINMUX_GPIO0_GPIO7_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO8_SEL_OFFSET 0x170 +#define GC_PINMUX_GPIO0_GPIO8_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO9_SEL_OFFSET 0x174 +#define GC_PINMUX_GPIO0_GPIO9_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO10_SEL_OFFSET 0x178 +#define GC_PINMUX_GPIO0_GPIO10_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO11_SEL_OFFSET 0x17c +#define GC_PINMUX_GPIO0_GPIO11_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO12_SEL_OFFSET 0x180 +#define GC_PINMUX_GPIO0_GPIO12_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO13_SEL_OFFSET 0x184 +#define GC_PINMUX_GPIO0_GPIO13_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO14_SEL_OFFSET 0x188 +#define GC_PINMUX_GPIO0_GPIO14_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO0_GPIO15_SEL_OFFSET 0x18c +#define GC_PINMUX_GPIO0_GPIO15_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO0_SEL_OFFSET 0x190 +#define GC_PINMUX_GPIO1_GPIO0_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO1_SEL_OFFSET 0x194 +#define GC_PINMUX_GPIO1_GPIO1_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO2_SEL_OFFSET 0x198 +#define GC_PINMUX_GPIO1_GPIO2_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO3_SEL_OFFSET 0x19c +#define GC_PINMUX_GPIO1_GPIO3_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO4_SEL_OFFSET 0x1a0 +#define GC_PINMUX_GPIO1_GPIO4_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO5_SEL_OFFSET 0x1a4 +#define GC_PINMUX_GPIO1_GPIO5_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO6_SEL_OFFSET 0x1a8 +#define GC_PINMUX_GPIO1_GPIO6_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO7_SEL_OFFSET 0x1ac +#define GC_PINMUX_GPIO1_GPIO7_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO8_SEL_OFFSET 0x1b0 +#define GC_PINMUX_GPIO1_GPIO8_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO9_SEL_OFFSET 0x1b4 +#define GC_PINMUX_GPIO1_GPIO9_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO10_SEL_OFFSET 0x1b8 +#define GC_PINMUX_GPIO1_GPIO10_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO11_SEL_OFFSET 0x1bc +#define GC_PINMUX_GPIO1_GPIO11_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO12_SEL_OFFSET 0x1c0 +#define GC_PINMUX_GPIO1_GPIO12_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO13_SEL_OFFSET 0x1c4 +#define GC_PINMUX_GPIO1_GPIO13_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO14_SEL_OFFSET 0x1c8 +#define GC_PINMUX_GPIO1_GPIO14_SEL_DEFAULT 0x0 +#define GC_PINMUX_GPIO1_GPIO15_SEL_OFFSET 0x1cc +#define GC_PINMUX_GPIO1_GPIO15_SEL_DEFAULT 0x0 +#define GC_PINMUX_I2CS0_SCL_SEL_OFFSET 0x1d0 +#define GC_PINMUX_I2CS0_SCL_SEL_DEFAULT 0x0 +#define GC_PINMUX_I2CS0_SDA_SEL_OFFSET 0x1d4 +#define GC_PINMUX_I2CS0_SDA_SEL_DEFAULT 0x0 +#define GC_PINMUX_I2C0_SCL_SEL_OFFSET 0x1d8 +#define GC_PINMUX_I2C0_SCL_SEL_DEFAULT 0x0 +#define GC_PINMUX_I2C0_SDA_SEL_OFFSET 0x1dc +#define GC_PINMUX_I2C0_SDA_SEL_DEFAULT 0x0 +#define GC_PINMUX_I2C1_SCL_SEL_OFFSET 0x1e0 +#define GC_PINMUX_I2C1_SCL_SEL_DEFAULT 0x0 +#define GC_PINMUX_I2C1_SDA_SEL_OFFSET 0x1e4 +#define GC_PINMUX_I2C1_SDA_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_TESTBUS0_SEL_OFFSET 0x1e8 +#define GC_PINMUX_PMU_TESTBUS0_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_TESTBUS1_SEL_OFFSET 0x1ec +#define GC_PINMUX_PMU_TESTBUS1_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_TESTBUS2_SEL_OFFSET 0x1f0 +#define GC_PINMUX_PMU_TESTBUS2_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_TESTBUS3_SEL_OFFSET 0x1f4 +#define GC_PINMUX_PMU_TESTBUS3_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_TESTBUS4_SEL_OFFSET 0x1f8 +#define GC_PINMUX_PMU_TESTBUS4_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_TESTBUS5_SEL_OFFSET 0x1fc +#define GC_PINMUX_PMU_TESTBUS5_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_TESTBUS6_SEL_OFFSET 0x200 +#define GC_PINMUX_PMU_TESTBUS6_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_TESTBUS7_SEL_OFFSET 0x204 +#define GC_PINMUX_PMU_TESTBUS7_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_AC_PRESENT_SEL_OFFSET 0x208 +#define GC_PINMUX_RBOX0_AC_PRESENT_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_BATT_EN_SEL_OFFSET 0x20c +#define GC_PINMUX_RBOX0_BATT_EN_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_EC_IN_RW_SEL_OFFSET 0x210 +#define GC_PINMUX_RBOX0_EC_IN_RW_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_EC_RST_L_SEL_OFFSET 0x214 +#define GC_PINMUX_RBOX0_EC_RST_L_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_EC_WP_L_SEL_OFFSET 0x218 +#define GC_PINMUX_RBOX0_EC_WP_L_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_ENTERING_RW_SEL_OFFSET 0x21c +#define GC_PINMUX_RBOX0_ENTERING_RW_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_FW_WP_L_SEL_OFFSET 0x220 +#define GC_PINMUX_RBOX0_FW_WP_L_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_KSI_SEL_OFFSET 0x224 +#define GC_PINMUX_RBOX0_KSI_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_KSI_SW_SEL_OFFSET 0x228 +#define GC_PINMUX_RBOX0_KSI_SW_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_KSO_INV_SEL_OFFSET 0x22c +#define GC_PINMUX_RBOX0_KSO_INV_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_KSO_SW_SEL_OFFSET 0x230 +#define GC_PINMUX_RBOX0_KSO_SW_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_PWR_BTN_L_SEL_OFFSET 0x234 +#define GC_PINMUX_RBOX0_PWR_BTN_L_SEL_DEFAULT 0x0 +#define GC_PINMUX_RBOX0_PWR_BTNO_L_SEL_OFFSET 0x238 +#define GC_PINMUX_RBOX0_PWR_BTNO_L_SEL_DEFAULT 0x0 +#define GC_PINMUX_RTC0_X_RTC_CLK_SEL_OFFSET 0x23c +#define GC_PINMUX_RTC0_X_RTC_CLK_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPI0_SPICLK_SEL_OFFSET 0x240 +#define GC_PINMUX_SPI0_SPICLK_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPI0_SPICSB_SEL_OFFSET 0x244 +#define GC_PINMUX_SPI0_SPICSB_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPI0_SPIMISO_SEL_OFFSET 0x248 +#define GC_PINMUX_SPI0_SPIMISO_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPI0_SPIMOSI_SEL_OFFSET 0x24c +#define GC_PINMUX_SPI0_SPIMOSI_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPS0_SPICLK_SEL_OFFSET 0x250 +#define GC_PINMUX_SPS0_SPICLK_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPS0_SPICSB_SEL_OFFSET 0x254 +#define GC_PINMUX_SPS0_SPICSB_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPS0_SPIMISO_SEL_OFFSET 0x258 +#define GC_PINMUX_SPS0_SPIMISO_SEL_DEFAULT 0x0 +#define GC_PINMUX_SPS0_SPIMOSI_SEL_OFFSET 0x25c +#define GC_PINMUX_SPS0_SPIMOSI_SEL_DEFAULT 0x0 +#define GC_PINMUX_SWDP0_TRACE_SEL_OFFSET 0x260 +#define GC_PINMUX_SWDP0_TRACE_SEL_DEFAULT 0x0 +#define GC_PINMUX_SWDP0_TRACE2_SEL_OFFSET 0x264 +#define GC_PINMUX_SWDP0_TRACE2_SEL_DEFAULT 0x0 +#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_OFFSET 0x268 +#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_DEFAULT 0x0 +#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_OFFSET 0x26c +#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_DEFAULT 0x0 +#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_OFFSET 0x270 +#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_DEFAULT 0x0 +#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_OFFSET 0x274 +#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_DEFAULT 0x0 +#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_OFFSET 0x278 +#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_DEFAULT 0x0 +#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_OFFSET 0x27c +#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART0_CTS_SEL_OFFSET 0x280 +#define GC_PINMUX_UART0_CTS_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART0_RTS_SEL_OFFSET 0x284 +#define GC_PINMUX_UART0_RTS_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART0_RX_SEL_OFFSET 0x288 +#define GC_PINMUX_UART0_RX_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART0_TX_SEL_OFFSET 0x28c +#define GC_PINMUX_UART0_TX_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART1_CTS_SEL_OFFSET 0x290 +#define GC_PINMUX_UART1_CTS_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART1_RTS_SEL_OFFSET 0x294 +#define GC_PINMUX_UART1_RTS_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART1_RX_SEL_OFFSET 0x298 +#define GC_PINMUX_UART1_RX_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART1_TX_SEL_OFFSET 0x29c +#define GC_PINMUX_UART1_TX_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART2_CTS_SEL_OFFSET 0x2a0 +#define GC_PINMUX_UART2_CTS_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART2_RTS_SEL_OFFSET 0x2a4 +#define GC_PINMUX_UART2_RTS_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART2_RX_SEL_OFFSET 0x2a8 +#define GC_PINMUX_UART2_RX_SEL_DEFAULT 0x0 +#define GC_PINMUX_UART2_TX_SEL_OFFSET 0x2ac +#define GC_PINMUX_UART2_TX_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x2b0 +#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x2b4 +#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x2b8 +#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x2bc +#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x2c0 +#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x2c4 +#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x2c8 +#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x2cc +#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x2d0 +#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x2d4 +#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0 +#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x2d8 +#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0 +#define GC_PINMUX_XO0_TESTCLK_SEL_OFFSET 0x2dc +#define GC_PINMUX_XO0_TESTCLK_SEL_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_OFFSET 0x2e4 +#define GC_PINMUX_EXITEN1_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_OFFSET 0x2ec +#define GC_PINMUX_EXITEDGE1_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_OFFSET 0x2f4 +#define GC_PINMUX_EXITINV1_DEFAULT 0x0 +#define GC_PMU_RESET_OFFSET 0x0 +#define GC_PMU_RESET_DEFAULT 0x3 +#define GC_PMU_SETRST_OFFSET 0x4 +#define GC_PMU_SETRST_DEFAULT 0x0 +#define GC_PMU_CLRRST_OFFSET 0x8 +#define GC_PMU_CLRRST_DEFAULT 0x0 +#define GC_PMU_RSTSRC_OFFSET 0xc +#define GC_PMU_RSTSRC_DEFAULT 0x0 +#define GC_PMU_GLOBAL_RESET_OFFSET 0x10 +#define GC_PMU_GLOBAL_RESET_DEFAULT 0x0 +#define GC_PMU_GLOBAL_RESET_KEY 0x7041776 +#define GC_PMU_SETDIS_OFFSET 0x14 +#define GC_PMU_SETDIS_DEFAULT 0x0 +#define GC_PMU_CLRDIS_OFFSET 0x18 +#define GC_PMU_CLRDIS_DEFAULT 0x0 +#define GC_PMU_STATDIS_OFFSET 0x1c +#define GC_PMU_STATDIS_DEFAULT 0xec000 +#define GC_PMU_SETWIC_OFFSET 0x20 +#define GC_PMU_SETWIC_DEFAULT 0x0 +#define GC_PMU_CLRWIC_OFFSET 0x24 +#define GC_PMU_CLRWIC_DEFAULT 0x0 +#define GC_PMU_SYSVTOR_OFFSET 0x28 +#define GC_PMU_SYSVTOR_DEFAULT 0xffffffff +#define GC_PMU_EXCLUSIVE_OFFSET 0x2c +#define GC_PMU_EXCLUSIVE_DEFAULT 0x0 +#define GC_PMU_DAP_ID0_OFFSET 0x30 +#define GC_PMU_DAP_ID0_DEFAULT 0x0 +#define GC_PMU_DAP_EN_OFFSET 0x34 +#define GC_PMU_DAP_EN_DEFAULT 0x0 +#define GC_PMU_DAP_LOCK_OFFSET 0x38 +#define GC_PMU_DAP_LOCK_DEFAULT 0x1 +#define GC_PMU_DAP_UNLOCK_OFFSET 0x3c +#define GC_PMU_DAP_UNLOCK_DEFAULT 0x0 +#define GC_PMU_DAP_UNLOCK_KEY 0xb4502f2f +#define GC_PMU_NAP_EN_OFFSET 0x40 +#define GC_PMU_NAP_EN_DEFAULT 0x0 +#define GC_PMUU_ADC_OFFSET 0x44 +#define GC_PMUU_ADC_DEFAULT 0x0 +#define GC_PMUSETU_ADC_OFFSET 0x48 +#define GC_PMUSETU_ADC_DEFAULT 0x0 +#define GC_PMUCLRU_ADC_OFFSET 0x4c +#define GC_PMUCLRU_ADC_DEFAULT 0x0 +#define GC_PMUSETU_TRNG_TOP_OFFSET 0x50 +#define GC_PMUSETU_TRNG_TOP_DEFAULT 0x0 +#define GC_PMUCLRU_TRNG_TOP_OFFSET 0x54 +#define GC_PMUCLRU_TRNG_TOP_DEFAULT 0x0 +#define GC_PMUSETRTC_OFFSET 0x58 +#define GC_PMUSETRTC_DEFAULT 0x0 +#define GC_PMUCLRRTC_OFFSET 0x5c +#define GC_PMUCLRRTC_DEFAULT 0x0 +#define GC_PMU_VREF_OFFSET 0x60 +#define GC_PMU_VREF_DEFAULT 0xffff88 +#define GC_PMU_VREFCMP_OFFSET 0x64 +#define GC_PMU_VREFCMP_DEFAULT 0x0 +#define GC_PMU_RBIAS_OFFSET 0x68 +#define GC_PMU_RBIAS_DEFAULT 0x0 +#define GC_PMU_RBIASLO_OFFSET 0x6c +#define GC_PMU_RBIASLO_DEFAULT 0x0 +#define GC_PMU_RBIASHI_OFFSET 0x70 +#define GC_PMU_RBIASHI_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_DEFAULT 0x0 +#define GC_PMU_BAT_LVL_OK_OFFSET 0x7c +#define GC_PMU_BAT_LVL_OK_DEFAULT 0x0 +#define GC_PMU_B_REG_DIG_CTRL_OFFSET 0x80 +#define GC_PMU_B_REG_DIG_CTRL_DEFAULT 0x0 +#define GC_PMU_B_REG_DIG_LATCH_CTRL_OFFSET 0x84 +#define GC_PMU_B_REG_DIG_LATCH_CTRL_DEFAULT 0x0 +#define GC_PMU_EXITPD_HOLD_SET_OFFSET 0x88 +#define GC_PMU_EXITPD_HOLD_SET_DEFAULT 0x0 +#define GC_PMU_EXITPD_HOLD_CLR_OFFSET 0x8c +#define GC_PMU_EXITPD_HOLD_CLR_DEFAULT 0x0 +#define GC_PMU_EXITPD_MASK_OFFSET 0x90 +#define GC_PMU_EXITPD_MASK_DEFAULT 0x7 +#define GC_PMU_EXITPD_SRC_OFFSET 0x94 +#define GC_PMU_EXITPD_SRC_DEFAULT 0x0 +#define GC_PMU_EXITPD_MON_OFFSET 0x98 +#define GC_PMU_EXITPD_MON_DEFAULT 0x0 +#define GC_PMU_OSC_HOLD_SET_OFFSET 0x9c +#define GC_PMU_OSC_HOLD_SET_DEFAULT 0x0 +#define GC_PMU_OSC_HOLD_CLR_OFFSET 0xa0 +#define GC_PMU_OSC_HOLD_CLR_DEFAULT 0x0 +#define GC_PMU_OSC_SELECT_OFFSET 0xa4 +#define GC_PMU_OSC_SELECT_DEFAULT 0x3 +#define GC_PMU_OSC_SELECT_XTL 0x0 +#define GC_PMU_OSC_SELECT_RC_TRIM 0x2 +#define GC_PMU_OSC_SELECT_RC 0x3 +#define GC_PMU_OSC_SELECT_STAT_OFFSET 0xa8 +#define GC_PMU_OSC_SELECT_STAT_DEFAULT 0x3 +#define GC_PMU_OSC_SELECT_STAT_XTL 0x0 +#define GC_PMU_OSC_SELECT_STAT_RC_TRIM 0x2 +#define GC_PMU_OSC_SELECT_STAT_RC 0x3 +#define GC_PMU_OSC_CTRL_OFFSET 0xac +#define GC_PMU_OSC_CTRL_DEFAULT 0x3 +#define GC_PMU_MEMCLKSET_OFFSET 0xb0 +#define GC_PMU_MEMCLKSET_DEFAULT 0x7f +#define GC_PMU_MEMCLKCLR_OFFSET 0xb4 +#define GC_PMU_MEMCLKCLR_DEFAULT 0x7f +#define GC_PMU_PERICLKSET0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DEFAULT 0x3c08 +#define GC_PMU_PERICLKCLR0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DEFAULT 0x3c08 +#define GC_PMU_PERICLKSET1_OFFSET 0xc0 +#define GC_PMU_PERICLKSET1_DEFAULT 0x7 +#define GC_PMU_PERICLKCLR1_OFFSET 0xc4 +#define GC_PMU_PERICLKCLR1_DEFAULT 0x7 +#define GC_PMU_PERIGATEONSLEEPSET0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DEFAULT 0x80089c00 +#define GC_PMU_PERIGATEONSLEEPCLR0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DEFAULT 0x80089c00 +#define GC_PMU_PERIGATEONSLEEPSET1_OFFSET 0xd0 +#define GC_PMU_PERIGATEONSLEEPSET1_DEFAULT 0x7 +#define GC_PMU_PERIGATEONSLEEPCLR1_OFFSET 0xd4 +#define GC_PMU_PERIGATEONSLEEPCLR1_DEFAULT 0x7 +#define GC_PMU_CLK0_OFFSET 0xd8 +#define GC_PMU_CLK0_DEFAULT 0x1f +#define GC_PMU_CLK1_OFFSET 0xdc +#define GC_PMU_CLK1_DEFAULT 0x1f +#define GC_PMU_RST0_OFFSET 0xe0 +#define GC_PMU_RST0_DEFAULT 0x0 +#define GC_PMU_RST1_OFFSET 0xe4 +#define GC_PMU_RST1_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH_HOLD_SET_OFFSET 0xe8 +#define GC_PMU_PWRDN_SCRATCH_HOLD_SET_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH_HOLD_CLR_OFFSET 0xec +#define GC_PMU_PWRDN_SCRATCH_HOLD_CLR_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH0_OFFSET 0xf0 +#define GC_PMU_PWRDN_SCRATCH0_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH1_OFFSET 0xf4 +#define GC_PMU_PWRDN_SCRATCH1_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH2_OFFSET 0xf8 +#define GC_PMU_PWRDN_SCRATCH2_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH3_OFFSET 0xfc +#define GC_PMU_PWRDN_SCRATCH3_DEFAULT 0x0 +#define GC_PMU_FUSE_EN_SET_OFFSET 0x100 +#define GC_PMU_FUSE_EN_SET_DEFAULT 0x0 +#define GC_PMU_FUSE_EN_CLR_OFFSET 0x104 +#define GC_PMU_FUSE_EN_CLR_DEFAULT 0x0 +#define GC_PMU_FUSE_START_OFFSET 0x108 +#define GC_PMU_FUSE_START_DEFAULT 0x0 +#define GC_PMU_FUSE_START_KEY 0x11de784a +#define GC_PMU_FUSE_CTRL_OFFSET 0x10c +#define GC_PMU_FUSE_CTRL_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_DEV_UID0_OFFSET 0x110 +#define GC_PMU_FUSE_WR_DEV_UID0_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_DEV_UID1_OFFSET 0x114 +#define GC_PMU_FUSE_WR_DEV_UID1_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_ID_OFFSET 0x118 +#define GC_PMU_FUSE_WR_ID_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_OFFSET 0x11c +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_OFFSET 0x120 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_OFFSET 0x124 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_LOCK_OFFSET 0x128 +#define GC_PMU_FUSE_WR_LOCK_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RSRV1_OFFSET 0x12c +#define GC_PMU_FUSE_WR_RSRV1_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RSRV2_OFFSET 0x130 +#define GC_PMU_FUSE_WR_RSRV2_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RSRV3_OFFSET 0x134 +#define GC_PMU_FUSE_WR_RSRV3_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RSRV4_OFFSET 0x138 +#define GC_PMU_FUSE_WR_RSRV4_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RSRV5_OFFSET 0x13c +#define GC_PMU_FUSE_WR_RSRV5_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_DEV_UID0_OFFSET 0x140 +#define GC_PMU_FUSE_RD_DEV_UID0_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_DEV_UID1_OFFSET 0x144 +#define GC_PMU_FUSE_RD_DEV_UID1_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_ID_OFFSET 0x148 +#define GC_PMU_FUSE_RD_ID_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_OFFSET 0x14c +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_OFFSET 0x150 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_OFFSET 0x154 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_LOCK_OFFSET 0x158 +#define GC_PMU_FUSE_RD_LOCK_DEFAULT 0x2 +#define GC_PMU_FUSE_RD_RSRV1_OFFSET 0x15c +#define GC_PMU_FUSE_RD_RSRV1_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RSRV2_OFFSET 0x160 +#define GC_PMU_FUSE_RD_RSRV2_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RSRV3_OFFSET 0x164 +#define GC_PMU_FUSE_RD_RSRV3_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RSRV4_OFFSET 0x168 +#define GC_PMU_FUSE_RD_RSRV4_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RSRV5_OFFSET 0x16c +#define GC_PMU_FUSE_RD_RSRV5_DEFAULT 0x0 +#define GC_PMU_FUSE_TIMING_OFFSET 0x170 +#define GC_PMU_FUSE_TIMING_DEFAULT 0x8007d +#define GC_PMU_FUSE_OVRD_EN_OFFSET 0x174 +#define GC_PMU_FUSE_OVRD_EN_DEFAULT 0x0 +#define GC_PMU_FUSE_OVRD_EN_KEY 0x1084210 +#define GC_PMU_FUSE_OVRD_OFFSET 0x178 +#define GC_PMU_FUSE_OVRD_DEFAULT 0x1 +#define GC_PMU_FUSE_DBG_OFFSET 0x17c +#define GC_PMU_FUSE_DBG_DEFAULT 0x0 +#define GC_PMU_ICTRL_OFFSET 0x180 +#define GC_PMU_ICTRL_DEFAULT 0x0 +#define GC_PMU_ISTAT_OFFSET 0x184 +#define GC_PMU_ISTAT_DEFAULT 0x0 +#define GC_PMU_ITCR_OFFSET 0xf00 +#define GC_PMU_ITCR_DEFAULT 0x0 +#define GC_PMU_ITOP_OFFSET 0xf04 +#define GC_PMU_ITOP_DEFAULT 0x0 +#define GC_PMU_ANTEST_TOP_CTRL_OFFSET 0x1008 +#define GC_PMU_ANTEST_TOP_CTRL_DEFAULT 0x3 +#define GC_PMU_ANTEST1_REGDIG_OFFSET 0x1010 +#define GC_PMU_ANTEST1_REGDIG_DEFAULT 0x0 +#define GC_PMU_ANTEST_FUSE_OFFSET 0x1018 +#define GC_PMU_ANTEST_FUSE_DEFAULT 0x0 +#define GC_PMU_HW_CONTROLS_OFFSET 0x101c +#define GC_PMU_HW_CONTROLS_DEFAULT 0x0 +#define GC_PMU_HW_BYPASS_OFFSET 0x1020 +#define GC_PMU_HW_BYPASS_DEFAULT 0x0 +#define GC_PMU_ANTEST_TRNG_OFFSET 0x1024 +#define GC_PMU_ANTEST_TRNG_DEFAULT 0x0 +#define GC_PMU_ANTEST_TEMP_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_DEFAULT 0x0 +#define GC_PMU_TESTBUS_CTRL_OFFSET 0x2000 +#define GC_PMU_TESTBUS_CTRL_DEFAULT 0x0 +#define GC_PMU_CHIP_ID_OFFSET 0x1fff8 +#define GC_PMU_CHIP_ID_DEFAULT 0x1485694d +#define GC_PMU_VERSION_OFFSET 0x1fffc +#define GC_PMU_VERSION_DEFAULT 0x1100c244 +#define GC_RBOX_OVERRIDE_OFFSET 0x0 +#define GC_RBOX_OVERRIDE_DEFAULT 0x0 +#define GC_RBOX_OVERRIDE_VALUES_OFFSET 0x4 +#define GC_RBOX_OVERRIDE_VALUES_DEFAULT 0x0 +#define GC_RBOX_INPUT_VALUES_OFFSET 0x8 +#define GC_RBOX_INPUT_VALUES_DEFAULT 0x0 +#define GC_RBOX_EC_WP_L_OFFSET 0xc +#define GC_RBOX_EC_WP_L_DEFAULT 0x0 +#define GC_RBOX_FW_WP_L_OFFSET 0x10 +#define GC_RBOX_FW_WP_L_DEFAULT 0x0 +#define GC_RBOX_RESET_OFFSET 0x14 +#define GC_RBOX_RESET_DEFAULT 0x0 +#define GC_RBOX_VERSION_OFFSET 0x18 +#define GC_RBOX_VERSION_DEFAULT 0x600c16f +#define GC_RTC_CTRL_OFFSET 0x0 +#define GC_RTC_CTRL_DEFAULT 0x22f01 +#define GC_RTC_PINMUX_EN_OFFSET 0x4 +#define GC_RTC_PINMUX_EN_DEFAULT 0x0 +#define GC_RTC_SETHOLD_OFFSET 0x8 +#define GC_RTC_SETHOLD_DEFAULT 0x0 +#define GC_RTC_CLRHOLD_OFFSET 0xc +#define GC_RTC_CLRHOLD_DEFAULT 0x0 +#define GC_SHA_CFG_MSGLEN_LO_OFFSET 0x0 +#define GC_SHA_CFG_MSGLEN_LO_DEFAULT 0x0 +#define GC_SHA_CFG_MSGLEN_HI_OFFSET 0x4 +#define GC_SHA_CFG_MSGLEN_HI_DEFAULT 0x0 +#define GC_SHA_CFG_EN_OFFSET 0x8 +#define GC_SHA_CFG_EN_DEFAULT 0x1 +#define GC_SHA_TRIG_OFFSET 0xc +#define GC_SHA_TRIG_DEFAULT 0x2 +#define GC_SHA_INPUT_FIFO_OFFSET 0x10 +#define GC_SHA_INPUT_FIFO_DEFAULT 0x0 +#define GC_SHA_STS_H0_OFFSET 0x14 +#define GC_SHA_STS_H0_DEFAULT 0x0 +#define GC_SHA_STS_H1_OFFSET 0x18 +#define GC_SHA_STS_H1_DEFAULT 0x0 +#define GC_SHA_STS_H2_OFFSET 0x1c +#define GC_SHA_STS_H2_DEFAULT 0x0 +#define GC_SHA_STS_H3_OFFSET 0x20 +#define GC_SHA_STS_H3_DEFAULT 0x0 +#define GC_SHA_STS_H4_OFFSET 0x24 +#define GC_SHA_STS_H4_DEFAULT 0x0 +#define GC_SHA_STS_H5_OFFSET 0x28 +#define GC_SHA_STS_H5_DEFAULT 0x0 +#define GC_SHA_STS_H6_OFFSET 0x2c +#define GC_SHA_STS_H6_DEFAULT 0x0 +#define GC_SHA_STS_H7_OFFSET 0x30 +#define GC_SHA_STS_H7_DEFAULT 0x0 +#define GC_SHA_STS_W0_OFFSET 0x34 +#define GC_SHA_STS_W0_DEFAULT 0x0 +#define GC_SHA_STS_W1_OFFSET 0x38 +#define GC_SHA_STS_W1_DEFAULT 0x0 +#define GC_SHA_STS_W2_OFFSET 0x3c +#define GC_SHA_STS_W2_DEFAULT 0x0 +#define GC_SHA_STS_W3_OFFSET 0x40 +#define GC_SHA_STS_W3_DEFAULT 0x0 +#define GC_SHA_STS_W4_OFFSET 0x44 +#define GC_SHA_STS_W4_DEFAULT 0x0 +#define GC_SHA_STS_W5_OFFSET 0x48 +#define GC_SHA_STS_W5_DEFAULT 0x0 +#define GC_SHA_STS_W6_OFFSET 0x4c +#define GC_SHA_STS_W6_DEFAULT 0x0 +#define GC_SHA_STS_W7_OFFSET 0x50 +#define GC_SHA_STS_W7_DEFAULT 0x0 +#define GC_SHA_STS_W8_OFFSET 0x54 +#define GC_SHA_STS_W8_DEFAULT 0x0 +#define GC_SHA_STS_W9_OFFSET 0x58 +#define GC_SHA_STS_W9_DEFAULT 0x0 +#define GC_SHA_STS_W10_OFFSET 0x5c +#define GC_SHA_STS_W10_DEFAULT 0x0 +#define GC_SHA_STS_W11_OFFSET 0x60 +#define GC_SHA_STS_W11_DEFAULT 0x0 +#define GC_SHA_STS_W12_OFFSET 0x64 +#define GC_SHA_STS_W12_DEFAULT 0x0 +#define GC_SHA_STS_W13_OFFSET 0x68 +#define GC_SHA_STS_W13_DEFAULT 0x0 +#define GC_SHA_STS_W14_OFFSET 0x6c +#define GC_SHA_STS_W14_DEFAULT 0x0 +#define GC_SHA_STS_W15_OFFSET 0x70 +#define GC_SHA_STS_W15_DEFAULT 0x0 +#define GC_SHA_STS_A_OFFSET 0x74 +#define GC_SHA_STS_A_DEFAULT 0x0 +#define GC_SHA_STS_B_OFFSET 0x78 +#define GC_SHA_STS_B_DEFAULT 0x0 +#define GC_SHA_STS_C_OFFSET 0x7c +#define GC_SHA_STS_C_DEFAULT 0x0 +#define GC_SHA_STS_D_OFFSET 0x80 +#define GC_SHA_STS_D_DEFAULT 0x0 +#define GC_SHA_STS_E_OFFSET 0x84 +#define GC_SHA_STS_E_DEFAULT 0x0 +#define GC_SHA_STS_F_OFFSET 0x88 +#define GC_SHA_STS_F_DEFAULT 0x0 +#define GC_SHA_STS_G_OFFSET 0x8c +#define GC_SHA_STS_G_DEFAULT 0x0 +#define GC_SHA_STS_H_OFFSET 0x90 +#define GC_SHA_STS_H_DEFAULT 0x0 +#define GC_SHA_ITCR_OFFSET 0xf00 +#define GC_SHA_ITCR_DEFAULT 0x0 +#define GC_SHA_ITOP_OFFSET 0xf04 +#define GC_SHA_ITOP_DEFAULT 0x0 +#define GC_SPI_CTRL_OFFSET 0x0 +#define GC_SPI_CTRL_DEFAULT 0x2800800 +#define GC_SPI_XACT_OFFSET 0x4 +#define GC_SPI_XACT_DEFAULT 0xe +#define GC_SPI_ICTRL_OFFSET 0x8 +#define GC_SPI_ICTRL_DEFAULT 0x0 +#define GC_SPI_ISTATE_OFFSET 0xc +#define GC_SPI_ISTATE_DEFAULT 0x0 +#define GC_SPI_ISTATE_CLR_OFFSET 0x10 +#define GC_SPI_ISTATE_CLR_DEFAULT 0x0 +#define GC_SPI_OVRD_OFFSET 0x14 +#define GC_SPI_OVRD_DEFAULT 0x8 +#define GC_SPI_VAL_OFFSET 0x18 +#define GC_SPI_VAL_DEFAULT 0x0 +#define GC_SPI_ITCR_OFFSET 0xf00 +#define GC_SPI_ITCR_DEFAULT 0x0 +#define GC_SPI_ITOP_OFFSET 0xf04 +#define GC_SPI_ITOP_DEFAULT 0x0 +#define GC_SPI_DATA_OFFSET 0x1000 +#define GC_SPI_TX_DATA_OFFSET 0x1000 +#define GC_SPI_RX_DATA_OFFSET 0x1080 +#define GC_SPS_CTRL_OFFSET 0x0 +#define GC_SPS_CTRL_DEFAULT 0x181 +#define GC_SPS_DUMMY_WORD_OFFSET 0x4 +#define GC_SPS_DUMMY_WORD_DEFAULT 0xff +#define GC_SPS_STATUS01_OFFSET 0x8 +#define GC_SPS_STATUS01_DEFAULT 0x0 +#define GC_SPS_STATUS23_OFFSET 0xc +#define GC_SPS_STATUS23_DEFAULT 0x0 +#define GC_SPS_STATUS45_OFFSET 0x10 +#define GC_SPS_STATUS45_DEFAULT 0x0 +#define GC_SPS_STATUS67_OFFSET 0x14 +#define GC_SPS_STATUS67_DEFAULT 0x0 +#define GC_SPS_CTRL01_OFFSET 0x18 +#define GC_SPS_CTRL01_DEFAULT 0x0 +#define GC_SPS_CTRL23_OFFSET 0x1c +#define GC_SPS_CTRL23_DEFAULT 0x0 +#define GC_SPS_CTRL45_OFFSET 0x20 +#define GC_SPS_CTRL45_DEFAULT 0x0 +#define GC_SPS_CTRL67_OFFSET 0x24 +#define GC_SPS_CTRL67_DEFAULT 0x0 +#define GC_SPS_FIFO_CTRL_OFFSET 0x28 +#define GC_SPS_FIFO_CTRL_DEFAULT 0x0 +#define GC_SPS_TXFIFO_SIZE_OFFSET 0x2c +#define GC_SPS_TXFIFO_SIZE_DEFAULT 0x0 +#define GC_SPS_TXFIFO_RPTR_OFFSET 0x30 +#define GC_SPS_TXFIFO_RPTR_DEFAULT 0x0 +#define GC_SPS_TXFIFO_WPTR_OFFSET 0x34 +#define GC_SPS_TXFIFO_WPTR_DEFAULT 0x0 +#define GC_SPS_TXFIFO_THRESHOLD_OFFSET 0x38 +#define GC_SPS_TXFIFO_THRESHOLD_DEFAULT 0x0 +#define GC_SPS_RXFIFO_SIZE_OFFSET 0x3c +#define GC_SPS_RXFIFO_SIZE_DEFAULT 0x0 +#define GC_SPS_RXFIFO_RPTR_OFFSET 0x40 +#define GC_SPS_RXFIFO_RPTR_DEFAULT 0x0 +#define GC_SPS_RXFIFO_WPTR_OFFSET 0x44 +#define GC_SPS_RXFIFO_WPTR_DEFAULT 0x0 +#define GC_SPS_RXFIFO_THRESHOLD_OFFSET 0x48 +#define GC_SPS_RXFIFO_THRESHOLD_DEFAULT 0x0 +#define GC_SPS_ROM_REGION0_CTRL_OFFSET 0x4c +#define GC_SPS_ROM_REGION0_CTRL_DEFAULT 0x0 +#define GC_SPS_ROM_REGION0_ROM_BASE_OFFSET 0x50 +#define GC_SPS_ROM_REGION0_ROM_BASE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION0_SP_BASE_OFFSET 0x54 +#define GC_SPS_ROM_REGION0_SP_BASE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION0_SIZE_OFFSET 0x58 +#define GC_SPS_ROM_REGION0_SIZE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION0_INT_LVL_OFFSET 0x5c +#define GC_SPS_ROM_REGION0_INT_LVL_DEFAULT 0x0 +#define GC_SPS_ROM_REGION1_CTRL_OFFSET 0x60 +#define GC_SPS_ROM_REGION1_CTRL_DEFAULT 0x0 +#define GC_SPS_ROM_REGION1_ROM_BASE_OFFSET 0x64 +#define GC_SPS_ROM_REGION1_ROM_BASE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION1_SP_BASE_OFFSET 0x68 +#define GC_SPS_ROM_REGION1_SP_BASE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION1_SIZE_OFFSET 0x6c +#define GC_SPS_ROM_REGION1_SIZE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION1_INT_LVL_OFFSET 0x70 +#define GC_SPS_ROM_REGION1_INT_LVL_DEFAULT 0x0 +#define GC_SPS_ROM_REGION2_CTRL_OFFSET 0x74 +#define GC_SPS_ROM_REGION2_CTRL_DEFAULT 0x0 +#define GC_SPS_ROM_REGION2_ROM_BASE_OFFSET 0x78 +#define GC_SPS_ROM_REGION2_ROM_BASE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION2_SP_BASE_OFFSET 0x7c +#define GC_SPS_ROM_REGION2_SP_BASE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION2_SIZE_OFFSET 0x80 +#define GC_SPS_ROM_REGION2_SIZE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION2_INT_LVL_OFFSET 0x84 +#define GC_SPS_ROM_REGION2_INT_LVL_DEFAULT 0x0 +#define GC_SPS_ROM_REGION3_CTRL_OFFSET 0x88 +#define GC_SPS_ROM_REGION3_CTRL_DEFAULT 0x0 +#define GC_SPS_ROM_REGION3_ROM_BASE_OFFSET 0x8c +#define GC_SPS_ROM_REGION3_ROM_BASE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION3_SP_BASE_OFFSET 0x90 +#define GC_SPS_ROM_REGION3_SP_BASE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION3_SIZE_OFFSET 0x94 +#define GC_SPS_ROM_REGION3_SIZE_DEFAULT 0x0 +#define GC_SPS_ROM_REGION3_INT_LVL_OFFSET 0x98 +#define GC_SPS_ROM_REGION3_INT_LVL_DEFAULT 0x0 +#define GC_SPS_ROM_STATUS_OFFSET 0x9c +#define GC_SPS_ROM_STATUS_DEFAULT 0x0 +#define GC_SPS_ROM_SET_RDY_OFFSET 0xa0 +#define GC_SPS_ROM_SET_RDY_DEFAULT 0x1 +#define GC_SPS_ROM_MEM_CMD_OP_OFFSET 0xa4 +#define GC_SPS_ROM_MEM_CMD_OP_DEFAULT 0x0 +#define GC_SPS_ROM_MEM_CMD_ADDR_OFFSET 0xa8 +#define GC_SPS_ROM_MEM_CMD_ADDR_DEFAULT 0x0 +#define GC_SPS_ROM_MEM_CMD_REGION_OFFSET 0xac +#define GC_SPS_ROM_MEM_CMD_REGION_DEFAULT 0x0 +#define GC_SPS_ROM_MEM_CMD_LEN_OFFSET 0xb0 +#define GC_SPS_ROM_MEM_CMD_LEN_DEFAULT 0x0 +#define GC_SPS_OVRD_OFFSET 0xb4 +#define GC_SPS_OVRD_DEFAULT 0x0 +#define GC_SPS_VAL_OFFSET 0xb8 +#define GC_SPS_VAL_DEFAULT 0x0 +#define GC_SPS_ICTRL_OFFSET 0xbc +#define GC_SPS_ICTRL_DEFAULT 0x0 +#define GC_SPS_ISTATE_OFFSET 0xc0 +#define GC_SPS_ISTATE_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_DEFAULT 0x0 +#define GC_SPS_ITCR_OFFSET 0xf00 +#define GC_SPS_ITCR_DEFAULT 0x0 +#define GC_SPS_ITOP_OFFSET 0xf04 +#define GC_SPS_ITOP_DEFAULT 0x0 +#define GC_SPS_DATA_OFFSET 0x1000 +#define GC_SPS_TX_DATA_OFFSET 0x1000 +#define GC_SPS_RX_DATA_OFFSET 0x1400 +#define GC_SPS_ROM_SP_OFFSET 0x1000 +#define GC_SWDP_TRICKBOX_HALT_OFFSET 0x0 +#define GC_SWDP_TRICKBOX_HALT_DEFAULT 0x0 +#define GC_SWDP_TRICKBOX_UART_OFFSET 0x4 +#define GC_SWDP_TRICKBOX_UART_DEFAULT 0x0 +#define GC_SWDP_TRICKBOX_ERROR_OFFSET 0x8 +#define GC_SWDP_TRICKBOX_ERROR_DEFAULT 0x0 +#define GC_SWDP_TRICKBOX_FATAL_OFFSET 0xc +#define GC_SWDP_TRICKBOX_FATAL_DEFAULT 0x0 +#define GC_SWDP_SCRATCH_REG0_OFFSET 0x10 +#define GC_SWDP_SCRATCH_REG0_DEFAULT 0x0 +#define GC_SWDP_SCRATCH_REG1_OFFSET 0x14 +#define GC_SWDP_SCRATCH_REG1_DEFAULT 0x0 +#define GC_SWDP_SCRATCH_REG2_OFFSET 0x18 +#define GC_SWDP_SCRATCH_REG2_DEFAULT 0x0 +#define GC_SWDP_SCRATCH_REG3_OFFSET 0x1c +#define GC_SWDP_SCRATCH_REG3_DEFAULT 0x0 +#define GC_SWDP_APPSVTOR_OFFSET 0x20 +#define GC_SWDP_APPSVTOR_DEFAULT 0xffffffff +#define GC_SWDP_XML_MD5SUM_OFFSET 0x24 +#define GC_SWDP_XML_MD5SUM_DEFAULT 0x0 +#define GC_SWDP_HEADER_MD5SUM_OFFSET 0x28 +#define GC_SWDP_HEADER_MD5SUM_DEFAULT 0x0 +#define GC_SWDP_P4_LAST_SYNC_OFFSET 0x2c +#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0x0 +#define GC_SWDP_BUILD_DATE_OFFSET 0x30 +#define GC_SWDP_BUILD_DATE_DEFAULT 0x0 +#define GC_SWDP_BUILD_TIME_OFFSET 0x34 +#define GC_SWDP_BUILD_TIME_DEFAULT 0x0 +#define GC_SWDP_A1_DIO8_OFFSET 0x38 +#define GC_SWDP_A1_DIO8_DEFAULT 0x0 +#define GC_SWDP_A1_CHANNEL_SEL_OFFSET 0x3c +#define GC_SWDP_A1_CHANNEL_SEL_DEFAULT 0x0 +#define GC_TEMP_VERSION_OFFSET 0x0 +#define GC_TEMP_VERSION_DEFAULT 0xd00c178 +#define GC_TEMP_ADC_INT_ENABLE_OFFSET 0x4 +#define GC_TEMP_ADC_INT_ENABLE_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_STATE_OFFSET 0x8 +#define GC_TEMP_ADC_INT_STATE_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_TEST_OFFSET 0xc +#define GC_TEMP_ADC_INT_TEST_DEFAULT 0x0 +#define GC_TEMP_SENSE_CAL_OFFSET_OFFSET 0x10 +#define GC_TEMP_SENSE_CAL_OFFSET_DEFAULT 0x0 +#define GC_TEMP_ADC_ANALOG_CTRL_OFFSET 0x14 +#define GC_TEMP_ADC_ANALOG_CTRL_DEFAULT 0x35 +#define GC_TEMP_ADC_FSM_CTRL_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_DEFAULT 0x38864 +#define GC_TEMP_ADC_CLKDIV2_ENABLE_OFFSET 0x1c +#define GC_TEMP_ADC_CLKDIV2_ENABLE_DEFAULT 0x0 +#define GC_TEMP_ADC_ONESHOT_ACQ_OFFSET 0x20 +#define GC_TEMP_ADC_ONESHOT_ACQ_DEFAULT 0x0 +#define GC_TEMP_ADC_POWER_DOWN_B_OFFSET 0x24 +#define GC_TEMP_ADC_POWER_DOWN_B_DEFAULT 0x0 +#define GC_TEMP_ADC_OPERATION_OFFSET 0x28 +#define GC_TEMP_ADC_OPERATION_DEFAULT 0x0 +#define GC_TEMP_ADC_IOUT_OFFSET 0x2c +#define GC_TEMP_ADC_IOUT_DEFAULT 0x0 +#define GC_TEMP_ADC_SUM2_OFFSET 0x30 +#define GC_TEMP_ADC_SUM2_DEFAULT 0x0 +#define GC_TEMP_ADC_SUM4_OFFSET 0x34 +#define GC_TEMP_ADC_SUM4_DEFAULT 0x0 +#define GC_TEMP_ADC_SUM8_OFFSET 0x38 +#define GC_TEMP_ADC_SUM8_DEFAULT 0x0 +#define GC_TEMP_ADC_REF_CHOP_OFFSET 0x3c +#define GC_TEMP_ADC_REF_CHOP_DEFAULT 0x0 +#define GC_TEMP_ADC_CONFIG_OFFSET 0x40 +#define GC_TEMP_ADC_CONFIG_DEFAULT 0x0 +#define GC_TEMP_ABS_LIMIT_OFFSET 0x44 +#define GC_TEMP_ABS_LIMIT_DEFAULT 0x0 +#define GC_TEMP_DIFF_PARAM_OFFSET 0x48 +#define GC_TEMP_DIFF_PARAM_DEFAULT 0x0 +#define GC_TEMP_METRIC_OFFSET 0x4c +#define GC_TEMP_METRIC_DEFAULT 0x0 +#define GC_TEMP_SAMPLE_CTR_STATE_OFFSET 0x50 +#define GC_TEMP_SAMPLE_CTR_STATE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1LOAD_OFFSET 0x0 +#define GC_TIMEHS_TIMER1LOAD_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1VALUE_OFFSET 0x4 +#define GC_TIMEHS_TIMER1VALUE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1CONTROL_OFFSET 0x8 +#define GC_TIMEHS_TIMER1CONTROL_DEFAULT 0x20 +#define GC_TIMEHS_TIMER1INTCLR_OFFSET 0xc +#define GC_TIMEHS_TIMER1INTCLR_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1RIS_OFFSET 0x10 +#define GC_TIMEHS_TIMER1RIS_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1MIS_OFFSET 0x14 +#define GC_TIMEHS_TIMER1MIS_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1BGLOAD_OFFSET 0x18 +#define GC_TIMEHS_TIMER1BGLOAD_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2LOAD_OFFSET 0x20 +#define GC_TIMEHS_TIMER2LOAD_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2VALUE_OFFSET 0x24 +#define GC_TIMEHS_TIMER2VALUE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2CONTROL_OFFSET 0x28 +#define GC_TIMEHS_TIMER2CONTROL_DEFAULT 0x20 +#define GC_TIMEHS_TIMER2INTCLR_OFFSET 0x2c +#define GC_TIMEHS_TIMER2INTCLR_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2RIS_OFFSET 0x30 +#define GC_TIMEHS_TIMER2RIS_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2MIS_OFFSET 0x34 +#define GC_TIMEHS_TIMER2MIS_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2BGLOAD_OFFSET 0x38 +#define GC_TIMEHS_TIMER2BGLOAD_DEFAULT 0x0 +#define GC_TIMEHS_TIMERITCR_OFFSET 0xf00 +#define GC_TIMEHS_TIMERITCR_DEFAULT 0x0 +#define GC_TIMEHS_TIMERITOP_OFFSET 0xf04 +#define GC_TIMEHS_TIMERITOP_DEFAULT 0x0 +#define GC_TIMEHS_TIMERPERIPHID4_OFFSET 0xfd0 +#define GC_TIMEHS_TIMERPERIPHID4_DEFAULT 0x4 +#define GC_TIMEHS_TIMERPERIPHID5_OFFSET 0xfd4 +#define GC_TIMEHS_TIMERPERIPHID5_DEFAULT 0x0 +#define GC_TIMEHS_TIMERPERIPHID6_OFFSET 0xfd8 +#define GC_TIMEHS_TIMERPERIPHID6_DEFAULT 0x0 +#define GC_TIMEHS_TIMERPERIPHID7_OFFSET 0xfdc +#define GC_TIMEHS_TIMERPERIPHID7_DEFAULT 0x0 +#define GC_TIMEHS_TIMERPERIPHID0_OFFSET 0xfe0 +#define GC_TIMEHS_TIMERPERIPHID0_DEFAULT 0x23 +#define GC_TIMEHS_TIMERPERIPHID1_OFFSET 0xfe4 +#define GC_TIMEHS_TIMERPERIPHID1_DEFAULT 0xb8 +#define GC_TIMEHS_TIMERPERIPHID2_OFFSET 0xfe8 +#define GC_TIMEHS_TIMERPERIPHID2_DEFAULT 0xb +#define GC_TIMEHS_TIMERPERIPHID3_OFFSET 0xfec +#define GC_TIMEHS_TIMERPERIPHID3_DEFAULT 0x0 +#define GC_TIMEHS_TIMERPCELLID0_OFFSET 0xff0 +#define GC_TIMEHS_TIMERPCELLID0_DEFAULT 0xd +#define GC_TIMEHS_TIMERPCELLID1_OFFSET 0xff4 +#define GC_TIMEHS_TIMERPCELLID1_DEFAULT 0xf0 +#define GC_TIMEHS_TIMERPCELLID2_OFFSET 0xff8 +#define GC_TIMEHS_TIMERPCELLID2_DEFAULT 0x5 +#define GC_TIMEHS_TIMERPCELLID3_OFFSET 0xffc +#define GC_TIMEHS_TIMERPCELLID3_DEFAULT 0xb1 +#define GC_TIMELS_TIMER0_CONTROL_OFFSET 0x0 +#define GC_TIMELS_TIMER0_CONTROL_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STATUS_OFFSET 0x4 +#define GC_TIMELS_TIMER0_STATUS_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_LOAD_OFFSET 0x8 +#define GC_TIMELS_TIMER0_LOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_RELOADVAL_OFFSET 0xc +#define GC_TIMELS_TIMER0_RELOADVAL_DEFAULT 0xffffffff +#define GC_TIMELS_TIMER0_VALUE_OFFSET 0x10 +#define GC_TIMELS_TIMER0_VALUE_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STEP_OFFSET 0x14 +#define GC_TIMELS_TIMER0_STEP_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_IER_OFFSET 0x18 +#define GC_TIMELS_TIMER0_IER_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_ISR_OFFSET 0x1c +#define GC_TIMELS_TIMER0_ISR_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_IPR_OFFSET 0x20 +#define GC_TIMELS_TIMER0_IPR_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_IAR_OFFSET 0x24 +#define GC_TIMELS_TIMER0_IAR_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_SETHOLD_OFFSET 0x28 +#define GC_TIMELS_TIMER0_SETHOLD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_CLRHOLD_OFFSET 0x2c +#define GC_TIMELS_TIMER0_CLRHOLD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_CONTROL_OFFSET 0x40 +#define GC_TIMELS_TIMER1_CONTROL_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STATUS_OFFSET 0x44 +#define GC_TIMELS_TIMER1_STATUS_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_LOAD_OFFSET 0x48 +#define GC_TIMELS_TIMER1_LOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_RELOADVAL_OFFSET 0x4c +#define GC_TIMELS_TIMER1_RELOADVAL_DEFAULT 0xffffffff +#define GC_TIMELS_TIMER1_VALUE_OFFSET 0x50 +#define GC_TIMELS_TIMER1_VALUE_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STEP_OFFSET 0x54 +#define GC_TIMELS_TIMER1_STEP_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_IER_OFFSET 0x58 +#define GC_TIMELS_TIMER1_IER_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_ISR_OFFSET 0x5c +#define GC_TIMELS_TIMER1_ISR_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_IPR_OFFSET 0x60 +#define GC_TIMELS_TIMER1_IPR_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_IAR_OFFSET 0x64 +#define GC_TIMELS_TIMER1_IAR_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_SETHOLD_OFFSET 0x68 +#define GC_TIMELS_TIMER1_SETHOLD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_CLRHOLD_OFFSET 0x6c +#define GC_TIMELS_TIMER1_CLRHOLD_DEFAULT 0x0 +#define GC_TIMELS_ITCR_OFFSET 0xf00 +#define GC_TIMELS_ITCR_DEFAULT 0x0 +#define GC_TIMELS_ITOP_OFFSET 0xf04 +#define GC_TIMELS_ITOP_DEFAULT 0x0 +#define GC_TRNG_VERSION_OFFSET 0x0 +#define GC_TRNG_VERSION_DEFAULT 0x700c241 +#define GC_TRNG_INT_ENABLE_OFFSET 0x4 +#define GC_TRNG_INT_ENABLE_DEFAULT 0x0 +#define GC_TRNG_INT_STATE_OFFSET 0x8 +#define GC_TRNG_INT_STATE_DEFAULT 0x0 +#define GC_TRNG_INT_TEST_OFFSET 0xc +#define GC_TRNG_INT_TEST_DEFAULT 0x0 +#define GC_TRNG_GO_EVENT_OFFSET 0x10 +#define GC_TRNG_GO_EVENT_DEFAULT 0x0 +#define GC_TRNG_TIMEOUT_COUNTER_OFFSET 0x14 +#define GC_TRNG_TIMEOUT_COUNTER_DEFAULT 0x2710 +#define GC_TRNG_TIMEOUT_MAX_TRY_NUM_OFFSET 0x18 +#define GC_TRNG_TIMEOUT_MAX_TRY_NUM_DEFAULT 0x4 +#define GC_TRNG_CAPTURE_FOR_CALIBRATION_NUM_ENTRIES_OFFSET 0x1c +#define GC_TRNG_CAPTURE_FOR_CALIBRATION_NUM_ENTRIES_DEFAULT 0x7 +#define GC_TRNG_STOP_WORK_OFFSET 0x20 +#define GC_TRNG_STOP_WORK_DEFAULT 0x0 +#define GC_TRNG_TAIL_POINTER_OFFSET 0x24 +#define GC_TRNG_TAIL_POINTER_DEFAULT 0x0 +#define GC_TRNG_SLICE_MAX_LIMIT_OFFSET 0x28 +#define GC_TRNG_SLICE_MAX_LIMIT_DEFAULT 0xf0 +#define GC_TRNG_HEAD_POINTER_OFFSET 0x2c +#define GC_TRNG_HEAD_POINTER_DEFAULT 0x0 +#define GC_TRNG_SYNC_ANALOG_OFFSET 0x30 +#define GC_TRNG_SYNC_ANALOG_DEFAULT 0x0 +#define GC_TRNG_MODE_OPERATION_OFFSET 0x34 +#define GC_TRNG_MODE_OPERATION_DEFAULT 0x0 +#define GC_TRNG_FSM_STATE_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_DEFAULT 0x1 +#define GC_TRNG_TIMER_COUNTER_OFFSET 0x3c +#define GC_TRNG_TIMER_COUNTER_DEFAULT 0x0 +#define GC_TRNG_SLICE_RANGE_OFFSET 0x40 +#define GC_TRNG_SLICE_RANGE_DEFAULT 0xf0 +#define GC_TRNG_AVERAGE_OFFSET 0x44 +#define GC_TRNG_AVERAGE_DEFAULT 0x0 +#define GC_TRNG_STD_DEV_OFFSET 0x48 +#define GC_TRNG_STD_DEV_DEFAULT 0x0 +#define GC_TRNG_INLINE_STATS_OFFSET 0x4c +#define GC_TRNG_INLINE_STATS_DEFAULT 0x0 +#define GC_TRNG_LDO_CTRL_OFFSET 0x50 +#define GC_TRNG_LDO_CTRL_DEFAULT 0xb +#define GC_TRNG_DIV_EN_OFFSET 0x54 +#define GC_TRNG_DIV_EN_DEFAULT 0x0 +#define GC_TRNG_ONE_SHOT_MODE_OFFSET 0x58 +#define GC_TRNG_ONE_SHOT_MODE_DEFAULT 0x0 +#define GC_TRNG_ONE_SHOT_REG_OFFSET 0x5c +#define GC_TRNG_ONE_SHOT_REG_DEFAULT 0x0 +#define GC_TRNG_REG_BITS0_OFFSET 0x100 +#define GC_TRNG_REG_BITS0_DEFAULT 0x0 +#define GC_TRNG_REG_BITS1_OFFSET 0x104 +#define GC_TRNG_REG_BITS1_DEFAULT 0x0 +#define GC_TRNG_REG_BITS2_OFFSET 0x108 +#define GC_TRNG_REG_BITS2_DEFAULT 0x0 +#define GC_TRNG_REG_BITS3_OFFSET 0x10c +#define GC_TRNG_REG_BITS3_DEFAULT 0x0 +#define GC_TRNG_REG_BITS4_OFFSET 0x110 +#define GC_TRNG_REG_BITS4_DEFAULT 0x0 +#define GC_TRNG_REG_BITS5_OFFSET 0x114 +#define GC_TRNG_REG_BITS5_DEFAULT 0x0 +#define GC_TRNG_REG_BITS6_OFFSET 0x118 +#define GC_TRNG_REG_BITS6_DEFAULT 0x0 +#define GC_TRNG_REG_BITS7_OFFSET 0x11c +#define GC_TRNG_REG_BITS7_DEFAULT 0x0 +#define GC_TRNG_REG_BITS8_OFFSET 0x120 +#define GC_TRNG_REG_BITS8_DEFAULT 0x0 +#define GC_TRNG_REG_BITS9_OFFSET 0x124 +#define GC_TRNG_REG_BITS9_DEFAULT 0x0 +#define GC_TRNG_REG_BITS10_OFFSET 0x128 +#define GC_TRNG_REG_BITS10_DEFAULT 0x0 +#define GC_TRNG_REG_BITS11_OFFSET 0x12c +#define GC_TRNG_REG_BITS11_DEFAULT 0x0 +#define GC_TRNG_REG_BITS12_OFFSET 0x130 +#define GC_TRNG_REG_BITS12_DEFAULT 0x0 +#define GC_TRNG_REG_BITS13_OFFSET 0x134 +#define GC_TRNG_REG_BITS13_DEFAULT 0x0 +#define GC_TRNG_REG_BITS14_OFFSET 0x138 +#define GC_TRNG_REG_BITS14_DEFAULT 0x0 +#define GC_TRNG_REG_BITS15_OFFSET 0x13c +#define GC_TRNG_REG_BITS15_DEFAULT 0x0 +#define GC_TRNG_REG_BITS16_OFFSET 0x140 +#define GC_TRNG_REG_BITS16_DEFAULT 0x0 +#define GC_TRNG_REG_BITS17_OFFSET 0x144 +#define GC_TRNG_REG_BITS17_DEFAULT 0x0 +#define GC_TRNG_REG_BITS18_OFFSET 0x148 +#define GC_TRNG_REG_BITS18_DEFAULT 0x0 +#define GC_TRNG_REG_BITS19_OFFSET 0x14c +#define GC_TRNG_REG_BITS19_DEFAULT 0x0 +#define GC_TRNG_REG_BITS20_OFFSET 0x150 +#define GC_TRNG_REG_BITS20_DEFAULT 0x0 +#define GC_TRNG_REG_BITS21_OFFSET 0x154 +#define GC_TRNG_REG_BITS21_DEFAULT 0x0 +#define GC_TRNG_REG_BITS22_OFFSET 0x158 +#define GC_TRNG_REG_BITS22_DEFAULT 0x0 +#define GC_TRNG_REG_BITS23_OFFSET 0x15c +#define GC_TRNG_REG_BITS23_DEFAULT 0x0 +#define GC_TRNG_REG_BITS24_OFFSET 0x160 +#define GC_TRNG_REG_BITS24_DEFAULT 0x0 +#define GC_TRNG_REG_BITS25_OFFSET 0x164 +#define GC_TRNG_REG_BITS25_DEFAULT 0x0 +#define GC_TRNG_REG_BITS26_OFFSET 0x168 +#define GC_TRNG_REG_BITS26_DEFAULT 0x0 +#define GC_TRNG_REG_BITS27_OFFSET 0x16c +#define GC_TRNG_REG_BITS27_DEFAULT 0x0 +#define GC_TRNG_REG_BITS28_OFFSET 0x170 +#define GC_TRNG_REG_BITS28_DEFAULT 0x0 +#define GC_TRNG_REG_BITS29_OFFSET 0x174 +#define GC_TRNG_REG_BITS29_DEFAULT 0x0 +#define GC_TRNG_REG_BITS30_OFFSET 0x178 +#define GC_TRNG_REG_BITS30_DEFAULT 0x0 +#define GC_TRNG_REG_BITS31_OFFSET 0x17c +#define GC_TRNG_REG_BITS31_DEFAULT 0x0 +#define GC_TRNG_REG_BITS32_OFFSET 0x180 +#define GC_TRNG_REG_BITS32_DEFAULT 0x0 +#define GC_TRNG_REG_BITS33_OFFSET 0x184 +#define GC_TRNG_REG_BITS33_DEFAULT 0x0 +#define GC_TRNG_REG_BITS34_OFFSET 0x188 +#define GC_TRNG_REG_BITS34_DEFAULT 0x0 +#define GC_TRNG_REG_BITS35_OFFSET 0x18c +#define GC_TRNG_REG_BITS35_DEFAULT 0x0 +#define GC_TRNG_REG_BITS36_OFFSET 0x190 +#define GC_TRNG_REG_BITS36_DEFAULT 0x0 +#define GC_TRNG_REG_BITS37_OFFSET 0x194 +#define GC_TRNG_REG_BITS37_DEFAULT 0x0 +#define GC_TRNG_REG_BITS38_OFFSET 0x198 +#define GC_TRNG_REG_BITS38_DEFAULT 0x0 +#define GC_TRNG_REG_BITS39_OFFSET 0x19c +#define GC_TRNG_REG_BITS39_DEFAULT 0x0 +#define GC_TRNG_REG_BITS40_OFFSET 0x1a0 +#define GC_TRNG_REG_BITS40_DEFAULT 0x0 +#define GC_TRNG_REG_BITS41_OFFSET 0x1a4 +#define GC_TRNG_REG_BITS41_DEFAULT 0x0 +#define GC_TRNG_REG_BITS42_OFFSET 0x1a8 +#define GC_TRNG_REG_BITS42_DEFAULT 0x0 +#define GC_TRNG_REG_BITS43_OFFSET 0x1ac +#define GC_TRNG_REG_BITS43_DEFAULT 0x0 +#define GC_TRNG_REG_BITS44_OFFSET 0x1b0 +#define GC_TRNG_REG_BITS44_DEFAULT 0x0 +#define GC_TRNG_REG_BITS45_OFFSET 0x1b4 +#define GC_TRNG_REG_BITS45_DEFAULT 0x0 +#define GC_TRNG_REG_BITS46_OFFSET 0x1b8 +#define GC_TRNG_REG_BITS46_DEFAULT 0x0 +#define GC_TRNG_REG_BITS47_OFFSET 0x1bc +#define GC_TRNG_REG_BITS47_DEFAULT 0x0 +#define GC_TRNG_REG_BITS48_OFFSET 0x1c0 +#define GC_TRNG_REG_BITS48_DEFAULT 0x0 +#define GC_TRNG_REG_BITS49_OFFSET 0x1c4 +#define GC_TRNG_REG_BITS49_DEFAULT 0x0 +#define GC_TRNG_REG_BITS50_OFFSET 0x1c8 +#define GC_TRNG_REG_BITS50_DEFAULT 0x0 +#define GC_TRNG_REG_BITS51_OFFSET 0x1cc +#define GC_TRNG_REG_BITS51_DEFAULT 0x0 +#define GC_TRNG_REG_BITS52_OFFSET 0x1d0 +#define GC_TRNG_REG_BITS52_DEFAULT 0x0 +#define GC_TRNG_REG_BITS53_OFFSET 0x1d4 +#define GC_TRNG_REG_BITS53_DEFAULT 0x0 +#define GC_TRNG_REG_BITS54_OFFSET 0x1d8 +#define GC_TRNG_REG_BITS54_DEFAULT 0x0 +#define GC_TRNG_REG_BITS55_OFFSET 0x1dc +#define GC_TRNG_REG_BITS55_DEFAULT 0x0 +#define GC_TRNG_REG_BITS56_OFFSET 0x1e0 +#define GC_TRNG_REG_BITS56_DEFAULT 0x0 +#define GC_TRNG_REG_BITS57_OFFSET 0x1e4 +#define GC_TRNG_REG_BITS57_DEFAULT 0x0 +#define GC_TRNG_REG_BITS58_OFFSET 0x1e8 +#define GC_TRNG_REG_BITS58_DEFAULT 0x0 +#define GC_TRNG_REG_BITS59_OFFSET 0x1ec +#define GC_TRNG_REG_BITS59_DEFAULT 0x0 +#define GC_TRNG_REG_BITS60_OFFSET 0x1f0 +#define GC_TRNG_REG_BITS60_DEFAULT 0x0 +#define GC_TRNG_REG_BITS61_OFFSET 0x1f4 +#define GC_TRNG_REG_BITS61_DEFAULT 0x0 +#define GC_TRNG_REG_BITS62_OFFSET 0x1f8 +#define GC_TRNG_REG_BITS62_DEFAULT 0x0 +#define GC_TRNG_REG_BITS63_OFFSET 0x1fc +#define GC_TRNG_REG_BITS63_DEFAULT 0x0 +#define GC_UART_RDATA_OFFSET 0x0 +#define GC_UART_RDATA_DEFAULT 0x0 +#define GC_UART_WDATA_OFFSET 0x4 +#define GC_UART_WDATA_DEFAULT 0x0 +#define GC_UART_NCO_OFFSET 0x8 +#define GC_UART_NCO_DEFAULT 0x0 +#define GC_UART_CTRL_OFFSET 0xc +#define GC_UART_CTRL_DEFAULT 0x0 +#define GC_UART_ICTRL_OFFSET 0x10 +#define GC_UART_ICTRL_DEFAULT 0x0 +#define GC_UART_STATE_OFFSET 0x14 +#define GC_UART_STATE_DEFAULT 0x90 +#define GC_UART_STATECLR_OFFSET 0x18 +#define GC_UART_STATECLR_DEFAULT 0x0 +#define GC_UART_ISTATE_OFFSET 0x1c +#define GC_UART_ISTATE_DEFAULT 0x0 +#define GC_UART_ISTATECLR_OFFSET 0x20 +#define GC_UART_ISTATECLR_DEFAULT 0x0 +#define GC_UART_FIFO_OFFSET 0x24 +#define GC_UART_FIFO_DEFAULT 0x0 +#define GC_UART_RFIFO_OFFSET 0x28 +#define GC_UART_RFIFO_DEFAULT 0x0 +#define GC_UART_OVRD_OFFSET 0x2c +#define GC_UART_OVRD_DEFAULT 0x0 +#define GC_UART_VAL_OFFSET 0x30 +#define GC_UART_VAL_DEFAULT 0x0 +#define GC_UART_RXTO_OFFSET 0x34 +#define GC_UART_RXTO_DEFAULT 0x0 +#define GC_UART_ITCR_OFFSET 0xf00 +#define GC_UART_ITCR_DEFAULT 0x0 +#define GC_UART_ITOP_OFFSET 0xf04 +#define GC_UART_ITOP_DEFAULT 0x0 +#define GC_USB_GOTGCTL_OFFSET 0x0 +#define GC_USB_GOTGCTL_DEFAULT 0x0 +#define GC_USB_GOTGINT_OFFSET 0x4 +#define GC_USB_GOTGINT_DEFAULT 0x0 +#define GC_USB_GAHBCFG_OFFSET 0x8 +#define GC_USB_GAHBCFG_DEFAULT 0x0 +#define GC_USB_GUSBCFG_OFFSET 0xc +#define GC_USB_GUSBCFG_DEFAULT 0x0 +#define GC_USB_GRSTCTL_OFFSET 0x10 +#define GC_USB_GRSTCTL_DEFAULT 0x0 +#define GC_USB_GINTSTS_OFFSET 0x14 +#define GC_USB_GINTSTS_DEFAULT 0x0 +#define GC_USB_GINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_DEFAULT 0x0 +#define GC_USB_GRXSTSR_OFFSET 0x1c +#define GC_USB_GRXSTSR_DEFAULT 0x0 +#define GC_USB_GRXSTSP_OFFSET 0x20 +#define GC_USB_GRXSTSP_DEFAULT 0x0 +#define GC_USB_GRXFSIZ_OFFSET 0x24 +#define GC_USB_GRXFSIZ_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_OFFSET 0x28 +#define GC_USB_GNPTXFSIZ_DEFAULT 0x0 +#define GC_USB_GGPIO_OFFSET 0x38 +#define GC_USB_GGPIO_DEFAULT 0x0 +#define GC_USB_GUID_OFFSET 0x3c +#define GC_USB_GUID_DEFAULT 0x0 +#define GC_USB_GSNPSID_OFFSET 0x40 +#define GC_USB_GSNPSID_DEFAULT 0x0 +#define GC_USB_GHWCFG1_OFFSET 0x44 +#define GC_USB_GHWCFG1_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OFFSET 0x48 +#define GC_USB_GHWCFG2_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OFFSET 0x4c +#define GC_USB_GHWCFG3_DEFAULT 0x0 +#define GC_USB_GHWCFG4_OFFSET 0x50 +#define GC_USB_GHWCFG4_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_OFFSET 0x5c +#define GC_USB_GDFIFOCFG_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_OFFSET 0x104 +#define GC_USB_DIEPTXF1_DEFAULT 0x0 +#define GC_USB_DIEPTXF2_OFFSET 0x108 +#define GC_USB_DIEPTXF2_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_OFFSET 0x10c +#define GC_USB_DIEPTXF3_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_OFFSET 0x110 +#define GC_USB_DIEPTXF4_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_OFFSET 0x114 +#define GC_USB_DIEPTXF5_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_OFFSET 0x118 +#define GC_USB_DIEPTXF6_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_OFFSET 0x11c +#define GC_USB_DIEPTXF7_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_OFFSET 0x120 +#define GC_USB_DIEPTXF8_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_OFFSET 0x124 +#define GC_USB_DIEPTXF9_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_OFFSET 0x128 +#define GC_USB_DIEPTXF10_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_OFFSET 0x12c +#define GC_USB_DIEPTXF11_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_OFFSET 0x130 +#define GC_USB_DIEPTXF12_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_OFFSET 0x134 +#define GC_USB_DIEPTXF13_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_OFFSET 0x138 +#define GC_USB_DIEPTXF14_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_OFFSET 0x13c +#define GC_USB_DIEPTXF15_DEFAULT 0x0 +#define GC_USB_DCFG_OFFSET 0x800 +#define GC_USB_DCFG_DEFAULT 0x8000000 +#define GC_USB_DCTL_OFFSET 0x804 +#define GC_USB_DCTL_DEFAULT 0x0 +#define GC_USB_DSTS_OFFSET 0x808 +#define GC_USB_DSTS_DEFAULT 0x0 +#define GC_USB_DIEPMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_DEFAULT 0x0 +#define GC_USB_DAINT_OFFSET 0x818 +#define GC_USB_DAINT_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OFFSET 0x81c +#define GC_USB_DAINTMSK_DEFAULT 0x0 +#define GC_USB_DVBUSDIS_OFFSET 0x828 +#define GC_USB_DVBUSDIS_DEFAULT 0x0 +#define GC_USB_DVBUSPULSE_OFFSET 0x82c +#define GC_USB_DVBUSPULSE_DEFAULT 0x0 +#define GC_USB_DTHRCTL_OFFSET 0x830 +#define GC_USB_DTHRCTL_DEFAULT 0x0 +#define GC_USB_DIEPEMPMSK_OFFSET 0x834 +#define GC_USB_DIEPEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_OFFSET 0x900 +#define GC_USB_DIEPCTL0_DEFAULT 0x0 +#define GC_USB_DIEPINT0_OFFSET 0x908 +#define GC_USB_DIEPINT0_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_OFFSET 0x910 +#define GC_USB_DIEPTSIZ0_DEFAULT 0x0 +#define GC_USB_DIEPDMA0_OFFSET 0x914 +#define GC_USB_DIEPDMA0_DEFAULT 0x0 +#define GC_USB_DTXFSTS0_OFFSET 0x918 +#define GC_USB_DTXFSTS0_DEFAULT 0x0 +#define GC_USB_DIEPDMAB0_OFFSET 0x91c +#define GC_USB_DIEPDMAB0_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_OFFSET 0x920 +#define GC_USB_DIEPCTL1_DEFAULT 0x0 +#define GC_USB_DIEPINT1_OFFSET 0x928 +#define GC_USB_DIEPINT1_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_DEFAULT 0x0 +#define GC_USB_DIEPDMA1_OFFSET 0x934 +#define GC_USB_DIEPDMA1_DEFAULT 0x0 +#define GC_USB_DTXFSTS1_OFFSET 0x938 +#define GC_USB_DTXFSTS1_DEFAULT 0x0 +#define GC_USB_DIEPDMAB1_OFFSET 0x93c +#define GC_USB_DIEPDMAB1_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_OFFSET 0x940 +#define GC_USB_DIEPCTL2_DEFAULT 0x0 +#define GC_USB_DIEPINT2_OFFSET 0x948 +#define GC_USB_DIEPINT2_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_DEFAULT 0x0 +#define GC_USB_DIEPDMA2_OFFSET 0x954 +#define GC_USB_DIEPDMA2_DEFAULT 0x0 +#define GC_USB_DTXFSTS2_OFFSET 0x958 +#define GC_USB_DTXFSTS2_DEFAULT 0x0 +#define GC_USB_DIEPDMAB2_OFFSET 0x95c +#define GC_USB_DIEPDMAB2_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_OFFSET 0x960 +#define GC_USB_DIEPCTL3_DEFAULT 0x0 +#define GC_USB_DIEPINT3_OFFSET 0x968 +#define GC_USB_DIEPINT3_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_DEFAULT 0x0 +#define GC_USB_DIEPDMA3_OFFSET 0x974 +#define GC_USB_DIEPDMA3_DEFAULT 0x0 +#define GC_USB_DTXFSTS3_OFFSET 0x978 +#define GC_USB_DTXFSTS3_DEFAULT 0x0 +#define GC_USB_DIEPDMAB3_OFFSET 0x97c +#define GC_USB_DIEPDMAB3_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_OFFSET 0x980 +#define GC_USB_DIEPCTL4_DEFAULT 0x0 +#define GC_USB_DIEPINT4_OFFSET 0x988 +#define GC_USB_DIEPINT4_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_DEFAULT 0x0 +#define GC_USB_DIEPDMA4_OFFSET 0x994 +#define GC_USB_DIEPDMA4_DEFAULT 0x0 +#define GC_USB_DTXFSTS4_OFFSET 0x998 +#define GC_USB_DTXFSTS4_DEFAULT 0x0 +#define GC_USB_DIEPDMAB4_OFFSET 0x99c +#define GC_USB_DIEPDMAB4_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_DEFAULT 0x0 +#define GC_USB_DIEPINT5_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_DEFAULT 0x0 +#define GC_USB_DIEPDMA5_OFFSET 0x9b4 +#define GC_USB_DIEPDMA5_DEFAULT 0x0 +#define GC_USB_DTXFSTS5_OFFSET 0x9b8 +#define GC_USB_DTXFSTS5_DEFAULT 0x0 +#define GC_USB_DIEPDMAB5_OFFSET 0x9bc +#define GC_USB_DIEPDMAB5_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_DEFAULT 0x0 +#define GC_USB_DIEPINT6_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_DEFAULT 0x0 +#define GC_USB_DIEPDMA6_OFFSET 0x9d4 +#define GC_USB_DIEPDMA6_DEFAULT 0x0 +#define GC_USB_DTXFSTS6_OFFSET 0x9d8 +#define GC_USB_DTXFSTS6_DEFAULT 0x0 +#define GC_USB_DIEPDMAB6_OFFSET 0x9dc +#define GC_USB_DIEPDMAB6_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_DEFAULT 0x0 +#define GC_USB_DIEPINT7_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_DEFAULT 0x0 +#define GC_USB_DIEPDMA7_OFFSET 0x9f4 +#define GC_USB_DIEPDMA7_DEFAULT 0x0 +#define GC_USB_DTXFSTS7_OFFSET 0x9f8 +#define GC_USB_DTXFSTS7_DEFAULT 0x0 +#define GC_USB_DIEPDMAB7_OFFSET 0x9fc +#define GC_USB_DIEPDMAB7_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_DEFAULT 0x0 +#define GC_USB_DIEPINT8_OFFSET 0xa08 +#define GC_USB_DIEPINT8_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_DEFAULT 0x0 +#define GC_USB_DIEPDMA8_OFFSET 0xa14 +#define GC_USB_DIEPDMA8_DEFAULT 0x0 +#define GC_USB_DTXFSTS8_OFFSET 0xa18 +#define GC_USB_DTXFSTS8_DEFAULT 0x0 +#define GC_USB_DIEPDMAB8_OFFSET 0xa1c +#define GC_USB_DIEPDMAB8_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_DEFAULT 0x0 +#define GC_USB_DIEPINT9_OFFSET 0xa28 +#define GC_USB_DIEPINT9_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_DEFAULT 0x0 +#define GC_USB_DIEPDMA9_OFFSET 0xa34 +#define GC_USB_DIEPDMA9_DEFAULT 0x0 +#define GC_USB_DTXFSTS9_OFFSET 0xa38 +#define GC_USB_DTXFSTS9_DEFAULT 0x0 +#define GC_USB_DIEPDMAB9_OFFSET 0xa3c +#define GC_USB_DIEPDMAB9_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_DEFAULT 0x0 +#define GC_USB_DIEPINT10_OFFSET 0xa48 +#define GC_USB_DIEPINT10_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_DEFAULT 0x0 +#define GC_USB_DIEPDMA10_OFFSET 0xa54 +#define GC_USB_DIEPDMA10_DEFAULT 0x0 +#define GC_USB_DTXFSTS10_OFFSET 0xa58 +#define GC_USB_DTXFSTS10_DEFAULT 0x0 +#define GC_USB_DIEPDMAB10_OFFSET 0xa5c +#define GC_USB_DIEPDMAB10_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_DEFAULT 0x0 +#define GC_USB_DIEPINT11_OFFSET 0xa68 +#define GC_USB_DIEPINT11_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_DEFAULT 0x0 +#define GC_USB_DIEPDMA11_OFFSET 0xa74 +#define GC_USB_DIEPDMA11_DEFAULT 0x0 +#define GC_USB_DTXFSTS11_OFFSET 0xa78 +#define GC_USB_DTXFSTS11_DEFAULT 0x0 +#define GC_USB_DIEPDMAB11_OFFSET 0xa7c +#define GC_USB_DIEPDMAB11_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_DEFAULT 0x0 +#define GC_USB_DIEPINT12_OFFSET 0xa88 +#define GC_USB_DIEPINT12_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_DEFAULT 0x0 +#define GC_USB_DIEPDMA12_OFFSET 0xa94 +#define GC_USB_DIEPDMA12_DEFAULT 0x0 +#define GC_USB_DTXFSTS12_OFFSET 0xa98 +#define GC_USB_DTXFSTS12_DEFAULT 0x0 +#define GC_USB_DIEPDMAB12_OFFSET 0xa9c +#define GC_USB_DIEPDMAB12_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_DEFAULT 0x0 +#define GC_USB_DIEPINT13_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_DEFAULT 0x0 +#define GC_USB_DIEPDMA13_OFFSET 0xab4 +#define GC_USB_DIEPDMA13_DEFAULT 0x0 +#define GC_USB_DTXFSTS13_OFFSET 0xab8 +#define GC_USB_DTXFSTS13_DEFAULT 0x0 +#define GC_USB_DIEPDMAB13_OFFSET 0xabc +#define GC_USB_DIEPDMAB13_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_DEFAULT 0x0 +#define GC_USB_DIEPINT14_OFFSET 0xac8 +#define GC_USB_DIEPINT14_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_DEFAULT 0x0 +#define GC_USB_DIEPDMA14_OFFSET 0xad4 +#define GC_USB_DIEPDMA14_DEFAULT 0x0 +#define GC_USB_DTXFSTS14_OFFSET 0xad8 +#define GC_USB_DTXFSTS14_DEFAULT 0x0 +#define GC_USB_DIEPDMAB14_OFFSET 0xadc +#define GC_USB_DIEPDMAB14_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_DEFAULT 0x0 +#define GC_USB_DIEPINT15_OFFSET 0xae8 +#define GC_USB_DIEPINT15_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_DEFAULT 0x0 +#define GC_USB_DIEPDMA15_OFFSET 0xaf4 +#define GC_USB_DIEPDMA15_DEFAULT 0x0 +#define GC_USB_DTXFSTS15_OFFSET 0xaf8 +#define GC_USB_DTXFSTS15_DEFAULT 0x0 +#define GC_USB_DIEPDMAB15_OFFSET 0xafc +#define GC_USB_DIEPDMAB15_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OFFSET 0xb08 +#define GC_USB_DOEPINT0_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_DEFAULT 0x0 +#define GC_USB_DOEPDMA0_OFFSET 0xb14 +#define GC_USB_DOEPDMA0_DEFAULT 0x0 +#define GC_USB_DOEPDMAB0_OFFSET 0xb1c +#define GC_USB_DOEPDMAB0_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OFFSET 0xb28 +#define GC_USB_DOEPINT1_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_DEFAULT 0x0 +#define GC_USB_DOEPDMA1_OFFSET 0xb34 +#define GC_USB_DOEPDMA1_DEFAULT 0x0 +#define GC_USB_DOEPDMAB1_OFFSET 0xb3c +#define GC_USB_DOEPDMAB1_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OFFSET 0xb48 +#define GC_USB_DOEPINT2_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_DEFAULT 0x0 +#define GC_USB_DOEPDMA2_OFFSET 0xb54 +#define GC_USB_DOEPDMA2_DEFAULT 0x0 +#define GC_USB_DOEPDMAB2_OFFSET 0xb5c +#define GC_USB_DOEPDMAB2_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OFFSET 0xb68 +#define GC_USB_DOEPINT3_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_DEFAULT 0x0 +#define GC_USB_DOEPDMA3_OFFSET 0xb74 +#define GC_USB_DOEPDMA3_DEFAULT 0x0 +#define GC_USB_DOEPDMAB3_OFFSET 0xb7c +#define GC_USB_DOEPDMAB3_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OFFSET 0xb88 +#define GC_USB_DOEPINT4_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_DEFAULT 0x0 +#define GC_USB_DOEPDMA4_OFFSET 0xb94 +#define GC_USB_DOEPDMA4_DEFAULT 0x0 +#define GC_USB_DOEPDMAB4_OFFSET 0xb9c +#define GC_USB_DOEPDMAB4_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OFFSET 0xba8 +#define GC_USB_DOEPINT5_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_DEFAULT 0x0 +#define GC_USB_DOEPDMA5_OFFSET 0xbb4 +#define GC_USB_DOEPDMA5_DEFAULT 0x0 +#define GC_USB_DOEPDMAB5_OFFSET 0xbbc +#define GC_USB_DOEPDMAB5_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_DEFAULT 0x0 +#define GC_USB_DOEPDMA6_OFFSET 0xbd4 +#define GC_USB_DOEPDMA6_DEFAULT 0x0 +#define GC_USB_DOEPDMAB6_OFFSET 0xbdc +#define GC_USB_DOEPDMAB6_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_DEFAULT 0x0 +#define GC_USB_DOEPDMA7_OFFSET 0xbf4 +#define GC_USB_DOEPDMA7_DEFAULT 0x0 +#define GC_USB_DOEPDMAB7_OFFSET 0xbfc +#define GC_USB_DOEPDMAB7_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OFFSET 0xc08 +#define GC_USB_DOEPINT8_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_DEFAULT 0x0 +#define GC_USB_DOEPDMA8_OFFSET 0xc14 +#define GC_USB_DOEPDMA8_DEFAULT 0x0 +#define GC_USB_DOEPDMAB8_OFFSET 0xc1c +#define GC_USB_DOEPDMAB8_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OFFSET 0xc28 +#define GC_USB_DOEPINT9_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_DEFAULT 0x0 +#define GC_USB_DOEPDMA9_OFFSET 0xc34 +#define GC_USB_DOEPDMA9_DEFAULT 0x0 +#define GC_USB_DOEPDMAB9_OFFSET 0xc3c +#define GC_USB_DOEPDMAB9_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OFFSET 0xc48 +#define GC_USB_DOEPINT10_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_DEFAULT 0x0 +#define GC_USB_DOEPDMA10_OFFSET 0xc54 +#define GC_USB_DOEPDMA10_DEFAULT 0x0 +#define GC_USB_DOEPDMAB10_OFFSET 0xc5c +#define GC_USB_DOEPDMAB10_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OFFSET 0xc68 +#define GC_USB_DOEPINT11_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_DEFAULT 0x0 +#define GC_USB_DOEPDMA11_OFFSET 0xc74 +#define GC_USB_DOEPDMA11_DEFAULT 0x0 +#define GC_USB_DOEPDMAB11_OFFSET 0xc7c +#define GC_USB_DOEPDMAB11_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OFFSET 0xc88 +#define GC_USB_DOEPINT12_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_DEFAULT 0x0 +#define GC_USB_DOEPDMA12_OFFSET 0xc94 +#define GC_USB_DOEPDMA12_DEFAULT 0x0 +#define GC_USB_DOEPDMAB12_OFFSET 0xc9c +#define GC_USB_DOEPDMAB12_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OFFSET 0xca8 +#define GC_USB_DOEPINT13_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_DEFAULT 0x0 +#define GC_USB_DOEPDMA13_OFFSET 0xcb4 +#define GC_USB_DOEPDMA13_DEFAULT 0x0 +#define GC_USB_DOEPDMAB13_OFFSET 0xcbc +#define GC_USB_DOEPDMAB13_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_DEFAULT 0x0 +#define GC_USB_DOEPDMA14_OFFSET 0xcd4 +#define GC_USB_DOEPDMA14_DEFAULT 0x0 +#define GC_USB_DOEPDMAB14_OFFSET 0xcdc +#define GC_USB_DOEPDMAB14_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OFFSET 0xce8 +#define GC_USB_DOEPINT15_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_DEFAULT 0x0 +#define GC_USB_DOEPDMA15_OFFSET 0xcf4 +#define GC_USB_DOEPDMA15_DEFAULT 0x0 +#define GC_USB_DOEPDMAB15_OFFSET 0xcfc +#define GC_USB_DOEPDMAB15_DEFAULT 0x0 +#define GC_USB_DFIFO_PP0_OFFSET 0x1000 +#define GC_USB_DFIFO_PP1_OFFSET 0x2000 +#define GC_USB_DFIFO_PP2_OFFSET 0x3000 +#define GC_USB_DFIFO_PP3_OFFSET 0x4000 +#define GC_USB_DFIFO_PP4_OFFSET 0x5000 +#define GC_USB_DFIFO_PP5_OFFSET 0x6000 +#define GC_USB_DFIFO_PP6_OFFSET 0x7000 +#define GC_USB_DFIFO_PP7_OFFSET 0x8000 +#define GC_USB_DFIFO_PP8_OFFSET 0x9000 +#define GC_USB_DFIFO_PP9_OFFSET 0xa000 +#define GC_USB_DFIFO_PP10_OFFSET 0xb000 +#define GC_USB_DFIFO_PP11_OFFSET 0xc000 +#define GC_USB_DFIFO_PP12_OFFSET 0xd000 +#define GC_USB_DFIFO_PP13_OFFSET 0xe000 +#define GC_USB_DFIFO_PP14_OFFSET 0xf000 +#define GC_USB_DFIFO_PP15_OFFSET 0x10000 +#define GC_USB_DFIFO_OFFSET 0x20000 +#define GC_WATCHDOG_WDOGLOAD_OFFSET 0x0 +#define GC_WATCHDOG_WDOGLOAD_DEFAULT 0xffffffff +#define GC_WATCHDOG_WDOGVALUE_OFFSET 0x4 +#define GC_WATCHDOG_WDOGVALUE_DEFAULT 0xffffffff +#define GC_WATCHDOG_WDOGCONTROL_OFFSET 0x8 +#define GC_WATCHDOG_WDOGCONTROL_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGINTCLR_OFFSET 0xc +#define GC_WATCHDOG_WDOGINTCLR_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGRIS_OFFSET 0x10 +#define GC_WATCHDOG_WDOGRIS_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGMIS_OFFSET 0x14 +#define GC_WATCHDOG_WDOGMIS_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGLOCK_OFFSET 0xc00 +#define GC_WATCHDOG_WDOGLOCK_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGITCR_OFFSET 0xf00 +#define GC_WATCHDOG_WDOGITCR_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGITOP_OFFSET 0xf04 +#define GC_WATCHDOG_WDOGITOP_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGPERIPHID4_OFFSET 0xfd0 +#define GC_WATCHDOG_WDOGPERIPHID4_DEFAULT 0x4 +#define GC_WATCHDOG_WDOGPERIPHID5_OFFSET 0xfd4 +#define GC_WATCHDOG_WDOGPERIPHID5_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGPERIPHID6_OFFSET 0xfd8 +#define GC_WATCHDOG_WDOGPERIPHID6_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGPERIPHID7_OFFSET 0xfdc +#define GC_WATCHDOG_WDOGPERIPHID7_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGPERIPHID0_OFFSET 0xfe0 +#define GC_WATCHDOG_WDOGPERIPHID0_DEFAULT 0x24 +#define GC_WATCHDOG_WDOGPERIPHID1_OFFSET 0xfe4 +#define GC_WATCHDOG_WDOGPERIPHID1_DEFAULT 0xb8 +#define GC_WATCHDOG_WDOGPERIPHID2_OFFSET 0xfe8 +#define GC_WATCHDOG_WDOGPERIPHID2_DEFAULT 0xb +#define GC_WATCHDOG_WDOGPERIPHID3_OFFSET 0xfec +#define GC_WATCHDOG_WDOGPERIPHID3_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGPCELLID0_OFFSET 0xff0 +#define GC_WATCHDOG_WDOGPCELLID0_DEFAULT 0xd +#define GC_WATCHDOG_WDOGPCELLID1_OFFSET 0xff4 +#define GC_WATCHDOG_WDOGPCELLID1_DEFAULT 0xf0 +#define GC_WATCHDOG_WDOGPCELLID2_OFFSET 0xff8 +#define GC_WATCHDOG_WDOGPCELLID2_DEFAULT 0x5 +#define GC_WATCHDOG_WDOGPCELLID3_OFFSET 0xffc +#define GC_WATCHDOG_WDOGPCELLID3_DEFAULT 0xb1 +#define GC_XO_OSC_CLKOUT_OFFSET 0x0 +#define GC_XO_OSC_CLKOUT_DEFAULT 0x0 +#define GC_XO_OSC_ADC_CAL_FREQ2X_OFFSET 0x4 +#define GC_XO_OSC_ADC_CAL_FREQ2X_DEFAULT 0x6 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_OFFSET 0x8 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_DEFAULT 0x6 +#define GC_XO_OSC_24_48B_SEL_OFFSET 0xc +#define GC_XO_OSC_24_48B_SEL_DEFAULT 0x0 +#define GC_XO_OSC_TEST_OFFSET 0x10 +#define GC_XO_OSC_TEST_DEFAULT 0x0 +#define GC_XO_OSC_RC_CAL_RSTB_OFFSET 0x14 +#define GC_XO_OSC_RC_CAL_RSTB_DEFAULT 0x1 +#define GC_XO_OSC_RC_CAL_LOAD_OFFSET 0x18 +#define GC_XO_OSC_RC_CAL_LOAD_DEFAULT 0x800 +#define GC_XO_OSC_RC_CAL_START_OFFSET 0x1c +#define GC_XO_OSC_RC_CAL_START_DEFAULT 0x0 +#define GC_XO_OSC_RC_CAL_DONE_OFFSET 0x20 +#define GC_XO_OSC_RC_CAL_DONE_DEFAULT 0x0 +#define GC_XO_OSC_RC_CAL_COUNT_OFFSET 0x24 +#define GC_XO_OSC_RC_CAL_COUNT_DEFAULT 0x0 +#define GC_XO_OSC_RC_OFFSET 0x28 +#define GC_XO_OSC_RC_DEFAULT 0x4444444 +#define GC_XO_OSC_RC_STATUS_OFFSET 0x2c +#define GC_XO_OSC_RC_STATUS_DEFAULT 0x4444444 +#define GC_XO_OSC_XTL_TRIMD_OFFSET 0x30 +#define GC_XO_OSC_XTL_TRIMD_DEFAULT 0x40 +#define GC_XO_OSC_XTL_TRIMG_OFFSET 0x34 +#define GC_XO_OSC_XTL_TRIMG_DEFAULT 0x40 +#define GC_XO_OSC_XTL_CTRL_OFFSET 0x38 +#define GC_XO_OSC_XTL_CTRL_DEFAULT 0x0 +#define GC_XO_OSC_XTL_RC_FLTR_OFFSET 0x3c +#define GC_XO_OSC_XTL_RC_FLTR_DEFAULT 0x15 +#define GC_XO_OSC_XTL_OVRD_OFFSET 0x40 +#define GC_XO_OSC_XTL_OVRD_DEFAULT 0x17 +#define GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET 0x44 +#define GC_XO_OSC_XTL_OVRD_HOLDB_DEFAULT 0x1 +#define GC_XO_OSC_XTL_TRIM_OFFSET 0x48 +#define GC_XO_OSC_XTL_TRIM_DEFAULT 0x0 +#define GC_XO_OSC_XTL_TRIM_STAT_OFFSET 0x4c +#define GC_XO_OSC_XTL_TRIM_STAT_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_EN_OFFSET 0x50 +#define GC_XO_OSC_XTL_FSM_EN_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_EN_KEY 0x60221413 +#define GC_XO_OSC_XTL_FSM_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_CFG_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_DEFAULT 0xd7488 +#define GC_XO_OSC_SETHOLD_OFFSET 0x5c +#define GC_XO_OSC_SETHOLD_DEFAULT 0x0 +#define GC_XO_OSC_CLRHOLD_OFFSET 0x60 +#define GC_XO_OSC_CLRHOLD_DEFAULT 0x0 +#define GC_M3_ITM_STIM0_OFFSET 0x0 +#define GC_M3_ITM_STIM0_DEFAULT 0x0 +#define GC_M3_ITM_STIM1_OFFSET 0x4 +#define GC_M3_ITM_STIM1_DEFAULT 0x0 +#define GC_M3_ITM_STIM2_OFFSET 0x8 +#define GC_M3_ITM_STIM2_DEFAULT 0x0 +#define GC_M3_ITM_STIM3_OFFSET 0xc +#define GC_M3_ITM_STIM3_DEFAULT 0x0 +#define GC_M3_ITM_STIM4_OFFSET 0x10 +#define GC_M3_ITM_STIM4_DEFAULT 0x0 +#define GC_M3_ITM_STIM5_OFFSET 0x14 +#define GC_M3_ITM_STIM5_DEFAULT 0x0 +#define GC_M3_ITM_STIM6_OFFSET 0x18 +#define GC_M3_ITM_STIM6_DEFAULT 0x0 +#define GC_M3_ITM_STIM7_OFFSET 0x1c +#define GC_M3_ITM_STIM7_DEFAULT 0x0 +#define GC_M3_ITM_STIM8_OFFSET 0x20 +#define GC_M3_ITM_STIM8_DEFAULT 0x0 +#define GC_M3_ITM_STIM9_OFFSET 0x24 +#define GC_M3_ITM_STIM9_DEFAULT 0x0 +#define GC_M3_ITM_STIM10_OFFSET 0x28 +#define GC_M3_ITM_STIM10_DEFAULT 0x0 +#define GC_M3_ITM_STIM11_OFFSET 0x2c +#define GC_M3_ITM_STIM11_DEFAULT 0x0 +#define GC_M3_ITM_STIM12_OFFSET 0x30 +#define GC_M3_ITM_STIM12_DEFAULT 0x0 +#define GC_M3_ITM_STIM13_OFFSET 0x34 +#define GC_M3_ITM_STIM13_DEFAULT 0x0 +#define GC_M3_ITM_STIM14_OFFSET 0x38 +#define GC_M3_ITM_STIM14_DEFAULT 0x0 +#define GC_M3_ITM_STIM15_OFFSET 0x3c +#define GC_M3_ITM_STIM15_DEFAULT 0x0 +#define GC_M3_ITM_STIM16_OFFSET 0x40 +#define GC_M3_ITM_STIM16_DEFAULT 0x0 +#define GC_M3_ITM_STIM17_OFFSET 0x44 +#define GC_M3_ITM_STIM17_DEFAULT 0x0 +#define GC_M3_ITM_STIM18_OFFSET 0x48 +#define GC_M3_ITM_STIM18_DEFAULT 0x0 +#define GC_M3_ITM_STIM19_OFFSET 0x4c +#define GC_M3_ITM_STIM19_DEFAULT 0x0 +#define GC_M3_ITM_STIM20_OFFSET 0x50 +#define GC_M3_ITM_STIM20_DEFAULT 0x0 +#define GC_M3_ITM_STIM21_OFFSET 0x54 +#define GC_M3_ITM_STIM21_DEFAULT 0x0 +#define GC_M3_ITM_STIM22_OFFSET 0x58 +#define GC_M3_ITM_STIM22_DEFAULT 0x0 +#define GC_M3_ITM_STIM23_OFFSET 0x5c +#define GC_M3_ITM_STIM23_DEFAULT 0x0 +#define GC_M3_ITM_STIM24_OFFSET 0x60 +#define GC_M3_ITM_STIM24_DEFAULT 0x0 +#define GC_M3_ITM_STIM25_OFFSET 0x64 +#define GC_M3_ITM_STIM25_DEFAULT 0x0 +#define GC_M3_ITM_STIM26_OFFSET 0x68 +#define GC_M3_ITM_STIM26_DEFAULT 0x0 +#define GC_M3_ITM_STIM27_OFFSET 0x6c +#define GC_M3_ITM_STIM27_DEFAULT 0x0 +#define GC_M3_ITM_STIM28_OFFSET 0x70 +#define GC_M3_ITM_STIM28_DEFAULT 0x0 +#define GC_M3_ITM_STIM29_OFFSET 0x74 +#define GC_M3_ITM_STIM29_DEFAULT 0x0 +#define GC_M3_ITM_STIM30_OFFSET 0x78 +#define GC_M3_ITM_STIM30_DEFAULT 0x0 +#define GC_M3_ITM_STIM31_OFFSET 0x7c +#define GC_M3_ITM_STIM31_DEFAULT 0x0 +#define GC_M3_ITM_TER_OFFSET 0xe00 +#define GC_M3_ITM_TER_DEFAULT 0x0 +#define GC_M3_ITM_TPR_OFFSET 0xe40 +#define GC_M3_ITM_TPR_DEFAULT 0x0 +#define GC_M3_ITM_TCR_OFFSET 0xe80 +#define GC_M3_ITM_TCR_DEFAULT 0x0 +#define GC_M3_ITM_INTRREG_OFFSET 0xef0 +#define GC_M3_ITM_INTRREG_DEFAULT 0x0 +#define GC_M3_ITM_INTWREG_OFFSET 0xef8 +#define GC_M3_ITM_INTWREG_DEFAULT 0x0 +#define GC_M3_ITM_INTMREG_OFFSET 0xf00 +#define GC_M3_ITM_INTMREG_DEFAULT 0x0 +#define GC_M3_ITM_LOCKCREG_OFFSET 0xfb0 +#define GC_M3_ITM_LOCKCREG_DEFAULT 0x0 +#define GC_M3_ITM_LOCKSREG_OFFSET 0xfb4 +#define GC_M3_ITM_LOCKSREG_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_DEFAULT 0x0 +#define GC_M3_DWT_CYCCNT_OFFSET 0x1004 +#define GC_M3_DWT_CYCCNT_DEFAULT 0x0 +#define GC_M3_DWT_CPICNT_OFFSET 0x1008 +#define GC_M3_DWT_CPICNT_DEFAULT 0x0 +#define GC_M3_DWT_EXCCNT_OFFSET 0x100c +#define GC_M3_DWT_EXCCNT_DEFAULT 0x0 +#define GC_M3_DWT_SLEEPCNT_OFFSET 0x1010 +#define GC_M3_DWT_SLEEPCNT_DEFAULT 0x0 +#define GC_M3_DWT_LSUCNT_OFFSET 0x1014 +#define GC_M3_DWT_LSUCNT_DEFAULT 0x0 +#define GC_M3_DWT_FOLDCNT_OFFSET 0x1018 +#define GC_M3_DWT_FOLDCNT_DEFAULT 0x0 +#define GC_M3_DWT_PCSR_OFFSET 0x101c +#define GC_M3_DWT_PCSR_DEFAULT 0x0 +#define GC_M3_DWT_COMP0_OFFSET 0x1020 +#define GC_M3_DWT_COMP0_DEFAULT 0x0 +#define GC_M3_DWT_MASK0_OFFSET 0x1024 +#define GC_M3_DWT_MASK0_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION0_OFFSET 0x1028 +#define GC_M3_DWT_FUNCTION0_DEFAULT 0x0 +#define GC_M3_DWT_COMP1_OFFSET 0x1030 +#define GC_M3_DWT_COMP1_DEFAULT 0x0 +#define GC_M3_DWT_MASK1_OFFSET 0x1034 +#define GC_M3_DWT_MASK1_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION1_DEFAULT 0x0 +#define GC_M3_DWT_COMP2_OFFSET 0x1040 +#define GC_M3_DWT_COMP2_DEFAULT 0x0 +#define GC_M3_DWT_MASK2_OFFSET 0x1044 +#define GC_M3_DWT_MASK2_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION2_OFFSET 0x1048 +#define GC_M3_DWT_FUNCTION2_DEFAULT 0x0 +#define GC_M3_DWT_COMP3_OFFSET 0x1050 +#define GC_M3_DWT_COMP3_DEFAULT 0x0 +#define GC_M3_DWT_MASK3_OFFSET 0x1054 +#define GC_M3_DWT_MASK3_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION3_OFFSET 0x1058 +#define GC_M3_DWT_FUNCTION3_DEFAULT 0x0 +#define GC_M3_FP_CTRL_OFFSET 0x2000 +#define GC_M3_FP_CTRL_DEFAULT 0x260 +#define GC_M3_FP_REMAP_OFFSET 0x2004 +#define GC_M3_FP_REMAP_DEFAULT 0x0 +#define GC_M3_FP_COMP0_OFFSET 0x2008 +#define GC_M3_FP_COMP0_DEFAULT 0x0 +#define GC_M3_FP_COMP1_OFFSET 0x200c +#define GC_M3_FP_COMP1_DEFAULT 0x0 +#define GC_M3_FP_COMP2_OFFSET 0x2010 +#define GC_M3_FP_COMP2_DEFAULT 0x0 +#define GC_M3_FP_COMP3_OFFSET 0x2014 +#define GC_M3_FP_COMP3_DEFAULT 0x0 +#define GC_M3_FP_COMP4_OFFSET 0x2018 +#define GC_M3_FP_COMP4_DEFAULT 0x0 +#define GC_M3_FP_COMP5_OFFSET 0x201c +#define GC_M3_FP_COMP5_DEFAULT 0x0 +#define GC_M3_FP_COMP6_OFFSET 0x2020 +#define GC_M3_FP_COMP6_DEFAULT 0x0 +#define GC_M3_FP_COMP7_OFFSET 0x2024 +#define GC_M3_FP_COMP7_DEFAULT 0x0 +#define GC_M3_ICTR_OFFSET 0xe004 +#define GC_M3_ICTR_DEFAULT 0x4 +#define GC_M3_SYST_CSR_OFFSET 0xe010 +#define GC_M3_SYST_CSR_DEFAULT 0x4 +#define GC_M3_SYST_RVR_OFFSET 0xe014 +#define GC_M3_SYST_RVR_DEFAULT 0x0 +#define GC_M3_SYST_CVR_OFFSET 0xe018 +#define GC_M3_SYST_CVR_DEFAULT 0x0 +#define GC_M3_SYST_CALIB_OFFSET 0xe01c +#define GC_M3_SYST_CALIB_DEFAULT 0x3f79f +#define GC_M3_NVIC_ISER0_OFFSET 0xe100 +#define GC_M3_NVIC_ISER0_DEFAULT 0x0 +#define GC_M3_NVIC_ISER1_OFFSET 0xe104 +#define GC_M3_NVIC_ISER1_DEFAULT 0x0 +#define GC_M3_NVIC_ISER2_OFFSET 0xe108 +#define GC_M3_NVIC_ISER2_DEFAULT 0x0 +#define GC_M3_NVIC_ISER3_OFFSET 0xe10c +#define GC_M3_NVIC_ISER3_DEFAULT 0x0 +#define GC_M3_NVIC_ISER4_OFFSET 0xe110 +#define GC_M3_NVIC_ISER4_DEFAULT 0x0 +#define GC_M3_NVIC_ISER5_OFFSET 0xe114 +#define GC_M3_NVIC_ISER5_DEFAULT 0x0 +#define GC_M3_NVIC_ISER6_OFFSET 0xe118 +#define GC_M3_NVIC_ISER6_DEFAULT 0x0 +#define GC_M3_NVIC_ISER7_OFFSET 0xe11c +#define GC_M3_NVIC_ISER7_DEFAULT 0x0 +#define GC_M3_NVIC_ICER0_OFFSET 0xe180 +#define GC_M3_NVIC_ICER0_DEFAULT 0x0 +#define GC_M3_NVIC_ICER1_OFFSET 0xe184 +#define GC_M3_NVIC_ICER1_DEFAULT 0x0 +#define GC_M3_NVIC_ICER2_OFFSET 0xe188 +#define GC_M3_NVIC_ICER2_DEFAULT 0x0 +#define GC_M3_NVIC_ICER3_OFFSET 0xe18c +#define GC_M3_NVIC_ICER3_DEFAULT 0x0 +#define GC_M3_NVIC_ICER4_OFFSET 0xe190 +#define GC_M3_NVIC_ICER4_DEFAULT 0x0 +#define GC_M3_NVIC_ICER5_OFFSET 0xe194 +#define GC_M3_NVIC_ICER5_DEFAULT 0x0 +#define GC_M3_NVIC_ICER6_OFFSET 0xe198 +#define GC_M3_NVIC_ICER6_DEFAULT 0x0 +#define GC_M3_NVIC_ICER7_OFFSET 0xe19c +#define GC_M3_NVIC_ICER7_DEFAULT 0x0 +#define GC_M3_NVIC_ISPR0_OFFSET 0xe200 +#define GC_M3_NVIC_ISPR0_DEFAULT 0x0 +#define GC_M3_NVIC_ISPR1_OFFSET 0xe204 +#define GC_M3_NVIC_ISPR1_DEFAULT 0x0 +#define GC_M3_NVIC_ISPR2_OFFSET 0xe208 +#define GC_M3_NVIC_ISPR2_DEFAULT 0x0 +#define GC_M3_NVIC_ISPR3_OFFSET 0xe20c +#define GC_M3_NVIC_ISPR3_DEFAULT 0x0 +#define GC_M3_NVIC_ISPR4_OFFSET 0xe210 +#define GC_M3_NVIC_ISPR4_DEFAULT 0x0 +#define GC_M3_NVIC_ISPR5_OFFSET 0xe214 +#define GC_M3_NVIC_ISPR5_DEFAULT 0x0 +#define GC_M3_NVIC_ISPR6_OFFSET 0xe218 +#define GC_M3_NVIC_ISPR6_DEFAULT 0x0 +#define GC_M3_NVIC_ISPR7_OFFSET 0xe21c +#define GC_M3_NVIC_ISPR7_DEFAULT 0x0 +#define GC_M3_NVIC_ICPR0_OFFSET 0xe280 +#define GC_M3_NVIC_ICPR0_DEFAULT 0x0 +#define GC_M3_NVIC_ICPR1_OFFSET 0xe284 +#define GC_M3_NVIC_ICPR1_DEFAULT 0x0 +#define GC_M3_NVIC_ICPR2_OFFSET 0xe288 +#define GC_M3_NVIC_ICPR2_DEFAULT 0x0 +#define GC_M3_NVIC_ICPR3_OFFSET 0xe28c +#define GC_M3_NVIC_ICPR3_DEFAULT 0x0 +#define GC_M3_NVIC_ICPR4_OFFSET 0xe290 +#define GC_M3_NVIC_ICPR4_DEFAULT 0x0 +#define GC_M3_NVIC_ICPR5_OFFSET 0xe294 +#define GC_M3_NVIC_ICPR5_DEFAULT 0x0 +#define GC_M3_NVIC_ICPR6_OFFSET 0xe298 +#define GC_M3_NVIC_ICPR6_DEFAULT 0x0 +#define GC_M3_NVIC_ICPR7_OFFSET 0xe29c +#define GC_M3_NVIC_ICPR7_DEFAULT 0x0 +#define GC_M3_NVIC_IABR0_OFFSET 0xe300 +#define GC_M3_NVIC_IABR0_DEFAULT 0x0 +#define GC_M3_NVIC_IABR1_OFFSET 0xe304 +#define GC_M3_NVIC_IABR1_DEFAULT 0x0 +#define GC_M3_NVIC_IABR2_OFFSET 0xe308 +#define GC_M3_NVIC_IABR2_DEFAULT 0x0 +#define GC_M3_NVIC_IABR3_OFFSET 0xe30c +#define GC_M3_NVIC_IABR3_DEFAULT 0x0 +#define GC_M3_NVIC_IABR4_OFFSET 0xe310 +#define GC_M3_NVIC_IABR4_DEFAULT 0x0 +#define GC_M3_NVIC_IABR5_OFFSET 0xe314 +#define GC_M3_NVIC_IABR5_DEFAULT 0x0 +#define GC_M3_NVIC_IABR6_OFFSET 0xe318 +#define GC_M3_NVIC_IABR6_DEFAULT 0x0 +#define GC_M3_NVIC_IABR7_OFFSET 0xe31c +#define GC_M3_NVIC_IABR7_DEFAULT 0x0 +#define GC_M3_NVIC_IPR0_OFFSET 0xe400 +#define GC_M3_NVIC_IPR0_DEFAULT 0x0 +#define GC_M3_NVIC_IPR1_OFFSET 0xe404 +#define GC_M3_NVIC_IPR1_DEFAULT 0x0 +#define GC_M3_NVIC_IPR2_OFFSET 0xe408 +#define GC_M3_NVIC_IPR2_DEFAULT 0x0 +#define GC_M3_NVIC_IPR3_OFFSET 0xe40c +#define GC_M3_NVIC_IPR3_DEFAULT 0x0 +#define GC_M3_NVIC_IPR4_OFFSET 0xe410 +#define GC_M3_NVIC_IPR4_DEFAULT 0x0 +#define GC_M3_NVIC_IPR5_OFFSET 0xe414 +#define GC_M3_NVIC_IPR5_DEFAULT 0x0 +#define GC_M3_NVIC_IPR6_OFFSET 0xe418 +#define GC_M3_NVIC_IPR6_DEFAULT 0x0 +#define GC_M3_NVIC_IPR7_OFFSET 0xe41c +#define GC_M3_NVIC_IPR7_DEFAULT 0x0 +#define GC_M3_NVIC_IPR8_OFFSET 0xe420 +#define GC_M3_NVIC_IPR8_DEFAULT 0x0 +#define GC_M3_NVIC_IPR9_OFFSET 0xe424 +#define GC_M3_NVIC_IPR9_DEFAULT 0x0 +#define GC_M3_NVIC_IPR10_OFFSET 0xe428 +#define GC_M3_NVIC_IPR10_DEFAULT 0x0 +#define GC_M3_NVIC_IPR11_OFFSET 0xe42c +#define GC_M3_NVIC_IPR11_DEFAULT 0x0 +#define GC_M3_NVIC_IPR12_OFFSET 0xe430 +#define GC_M3_NVIC_IPR12_DEFAULT 0x0 +#define GC_M3_NVIC_IPR13_OFFSET 0xe434 +#define GC_M3_NVIC_IPR13_DEFAULT 0x0 +#define GC_M3_NVIC_IPR14_OFFSET 0xe438 +#define GC_M3_NVIC_IPR14_DEFAULT 0x0 +#define GC_M3_NVIC_IPR15_OFFSET 0xe43c +#define GC_M3_NVIC_IPR15_DEFAULT 0x0 +#define GC_M3_NVIC_IPR16_OFFSET 0xe440 +#define GC_M3_NVIC_IPR16_DEFAULT 0x0 +#define GC_M3_NVIC_IPR17_OFFSET 0xe444 +#define GC_M3_NVIC_IPR17_DEFAULT 0x0 +#define GC_M3_NVIC_IPR18_OFFSET 0xe448 +#define GC_M3_NVIC_IPR18_DEFAULT 0x0 +#define GC_M3_NVIC_IPR19_OFFSET 0xe44c +#define GC_M3_NVIC_IPR19_DEFAULT 0x0 +#define GC_M3_NVIC_IPR20_OFFSET 0xe450 +#define GC_M3_NVIC_IPR20_DEFAULT 0x0 +#define GC_M3_NVIC_IPR21_OFFSET 0xe454 +#define GC_M3_NVIC_IPR21_DEFAULT 0x0 +#define GC_M3_NVIC_IPR22_OFFSET 0xe458 +#define GC_M3_NVIC_IPR22_DEFAULT 0x0 +#define GC_M3_NVIC_IPR23_OFFSET 0xe45c +#define GC_M3_NVIC_IPR23_DEFAULT 0x0 +#define GC_M3_NVIC_IPR24_OFFSET 0xe460 +#define GC_M3_NVIC_IPR24_DEFAULT 0x0 +#define GC_M3_NVIC_IPR25_OFFSET 0xe464 +#define GC_M3_NVIC_IPR25_DEFAULT 0x0 +#define GC_M3_NVIC_IPR26_OFFSET 0xe468 +#define GC_M3_NVIC_IPR26_DEFAULT 0x0 +#define GC_M3_NVIC_IPR27_OFFSET 0xe46c +#define GC_M3_NVIC_IPR27_DEFAULT 0x0 +#define GC_M3_NVIC_IPR28_OFFSET 0xe470 +#define GC_M3_NVIC_IPR28_DEFAULT 0x0 +#define GC_M3_NVIC_IPR29_OFFSET 0xe474 +#define GC_M3_NVIC_IPR29_DEFAULT 0x0 +#define GC_M3_NVIC_IPR30_OFFSET 0xe478 +#define GC_M3_NVIC_IPR30_DEFAULT 0x0 +#define GC_M3_NVIC_IPR31_OFFSET 0xe47c +#define GC_M3_NVIC_IPR31_DEFAULT 0x0 +#define GC_M3_NVIC_IPR32_OFFSET 0xe480 +#define GC_M3_NVIC_IPR32_DEFAULT 0x0 +#define GC_M3_NVIC_IPR33_OFFSET 0xe484 +#define GC_M3_NVIC_IPR33_DEFAULT 0x0 +#define GC_M3_NVIC_IPR34_OFFSET 0xe488 +#define GC_M3_NVIC_IPR34_DEFAULT 0x0 +#define GC_M3_NVIC_IPR35_OFFSET 0xe48c +#define GC_M3_NVIC_IPR35_DEFAULT 0x0 +#define GC_M3_NVIC_IPR36_OFFSET 0xe490 +#define GC_M3_NVIC_IPR36_DEFAULT 0x0 +#define GC_M3_NVIC_IPR37_OFFSET 0xe494 +#define GC_M3_NVIC_IPR37_DEFAULT 0x0 +#define GC_M3_NVIC_IPR38_OFFSET 0xe498 +#define GC_M3_NVIC_IPR38_DEFAULT 0x0 +#define GC_M3_NVIC_IPR39_OFFSET 0xe49c +#define GC_M3_NVIC_IPR39_DEFAULT 0x0 +#define GC_M3_NVIC_IPR40_OFFSET 0xe4a0 +#define GC_M3_NVIC_IPR40_DEFAULT 0x0 +#define GC_M3_NVIC_IPR41_OFFSET 0xe4a4 +#define GC_M3_NVIC_IPR41_DEFAULT 0x0 +#define GC_M3_NVIC_IPR42_OFFSET 0xe4a8 +#define GC_M3_NVIC_IPR42_DEFAULT 0x0 +#define GC_M3_NVIC_IPR43_OFFSET 0xe4ac +#define GC_M3_NVIC_IPR43_DEFAULT 0x0 +#define GC_M3_NVIC_IPR44_OFFSET 0xe4b0 +#define GC_M3_NVIC_IPR44_DEFAULT 0x0 +#define GC_M3_NVIC_IPR45_OFFSET 0xe4b4 +#define GC_M3_NVIC_IPR45_DEFAULT 0x0 +#define GC_M3_NVIC_IPR46_OFFSET 0xe4b8 +#define GC_M3_NVIC_IPR46_DEFAULT 0x0 +#define GC_M3_NVIC_IPR47_OFFSET 0xe4bc +#define GC_M3_NVIC_IPR47_DEFAULT 0x0 +#define GC_M3_NVIC_IPR48_OFFSET 0xe4c0 +#define GC_M3_NVIC_IPR48_DEFAULT 0x0 +#define GC_M3_NVIC_IPR49_OFFSET 0xe4c4 +#define GC_M3_NVIC_IPR49_DEFAULT 0x0 +#define GC_M3_NVIC_IPR50_OFFSET 0xe4c8 +#define GC_M3_NVIC_IPR50_DEFAULT 0x0 +#define GC_M3_NVIC_IPR51_OFFSET 0xe4cc +#define GC_M3_NVIC_IPR51_DEFAULT 0x0 +#define GC_M3_NVIC_IPR52_OFFSET 0xe4d0 +#define GC_M3_NVIC_IPR52_DEFAULT 0x0 +#define GC_M3_NVIC_IPR53_OFFSET 0xe4d4 +#define GC_M3_NVIC_IPR53_DEFAULT 0x0 +#define GC_M3_NVIC_IPR54_OFFSET 0xe4d8 +#define GC_M3_NVIC_IPR54_DEFAULT 0x0 +#define GC_M3_NVIC_IPR55_OFFSET 0xe4dc +#define GC_M3_NVIC_IPR55_DEFAULT 0x0 +#define GC_M3_NVIC_IPR56_OFFSET 0xe4e0 +#define GC_M3_NVIC_IPR56_DEFAULT 0x0 +#define GC_M3_NVIC_IPR57_OFFSET 0xe4e4 +#define GC_M3_NVIC_IPR57_DEFAULT 0x0 +#define GC_M3_NVIC_IPR58_OFFSET 0xe4e8 +#define GC_M3_NVIC_IPR58_DEFAULT 0x0 +#define GC_M3_CPUID_OFFSET 0xed00 +#define GC_M3_CPUID_DEFAULT 0x410fc331 +#define GC_M3_ICSR_OFFSET 0xed04 +#define GC_M3_ICSR_DEFAULT 0x0 +#define GC_M3_VTOR_OFFSET 0xed08 +#define GC_M3_VTOR_DEFAULT 0x0 +#define GC_M3_AIRCR_OFFSET 0xed0c +#define GC_M3_AIRCR_DEFAULT 0x0 +#define GC_M3_SCR_OFFSET 0xed10 +#define GC_M3_SCR_DEFAULT 0x0 +#define GC_M3_CCR_OFFSET 0xed14 +#define GC_M3_CCR_DEFAULT 0x0 +#define GC_M3_SHPR1_OFFSET 0xed18 +#define GC_M3_SHPR1_DEFAULT 0x0 +#define GC_M3_SHPR2_OFFSET 0xed1c +#define GC_M3_SHPR2_DEFAULT 0x0 +#define GC_M3_SHPR3_OFFSET 0xed20 +#define GC_M3_SHPR3_DEFAULT 0x0 +#define GC_M3_SHCSR_OFFSET 0xed24 +#define GC_M3_SHCSR_DEFAULT 0x0 +#define GC_M3_CFSR_OFFSET 0xed28 +#define GC_M3_CFSR_DEFAULT 0x0 +#define GC_M3_HFSR_OFFSET 0xed2c +#define GC_M3_HFSR_DEFAULT 0x0 +#define GC_M3_DFSR_OFFSET 0xed30 +#define GC_M3_DFSR_DEFAULT 0x0 +#define GC_M3_MMFAR_OFFSET 0xed34 +#define GC_M3_MMFAR_DEFAULT 0x0 +#define GC_M3_BFAR_OFFSET 0xed38 +#define GC_M3_BFAR_DEFAULT 0x0 +#define GC_M3_AFSR_OFFSET 0xed3c +#define GC_M3_AFSR_DEFAULT 0x0 +#define GC_M3_MPU_TYPE_OFFSET 0xed90 +#define GC_M3_MPU_TYPE_DEFAULT 0x800 +#define GC_M3_MPU_CTRL_OFFSET 0xed94 +#define GC_M3_MPU_CTRL_DEFAULT 0x0 +#define GC_M3_MPU_RNR_OFFSET 0xed98 +#define GC_M3_MPU_RNR_DEFAULT 0x0 +#define GC_M3_MPU_RBAR_OFFSET 0xed9c +#define GC_M3_MPU_RBAR_DEFAULT 0x0 +#define GC_M3_MPU_RASR_OFFSET 0xeda0 +#define GC_M3_MPU_RASR_DEFAULT 0x0 +#define GC_M3_MPU_RBAR_A1_OFFSET 0xeda4 +#define GC_M3_MPU_RBAR_A1_DEFAULT 0x0 +#define GC_M3_MPU_RASR_A1_OFFSET 0xeda8 +#define GC_M3_MPU_RASR_A1_DEFAULT 0x0 +#define GC_M3_MPU_RBAR_A2_OFFSET 0xedac +#define GC_M3_MPU_RBAR_A2_DEFAULT 0x0 +#define GC_M3_MPU_RASR_A2_OFFSET 0xedb0 +#define GC_M3_MPU_RASR_A2_DEFAULT 0x0 +#define GC_M3_MPU_RBAR_A3_OFFSET 0xedb4 +#define GC_M3_MPU_RBAR_A3_DEFAULT 0x0 +#define GC_M3_MPU_RASR_A3_OFFSET 0xedb8 +#define GC_M3_MPU_RASR_A3_DEFAULT 0x0 +#define GC_M3_DHCSR_OFFSET 0xedf0 +#define GC_M3_DHCSR_DEFAULT 0x0 +#define GC_M3_DCRSR_OFFSET 0xedf4 +#define GC_M3_DCRSR_DEFAULT 0x0 +#define GC_M3_DCRDR_OFFSET 0xedf8 +#define GC_M3_DCRDR_DEFAULT 0x0 +#define GC_M3_DEMCR_OFFSET 0xedfc +#define GC_M3_DEMCR_DEFAULT 0x0 +#define GC_M3_TPIU_SSPSR_OFFSET 0x40000 +#define GC_M3_TPIU_SSPSR_DEFAULT 0x0 +#define GC_M3_TPIU_CSPSR_OFFSET 0x40004 +#define GC_M3_TPIU_CSPSR_DEFAULT 0x1 +#define GC_M3_TPIU_ACPR_OFFSET 0x40010 +#define GC_M3_TPIU_ACPR_DEFAULT 0x0 +#define GC_M3_TPIU_SPPR_OFFSET 0x400f0 +#define GC_M3_TPIU_SPPR_DEFAULT 0x1 +#define GC_M3_TPIU_FFSR_OFFSET 0x40300 +#define GC_M3_TPIU_FFSR_DEFAULT 0x8 +#define GC_M3_TPIU_FFCR_OFFSET 0x40304 +#define GC_M3_TPIU_FFCR_DEFAULT 0x0 +#define GC_M3_TPIU_FSCR_OFFSET 0x40308 +#define GC_M3_TPIU_FSCR_DEFAULT 0x0 +#define GC_M3_TRIGGER_OFFSET 0x40ee8 +#define GC_M3_TRIGGER_DEFAULT 0x0 +#define GC_M3_FIFO_DATA0_OFFSET 0x40eec +#define GC_M3_FIFO_DATA0_DEFAULT 0x0 +#define GC_M3_ITATBCTR2_OFFSET 0x40ef0 +#define GC_M3_ITATBCTR2_DEFAULT 0x0 +#define GC_M3_ITATBCTR0_OFFSET 0x40ef8 +#define GC_M3_ITATBCTR0_DEFAULT 0x0 +#define GC_M3_FIFO_DATA1_OFFSET 0x40efc +#define GC_M3_FIFO_DATA1_DEFAULT 0x0 +#define GC_M3_ITCTRL_OFFSET 0x40f00 +#define GC_M3_ITCTRL_DEFAULT 0x0 +#define GC_M3_CLAIMSET_OFFSET 0x40fa0 +#define GC_M3_CLAIMSET_DEFAULT 0x0 +#define GC_M3_CLAIMCLR_OFFSET 0x40fa4 +#define GC_M3_CLAIMCLR_DEFAULT 0x0 +#define GC_M3_DEVID_OFFSET 0x40fc8 +#define GC_M3_DEVID_DEFAULT 0xca0 +#define GC_M3_DEVTYPE_OFFSET 0x40fcc +#define GC_M3_DEVTYPE_DEFAULT 0x11 +#define GC_M3_ITM_STIM0_ADDR 0xe0000000 +#define GC_M3_ITM_STIM1_ADDR 0xe0000004 +#define GC_M3_ITM_STIM2_ADDR 0xe0000008 +#define GC_M3_ITM_STIM3_ADDR 0xe000000c +#define GC_M3_ITM_STIM4_ADDR 0xe0000010 +#define GC_M3_ITM_STIM5_ADDR 0xe0000014 +#define GC_M3_ITM_STIM6_ADDR 0xe0000018 +#define GC_M3_ITM_STIM7_ADDR 0xe000001c +#define GC_M3_ITM_STIM8_ADDR 0xe0000020 +#define GC_M3_ITM_STIM9_ADDR 0xe0000024 +#define GC_M3_ITM_STIM10_ADDR 0xe0000028 +#define GC_M3_ITM_STIM11_ADDR 0xe000002c +#define GC_M3_ITM_STIM12_ADDR 0xe0000030 +#define GC_M3_ITM_STIM13_ADDR 0xe0000034 +#define GC_M3_ITM_STIM14_ADDR 0xe0000038 +#define GC_M3_ITM_STIM15_ADDR 0xe000003c +#define GC_M3_ITM_STIM16_ADDR 0xe0000040 +#define GC_M3_ITM_STIM17_ADDR 0xe0000044 +#define GC_M3_ITM_STIM18_ADDR 0xe0000048 +#define GC_M3_ITM_STIM19_ADDR 0xe000004c +#define GC_M3_ITM_STIM20_ADDR 0xe0000050 +#define GC_M3_ITM_STIM21_ADDR 0xe0000054 +#define GC_M3_ITM_STIM22_ADDR 0xe0000058 +#define GC_M3_ITM_STIM23_ADDR 0xe000005c +#define GC_M3_ITM_STIM24_ADDR 0xe0000060 +#define GC_M3_ITM_STIM25_ADDR 0xe0000064 +#define GC_M3_ITM_STIM26_ADDR 0xe0000068 +#define GC_M3_ITM_STIM27_ADDR 0xe000006c +#define GC_M3_ITM_STIM28_ADDR 0xe0000070 +#define GC_M3_ITM_STIM29_ADDR 0xe0000074 +#define GC_M3_ITM_STIM30_ADDR 0xe0000078 +#define GC_M3_ITM_STIM31_ADDR 0xe000007c +#define GC_M3_ITM_TER_ADDR 0xe0000e00 +#define GC_M3_ITM_TPR_ADDR 0xe0000e40 +#define GC_M3_ITM_TCR_ADDR 0xe0000e80 +#define GC_M3_ITM_INTRREG_ADDR 0xe0000ef0 +#define GC_M3_ITM_INTWREG_ADDR 0xe0000ef8 +#define GC_M3_ITM_INTMREG_ADDR 0xe0000f00 +#define GC_M3_ITM_LOCKCREG_ADDR 0xe0000fb0 +#define GC_M3_ITM_LOCKSREG_ADDR 0xe0000fb4 +#define GC_M3_DWT_CTRL_ADDR 0xe0001000 +#define GC_M3_DWT_CYCCNT_ADDR 0xe0001004 +#define GC_M3_DWT_CPICNT_ADDR 0xe0001008 +#define GC_M3_DWT_EXCCNT_ADDR 0xe000100c +#define GC_M3_DWT_SLEEPCNT_ADDR 0xe0001010 +#define GC_M3_DWT_LSUCNT_ADDR 0xe0001014 +#define GC_M3_DWT_FOLDCNT_ADDR 0xe0001018 +#define GC_M3_DWT_PCSR_ADDR 0xe000101c +#define GC_M3_DWT_COMP0_ADDR 0xe0001020 +#define GC_M3_DWT_MASK0_ADDR 0xe0001024 +#define GC_M3_DWT_FUNCTION0_ADDR 0xe0001028 +#define GC_M3_DWT_COMP1_ADDR 0xe0001030 +#define GC_M3_DWT_MASK1_ADDR 0xe0001034 +#define GC_M3_DWT_FUNCTION1_ADDR 0xe0001038 +#define GC_M3_DWT_COMP2_ADDR 0xe0001040 +#define GC_M3_DWT_MASK2_ADDR 0xe0001044 +#define GC_M3_DWT_FUNCTION2_ADDR 0xe0001048 +#define GC_M3_DWT_COMP3_ADDR 0xe0001050 +#define GC_M3_DWT_MASK3_ADDR 0xe0001054 +#define GC_M3_DWT_FUNCTION3_ADDR 0xe0001058 +#define GC_M3_FP_CTRL_ADDR 0xe0002000 +#define GC_M3_FP_REMAP_ADDR 0xe0002004 +#define GC_M3_FP_COMP0_ADDR 0xe0002008 +#define GC_M3_FP_COMP1_ADDR 0xe000200c +#define GC_M3_FP_COMP2_ADDR 0xe0002010 +#define GC_M3_FP_COMP3_ADDR 0xe0002014 +#define GC_M3_FP_COMP4_ADDR 0xe0002018 +#define GC_M3_FP_COMP5_ADDR 0xe000201c +#define GC_M3_FP_COMP6_ADDR 0xe0002020 +#define GC_M3_FP_COMP7_ADDR 0xe0002024 +#define GC_M3_ICTR_ADDR 0xe000e004 +#define GC_M3_SYST_CSR_ADDR 0xe000e010 +#define GC_M3_SYST_RVR_ADDR 0xe000e014 +#define GC_M3_SYST_CVR_ADDR 0xe000e018 +#define GC_M3_SYST_CALIB_ADDR 0xe000e01c +#define GC_M3_NVIC_ISER0_ADDR 0xe000e100 +#define GC_M3_NVIC_ISER1_ADDR 0xe000e104 +#define GC_M3_NVIC_ISER2_ADDR 0xe000e108 +#define GC_M3_NVIC_ISER3_ADDR 0xe000e10c +#define GC_M3_NVIC_ISER4_ADDR 0xe000e110 +#define GC_M3_NVIC_ISER5_ADDR 0xe000e114 +#define GC_M3_NVIC_ISER6_ADDR 0xe000e118 +#define GC_M3_NVIC_ISER7_ADDR 0xe000e11c +#define GC_M3_NVIC_ICER0_ADDR 0xe000e180 +#define GC_M3_NVIC_ICER1_ADDR 0xe000e184 +#define GC_M3_NVIC_ICER2_ADDR 0xe000e188 +#define GC_M3_NVIC_ICER3_ADDR 0xe000e18c +#define GC_M3_NVIC_ICER4_ADDR 0xe000e190 +#define GC_M3_NVIC_ICER5_ADDR 0xe000e194 +#define GC_M3_NVIC_ICER6_ADDR 0xe000e198 +#define GC_M3_NVIC_ICER7_ADDR 0xe000e19c +#define GC_M3_NVIC_ISPR0_ADDR 0xe000e200 +#define GC_M3_NVIC_ISPR1_ADDR 0xe000e204 +#define GC_M3_NVIC_ISPR2_ADDR 0xe000e208 +#define GC_M3_NVIC_ISPR3_ADDR 0xe000e20c +#define GC_M3_NVIC_ISPR4_ADDR 0xe000e210 +#define GC_M3_NVIC_ISPR5_ADDR 0xe000e214 +#define GC_M3_NVIC_ISPR6_ADDR 0xe000e218 +#define GC_M3_NVIC_ISPR7_ADDR 0xe000e21c +#define GC_M3_NVIC_ICPR0_ADDR 0xe000e280 +#define GC_M3_NVIC_ICPR1_ADDR 0xe000e284 +#define GC_M3_NVIC_ICPR2_ADDR 0xe000e288 +#define GC_M3_NVIC_ICPR3_ADDR 0xe000e28c +#define GC_M3_NVIC_ICPR4_ADDR 0xe000e290 +#define GC_M3_NVIC_ICPR5_ADDR 0xe000e294 +#define GC_M3_NVIC_ICPR6_ADDR 0xe000e298 +#define GC_M3_NVIC_ICPR7_ADDR 0xe000e29c +#define GC_M3_NVIC_IABR0_ADDR 0xe000e300 +#define GC_M3_NVIC_IABR1_ADDR 0xe000e304 +#define GC_M3_NVIC_IABR2_ADDR 0xe000e308 +#define GC_M3_NVIC_IABR3_ADDR 0xe000e30c +#define GC_M3_NVIC_IABR4_ADDR 0xe000e310 +#define GC_M3_NVIC_IABR5_ADDR 0xe000e314 +#define GC_M3_NVIC_IABR6_ADDR 0xe000e318 +#define GC_M3_NVIC_IABR7_ADDR 0xe000e31c +#define GC_M3_NVIC_IPR0_ADDR 0xe000e400 +#define GC_M3_NVIC_IPR1_ADDR 0xe000e404 +#define GC_M3_NVIC_IPR2_ADDR 0xe000e408 +#define GC_M3_NVIC_IPR3_ADDR 0xe000e40c +#define GC_M3_NVIC_IPR4_ADDR 0xe000e410 +#define GC_M3_NVIC_IPR5_ADDR 0xe000e414 +#define GC_M3_NVIC_IPR6_ADDR 0xe000e418 +#define GC_M3_NVIC_IPR7_ADDR 0xe000e41c +#define GC_M3_NVIC_IPR8_ADDR 0xe000e420 +#define GC_M3_NVIC_IPR9_ADDR 0xe000e424 +#define GC_M3_NVIC_IPR10_ADDR 0xe000e428 +#define GC_M3_NVIC_IPR11_ADDR 0xe000e42c +#define GC_M3_NVIC_IPR12_ADDR 0xe000e430 +#define GC_M3_NVIC_IPR13_ADDR 0xe000e434 +#define GC_M3_NVIC_IPR14_ADDR 0xe000e438 +#define GC_M3_NVIC_IPR15_ADDR 0xe000e43c +#define GC_M3_NVIC_IPR16_ADDR 0xe000e440 +#define GC_M3_NVIC_IPR17_ADDR 0xe000e444 +#define GC_M3_NVIC_IPR18_ADDR 0xe000e448 +#define GC_M3_NVIC_IPR19_ADDR 0xe000e44c +#define GC_M3_NVIC_IPR20_ADDR 0xe000e450 +#define GC_M3_NVIC_IPR21_ADDR 0xe000e454 +#define GC_M3_NVIC_IPR22_ADDR 0xe000e458 +#define GC_M3_NVIC_IPR23_ADDR 0xe000e45c +#define GC_M3_NVIC_IPR24_ADDR 0xe000e460 +#define GC_M3_NVIC_IPR25_ADDR 0xe000e464 +#define GC_M3_NVIC_IPR26_ADDR 0xe000e468 +#define GC_M3_NVIC_IPR27_ADDR 0xe000e46c +#define GC_M3_NVIC_IPR28_ADDR 0xe000e470 +#define GC_M3_NVIC_IPR29_ADDR 0xe000e474 +#define GC_M3_NVIC_IPR30_ADDR 0xe000e478 +#define GC_M3_NVIC_IPR31_ADDR 0xe000e47c +#define GC_M3_NVIC_IPR32_ADDR 0xe000e480 +#define GC_M3_NVIC_IPR33_ADDR 0xe000e484 +#define GC_M3_NVIC_IPR34_ADDR 0xe000e488 +#define GC_M3_NVIC_IPR35_ADDR 0xe000e48c +#define GC_M3_NVIC_IPR36_ADDR 0xe000e490 +#define GC_M3_NVIC_IPR37_ADDR 0xe000e494 +#define GC_M3_NVIC_IPR38_ADDR 0xe000e498 +#define GC_M3_NVIC_IPR39_ADDR 0xe000e49c +#define GC_M3_NVIC_IPR40_ADDR 0xe000e4a0 +#define GC_M3_NVIC_IPR41_ADDR 0xe000e4a4 +#define GC_M3_NVIC_IPR42_ADDR 0xe000e4a8 +#define GC_M3_NVIC_IPR43_ADDR 0xe000e4ac +#define GC_M3_NVIC_IPR44_ADDR 0xe000e4b0 +#define GC_M3_NVIC_IPR45_ADDR 0xe000e4b4 +#define GC_M3_NVIC_IPR46_ADDR 0xe000e4b8 +#define GC_M3_NVIC_IPR47_ADDR 0xe000e4bc +#define GC_M3_NVIC_IPR48_ADDR 0xe000e4c0 +#define GC_M3_NVIC_IPR49_ADDR 0xe000e4c4 +#define GC_M3_NVIC_IPR50_ADDR 0xe000e4c8 +#define GC_M3_NVIC_IPR51_ADDR 0xe000e4cc +#define GC_M3_NVIC_IPR52_ADDR 0xe000e4d0 +#define GC_M3_NVIC_IPR53_ADDR 0xe000e4d4 +#define GC_M3_NVIC_IPR54_ADDR 0xe000e4d8 +#define GC_M3_NVIC_IPR55_ADDR 0xe000e4dc +#define GC_M3_NVIC_IPR56_ADDR 0xe000e4e0 +#define GC_M3_NVIC_IPR57_ADDR 0xe000e4e4 +#define GC_M3_NVIC_IPR58_ADDR 0xe000e4e8 +#define GC_M3_CPUID_ADDR 0xe000ed00 +#define GC_M3_ICSR_ADDR 0xe000ed04 +#define GC_M3_VTOR_ADDR 0xe000ed08 +#define GC_M3_AIRCR_ADDR 0xe000ed0c +#define GC_M3_SCR_ADDR 0xe000ed10 +#define GC_M3_CCR_ADDR 0xe000ed14 +#define GC_M3_SHPR1_ADDR 0xe000ed18 +#define GC_M3_SHPR2_ADDR 0xe000ed1c +#define GC_M3_SHPR3_ADDR 0xe000ed20 +#define GC_M3_SHCSR_ADDR 0xe000ed24 +#define GC_M3_CFSR_ADDR 0xe000ed28 +#define GC_M3_HFSR_ADDR 0xe000ed2c +#define GC_M3_DFSR_ADDR 0xe000ed30 +#define GC_M3_MMFAR_ADDR 0xe000ed34 +#define GC_M3_BFAR_ADDR 0xe000ed38 +#define GC_M3_AFSR_ADDR 0xe000ed3c +#define GC_M3_MPU_TYPE_ADDR 0xe000ed90 +#define GC_M3_MPU_CTRL_ADDR 0xe000ed94 +#define GC_M3_MPU_RNR_ADDR 0xe000ed98 +#define GC_M3_MPU_RBAR_ADDR 0xe000ed9c +#define GC_M3_MPU_RASR_ADDR 0xe000eda0 +#define GC_M3_MPU_RBAR_A1_ADDR 0xe000eda4 +#define GC_M3_MPU_RASR_A1_ADDR 0xe000eda8 +#define GC_M3_MPU_RBAR_A2_ADDR 0xe000edac +#define GC_M3_MPU_RASR_A2_ADDR 0xe000edb0 +#define GC_M3_MPU_RBAR_A3_ADDR 0xe000edb4 +#define GC_M3_MPU_RASR_A3_ADDR 0xe000edb8 +#define GC_M3_DHCSR_ADDR 0xe000edf0 +#define GC_M3_DCRSR_ADDR 0xe000edf4 +#define GC_M3_DCRDR_ADDR 0xe000edf8 +#define GC_M3_DEMCR_ADDR 0xe000edfc +#define GC_M3_TPIU_SSPSR_ADDR 0xe0040000 +#define GC_M3_TPIU_CSPSR_ADDR 0xe0040004 +#define GC_M3_TPIU_ACPR_ADDR 0xe0040010 +#define GC_M3_TPIU_SPPR_ADDR 0xe00400f0 +#define GC_M3_TPIU_FFSR_ADDR 0xe0040300 +#define GC_M3_TPIU_FFCR_ADDR 0xe0040304 +#define GC_M3_TPIU_FSCR_ADDR 0xe0040308 +#define GC_M3_TRIGGER_ADDR 0xe0040ee8 +#define GC_M3_FIFO_DATA0_ADDR 0xe0040eec +#define GC_M3_ITATBCTR2_ADDR 0xe0040ef0 +#define GC_M3_ITATBCTR0_ADDR 0xe0040ef8 +#define GC_M3_FIFO_DATA1_ADDR 0xe0040efc +#define GC_M3_ITCTRL_ADDR 0xe0040f00 +#define GC_M3_CLAIMSET_ADDR 0xe0040fa0 +#define GC_M3_CLAIMCLR_ADDR 0xe0040fa4 +#define GC_M3_DEVID_ADDR 0xe0040fc8 +#define GC_M3_DEVTYPE_ADDR 0xe0040fcc +#define GC_AES_CTRL_KEYSIZE_LSB 0x0 +#define GC_AES_CTRL_KEYSIZE_MASK 0x3 +#define GC_AES_CTRL_KEYSIZE_SIZE 0x2 +#define GC_AES_CTRL_KEYSIZE_DEFAULT 0x0 +#define GC_AES_CTRL_KEYSIZE_OFFSET 0x0 +#define GC_AES_CTRL_CTR_MODE_LSB 0x2 +#define GC_AES_CTRL_CTR_MODE_MASK 0x4 +#define GC_AES_CTRL_CTR_MODE_SIZE 0x1 +#define GC_AES_CTRL_CTR_MODE_DEFAULT 0x0 +#define GC_AES_CTRL_CTR_MODE_OFFSET 0x0 +#define GC_AES_CTRL_ENC_MODE_LSB 0x3 +#define GC_AES_CTRL_ENC_MODE_MASK 0x8 +#define GC_AES_CTRL_ENC_MODE_SIZE 0x1 +#define GC_AES_CTRL_ENC_MODE_DEFAULT 0x0 +#define GC_AES_CTRL_ENC_MODE_OFFSET 0x0 +#define GC_AES_CTRL_CTR_ENDIAN_LSB 0x4 +#define GC_AES_CTRL_CTR_ENDIAN_MASK 0x10 +#define GC_AES_CTRL_CTR_ENDIAN_SIZE 0x1 +#define GC_AES_CTRL_CTR_ENDIAN_DEFAULT 0x0 +#define GC_AES_CTRL_CTR_ENDIAN_OFFSET 0x0 +#define GC_AES_LFSR_CTL_STALL_EN_LSB 0x0 +#define GC_AES_LFSR_CTL_STALL_EN_MASK 0x1 +#define GC_AES_LFSR_CTL_STALL_EN_SIZE 0x1 +#define GC_AES_LFSR_CTL_STALL_EN_DEFAULT 0x1 +#define GC_AES_LFSR_CTL_STALL_EN_OFFSET 0x60 +#define GC_AES_LFSR_CTL_WIDTH_LSB 0x1 +#define GC_AES_LFSR_CTL_WIDTH_MASK 0x6 +#define GC_AES_LFSR_CTL_WIDTH_SIZE 0x2 +#define GC_AES_LFSR_CTL_WIDTH_DEFAULT 0x3 +#define GC_AES_LFSR_CTL_WIDTH_OFFSET 0x60 +#define GC_AES_LFSR_CTL_FREQ_LSB 0x3 +#define GC_AES_LFSR_CTL_FREQ_MASK 0x18 +#define GC_AES_LFSR_CTL_FREQ_SIZE 0x2 +#define GC_AES_LFSR_CTL_FREQ_DEFAULT 0x3 +#define GC_AES_LFSR_CTL_FREQ_OFFSET 0x60 +#define GC_AES_VERSION_CHANGE_LSB 0x0 +#define GC_AES_VERSION_CHANGE_MASK 0xffffff +#define GC_AES_VERSION_CHANGE_SIZE 0x18 +#define GC_AES_VERSION_CHANGE_DEFAULT 0xbe5c +#define GC_AES_VERSION_CHANGE_OFFSET 0x64 +#define GC_AES_VERSION_REVISION_LSB 0x18 +#define GC_AES_VERSION_REVISION_MASK 0xff000000 +#define GC_AES_VERSION_REVISION_SIZE 0x8 +#define GC_AES_VERSION_REVISION_DEFAULT 0x8 +#define GC_AES_VERSION_REVISION_OFFSET 0x64 +#define GC_CAMO_INT_ENABLE_BREACH_LSB 0x0 +#define GC_CAMO_INT_ENABLE_BREACH_MASK 0x1 +#define GC_CAMO_INT_ENABLE_BREACH_SIZE 0x1 +#define GC_CAMO_INT_ENABLE_BREACH_DEFAULT 0x0 +#define GC_CAMO_INT_ENABLE_BREACH_OFFSET 0x8 +#define GC_CAMO_INT_STATE_BREACH_LSB 0x0 +#define GC_CAMO_INT_STATE_BREACH_MASK 0x1 +#define GC_CAMO_INT_STATE_BREACH_SIZE 0x1 +#define GC_CAMO_INT_STATE_BREACH_DEFAULT 0x0 +#define GC_CAMO_INT_STATE_BREACH_OFFSET 0xc +#define GC_CAMO_INT_TEST_BREACH_LSB 0x0 +#define GC_CAMO_INT_TEST_BREACH_MASK 0x1 +#define GC_CAMO_INT_TEST_BREACH_SIZE 0x1 +#define GC_CAMO_INT_TEST_BREACH_DEFAULT 0x0 +#define GC_CAMO_INT_TEST_BREACH_OFFSET 0x10 +#define GC_CAMO_VERSION_CHANGE_LSB 0x0 +#define GC_CAMO_VERSION_CHANGE_MASK 0xffffff +#define GC_CAMO_VERSION_CHANGE_SIZE 0x18 +#define GC_CAMO_VERSION_CHANGE_DEFAULT 0xba73 +#define GC_CAMO_VERSION_CHANGE_OFFSET 0x28 +#define GC_CAMO_VERSION_REVISION_LSB 0x18 +#define GC_CAMO_VERSION_REVISION_MASK 0xff000000 +#define GC_CAMO_VERSION_REVISION_SIZE 0x8 +#define GC_CAMO_VERSION_REVISION_DEFAULT 0x5 +#define GC_CAMO_VERSION_REVISION_OFFSET 0x28 +#define GC_FLASH_FSH_TRANS_OFFSET_LSB 0x0 +#define GC_FLASH_FSH_TRANS_OFFSET_MASK 0xffff +#define GC_FLASH_FSH_TRANS_OFFSET_SIZE 0x10 +#define GC_FLASH_FSH_TRANS_OFFSET_DEFAULT 0x0 +#define GC_FLASH_FSH_TRANS_OFFSET_OFFSET 0x8 +#define GC_FLASH_FSH_TRANS_MAINB_LSB 0x10 +#define GC_FLASH_FSH_TRANS_MAINB_MASK 0x10000 +#define GC_FLASH_FSH_TRANS_MAINB_SIZE 0x1 +#define GC_FLASH_FSH_TRANS_MAINB_DEFAULT 0x0 +#define GC_FLASH_FSH_TRANS_MAINB_OFFSET 0x8 +#define GC_FLASH_FSH_TRANS_SIZE_LSB 0x11 +#define GC_FLASH_FSH_TRANS_SIZE_MASK 0x3e0000 +#define GC_FLASH_FSH_TRANS_SIZE_SIZE 0x5 +#define GC_FLASH_FSH_TRANS_SIZE_DEFAULT 0x0 +#define GC_FLASH_FSH_TRANS_SIZE_OFFSET 0x8 +#define GC_FLASH_FSH_ICTRL_EDONE_LSB 0x0 +#define GC_FLASH_FSH_ICTRL_EDONE_MASK 0x1 +#define GC_FLASH_FSH_ICTRL_EDONE_SIZE 0x1 +#define GC_FLASH_FSH_ICTRL_EDONE_DEFAULT 0x0 +#define GC_FLASH_FSH_ICTRL_EDONE_OFFSET 0xc +#define GC_FLASH_FSH_ICTRL_PDONE_LSB 0x1 +#define GC_FLASH_FSH_ICTRL_PDONE_MASK 0x2 +#define GC_FLASH_FSH_ICTRL_PDONE_SIZE 0x1 +#define GC_FLASH_FSH_ICTRL_PDONE_DEFAULT 0x0 +#define GC_FLASH_FSH_ICTRL_PDONE_OFFSET 0xc +#define GC_FLASH_FSH_ISTATE_EDONE_LSB 0x0 +#define GC_FLASH_FSH_ISTATE_EDONE_MASK 0x1 +#define GC_FLASH_FSH_ISTATE_EDONE_SIZE 0x1 +#define GC_FLASH_FSH_ISTATE_EDONE_DEFAULT 0x0 +#define GC_FLASH_FSH_ISTATE_EDONE_OFFSET 0x10 +#define GC_FLASH_FSH_ISTATE_PDONE_LSB 0x1 +#define GC_FLASH_FSH_ISTATE_PDONE_MASK 0x2 +#define GC_FLASH_FSH_ISTATE_PDONE_SIZE 0x1 +#define GC_FLASH_FSH_ISTATE_PDONE_DEFAULT 0x0 +#define GC_FLASH_FSH_ISTATE_PDONE_OFFSET 0x10 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_LSB 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_MASK 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_LSB 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_MASK 0x2 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_LSB 0x2 +#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_MASK 0x4 +#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_LSB 0x3 +#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_MASK 0x8 +#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_XE_LSB 0x4 +#define GC_FLASH_FSH_OVRD_SIGVAL_XE_MASK 0x10 +#define GC_FLASH_FSH_OVRD_SIGVAL_XE_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_XE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_XE_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_YE_LSB 0x5 +#define GC_FLASH_FSH_OVRD_SIGVAL_YE_MASK 0x20 +#define GC_FLASH_FSH_OVRD_SIGVAL_YE_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_YE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_YE_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_SE_LSB 0x6 +#define GC_FLASH_FSH_OVRD_SIGVAL_SE_MASK 0x40 +#define GC_FLASH_FSH_OVRD_SIGVAL_SE_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_SE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_SE_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_LSB 0x7 +#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_MASK 0x80 +#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_LSB 0x8 +#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_MASK 0x100 +#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_LSB 0x9 +#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_MASK 0x200 +#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_LSB 0xa +#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_MASK 0x400 +#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_PV_LSB 0xb +#define GC_FLASH_FSH_OVRD_SIGVAL_PV_MASK 0x800 +#define GC_FLASH_FSH_OVRD_SIGVAL_PV_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_PV_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_PV_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_EV_LSB 0xc +#define GC_FLASH_FSH_OVRD_SIGVAL_EV_MASK 0x1000 +#define GC_FLASH_FSH_OVRD_SIGVAL_EV_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGVAL_EV_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGVAL_EV_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_LSB 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_MASK 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_LSB 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_MASK 0x2 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_LSB 0x2 +#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_MASK 0x4 +#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_TMR_LSB 0x3 +#define GC_FLASH_FSH_OVRD_SIGEN_TMR_MASK 0x8 +#define GC_FLASH_FSH_OVRD_SIGEN_TMR_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_TMR_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_TMR_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_XE_LSB 0x4 +#define GC_FLASH_FSH_OVRD_SIGEN_XE_MASK 0x10 +#define GC_FLASH_FSH_OVRD_SIGEN_XE_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_XE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_XE_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_YE_LSB 0x5 +#define GC_FLASH_FSH_OVRD_SIGEN_YE_MASK 0x20 +#define GC_FLASH_FSH_OVRD_SIGEN_YE_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_YE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_YE_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_SE_LSB 0x6 +#define GC_FLASH_FSH_OVRD_SIGEN_SE_MASK 0x40 +#define GC_FLASH_FSH_OVRD_SIGEN_SE_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_SE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_SE_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_LSB 0x7 +#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_MASK 0x80 +#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_PROG_LSB 0x8 +#define GC_FLASH_FSH_OVRD_SIGEN_PROG_MASK 0x100 +#define GC_FLASH_FSH_OVRD_SIGEN_PROG_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_PROG_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_PROG_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_LSB 0x9 +#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_MASK 0x200 +#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_LSB 0xa +#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_MASK 0x400 +#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_PV_LSB 0xb +#define GC_FLASH_FSH_OVRD_SIGEN_PV_MASK 0x800 +#define GC_FLASH_FSH_OVRD_SIGEN_PV_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_PV_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_PV_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_EV_LSB 0xc +#define GC_FLASH_FSH_OVRD_SIGEN_EV_MASK 0x1000 +#define GC_FLASH_FSH_OVRD_SIGEN_EV_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_EV_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_EV_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_DIN_LSB 0xd +#define GC_FLASH_FSH_OVRD_SIGEN_DIN_MASK 0x2000 +#define GC_FLASH_FSH_OVRD_SIGEN_DIN_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_DIN_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_DIN_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_LSB 0xe +#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_MASK 0x4000 +#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_LSB 0xf +#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_MASK 0x8000 +#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_OFFSET 0x28 +#define GC_FLASH_FSH_REDUN0_EN_LSB 0x0 +#define GC_FLASH_FSH_REDUN0_EN_MASK 0x1 +#define GC_FLASH_FSH_REDUN0_EN_SIZE 0x1 +#define GC_FLASH_FSH_REDUN0_EN_DEFAULT 0x0 +#define GC_FLASH_FSH_REDUN0_EN_OFFSET 0xbc +#define GC_FLASH_FSH_REDUN0_REMAP_LSB 0x1 +#define GC_FLASH_FSH_REDUN0_REMAP_MASK 0xfe +#define GC_FLASH_FSH_REDUN0_REMAP_SIZE 0x7 +#define GC_FLASH_FSH_REDUN0_REMAP_DEFAULT 0x0 +#define GC_FLASH_FSH_REDUN0_REMAP_OFFSET 0xbc +#define GC_FLASH_FSH_REDUN1_EN_LSB 0x0 +#define GC_FLASH_FSH_REDUN1_EN_MASK 0x1 +#define GC_FLASH_FSH_REDUN1_EN_SIZE 0x1 +#define GC_FLASH_FSH_REDUN1_EN_DEFAULT 0x0 +#define GC_FLASH_FSH_REDUN1_EN_OFFSET 0xc0 +#define GC_FLASH_FSH_REDUN1_REMAP_LSB 0x1 +#define GC_FLASH_FSH_REDUN1_REMAP_MASK 0xfe +#define GC_FLASH_FSH_REDUN1_REMAP_SIZE 0x7 +#define GC_FLASH_FSH_REDUN1_REMAP_DEFAULT 0x0 +#define GC_FLASH_FSH_REDUN1_REMAP_OFFSET 0xc0 +#define GC_FLASH_FSH_DBG_STATE_LSB 0x0 +#define GC_FLASH_FSH_DBG_STATE_MASK 0xf +#define GC_FLASH_FSH_DBG_STATE_SIZE 0x4 +#define GC_FLASH_FSH_DBG_STATE_DEFAULT 0x0 +#define GC_FLASH_FSH_DBG_STATE_OFFSET 0x16c +#define GC_FLASH_FSH_ITOP_PDONEINT_LSB 0x0 +#define GC_FLASH_FSH_ITOP_PDONEINT_MASK 0x1 +#define GC_FLASH_FSH_ITOP_PDONEINT_SIZE 0x1 +#define GC_FLASH_FSH_ITOP_PDONEINT_DEFAULT 0x0 +#define GC_FLASH_FSH_ITOP_PDONEINT_OFFSET 0xf04 +#define GC_FLASH_FSH_ITOP_EDONEINT_LSB 0x1 +#define GC_FLASH_FSH_ITOP_EDONEINT_MASK 0x2 +#define GC_FLASH_FSH_ITOP_EDONEINT_SIZE 0x1 +#define GC_FLASH_FSH_ITOP_EDONEINT_DEFAULT 0x0 +#define GC_FLASH_FSH_ITOP_EDONEINT_OFFSET 0xf04 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_RNG_LSB 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_RNG_MASK 0xf +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_RNG_SIZE 0x4 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_RNG_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_RNG_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_RNG_LSB 0x4 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_RNG_MASK 0xf0 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_RNG_SIZE 0x4 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_RNG_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_RNG_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_RNG_LSB 0x8 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_RNG_MASK 0xf00 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_RNG_SIZE 0x4 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_RNG_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_RNG_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_MODE_LSB 0xc +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_MODE_MASK 0x1000 +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_MODE_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_MODE_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_MODE_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_CLR_LSB 0xd +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_CLR_MASK 0x2000 +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_CLR_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_CLR_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_SEC_MONITOR_CLR_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_PERR_CLR_LSB 0xe +#define GC_GLOBALSEC_SEC_CONTROL_PERR_CLR_MASK 0x4000 +#define GC_GLOBALSEC_SEC_CONTROL_PERR_CLR_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_PERR_CLR_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_PERR_CLR_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_EN_LSB 0x10 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_EN_MASK 0x10000 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_EN_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_LFSR_EN_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_SEED_LFSR_LSB 0x11 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_SEED_LFSR_MASK 0x20000 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_SEED_LFSR_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_SEED_LFSR_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_PSCU_SEED_LFSR_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_EN_LSB 0x12 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_EN_MASK 0x40000 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_EN_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_LFSR_EN_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_SEED_LFSR_LSB 0x13 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_SEED_LFSR_MASK 0x80000 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_SEED_LFSR_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_SEED_LFSR_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_RBIU_SEED_LFSR_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_EN_LSB 0x14 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_EN_MASK 0x100000 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_EN_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_LFSR_EN_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_SEED_LFSR_LSB 0x15 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_SEED_LFSR_MASK 0x200000 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_SEED_LFSR_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_SEED_LFSR_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_CGOU_SEED_LFSR_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_PPBLOCK_LSB 0x18 +#define GC_GLOBALSEC_SEC_CONTROL_PPBLOCK_MASK 0x3f000000 +#define GC_GLOBALSEC_SEC_CONTROL_PPBLOCK_SIZE 0x6 +#define GC_GLOBALSEC_SEC_CONTROL_PPBLOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_PPBLOCK_OFFSET 0x26d0 +#define GC_GLOBALSEC_SEC_CONTROL_REG_BANK_CLR_LSB 0x1f +#define GC_GLOBALSEC_SEC_CONTROL_REG_BANK_CLR_MASK 0x80000000 +#define GC_GLOBALSEC_SEC_CONTROL_REG_BANK_CLR_SIZE 0x1 +#define GC_GLOBALSEC_SEC_CONTROL_REG_BANK_CLR_DEFAULT 0x0 +#define GC_GLOBALSEC_SEC_CONTROL_REG_BANK_CLR_OFFSET 0x26d0 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLEDEBUG_LSB 0x0 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLEDEBUG_MASK 0x1 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLEDEBUG_SIZE 0x1 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLEDEBUG_DEFAULT 0x0 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLEDEBUG_OFFSET 0xb1dc +#define GC_GLOBALSEC_DBG_CONTROL_DISABLETRACE_LSB 0x1 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLETRACE_MASK 0x2 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLETRACE_SIZE 0x1 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLETRACE_DEFAULT 0x0 +#define GC_GLOBALSEC_DBG_CONTROL_DISABLETRACE_OFFSET 0xb1dc +#define GC_GLOBALSEC_VERSION_CHANGE_LSB 0x0 +#define GC_GLOBALSEC_VERSION_CHANGE_MASK 0xffffff +#define GC_GLOBALSEC_VERSION_CHANGE_SIZE 0x18 +#define GC_GLOBALSEC_VERSION_CHANGE_DEFAULT 0xb407 +#define GC_GLOBALSEC_VERSION_CHANGE_OFFSET 0xb2b0 +#define GC_GLOBALSEC_VERSION_REVISION_LSB 0x18 +#define GC_GLOBALSEC_VERSION_REVISION_MASK 0xff000000 +#define GC_GLOBALSEC_VERSION_REVISION_SIZE 0x8 +#define GC_GLOBALSEC_VERSION_REVISION_DEFAULT 0x1 +#define GC_GLOBALSEC_VERSION_REVISION_OFFSET 0xb2b0 +#define GC_I2C_CTRL_PHASESTEPS_P0_LSB 0x0 +#define GC_I2C_CTRL_PHASESTEPS_P0_MASK 0x3f +#define GC_I2C_CTRL_PHASESTEPS_P0_SIZE 0x6 +#define GC_I2C_CTRL_PHASESTEPS_P0_DEFAULT 0x6 +#define GC_I2C_CTRL_PHASESTEPS_P0_OFFSET 0x8 +#define GC_I2C_CTRL_PHASESTEPS_P1_LSB 0x6 +#define GC_I2C_CTRL_PHASESTEPS_P1_MASK 0xfc0 +#define GC_I2C_CTRL_PHASESTEPS_P1_SIZE 0x6 +#define GC_I2C_CTRL_PHASESTEPS_P1_DEFAULT 0x6 +#define GC_I2C_CTRL_PHASESTEPS_P1_OFFSET 0x8 +#define GC_I2C_CTRL_PHASESTEPS_P2_LSB 0xc +#define GC_I2C_CTRL_PHASESTEPS_P2_MASK 0x3f000 +#define GC_I2C_CTRL_PHASESTEPS_P2_SIZE 0x6 +#define GC_I2C_CTRL_PHASESTEPS_P2_DEFAULT 0x8 +#define GC_I2C_CTRL_PHASESTEPS_P2_OFFSET 0x8 +#define GC_I2C_CTRL_PHASESTEPS_P3_LSB 0x12 +#define GC_I2C_CTRL_PHASESTEPS_P3_MASK 0xfc0000 +#define GC_I2C_CTRL_PHASESTEPS_P3_SIZE 0x6 +#define GC_I2C_CTRL_PHASESTEPS_P3_DEFAULT 0x6 +#define GC_I2C_CTRL_PHASESTEPS_P3_OFFSET 0x8 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_LSB 0x0 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_MASK 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_LSB 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_MASK 0x2 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_LSB 0x2 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_MASK 0x4 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_LSB 0x3 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_MASK 0x8 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_LSB 0x4 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_MASK 0x10 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_LSB 0x5 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_MASK 0x20 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_LSB 0x6 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_MASK 0x40 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_LSB 0x7 +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_MASK 0x80 +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_LSB 0x8 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_MASK 0x100 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_LSB 0x9 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_MASK 0x200 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_LSB 0xa +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_MASK 0x400 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_LSB 0xb +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_MASK 0x800 +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_LSB 0xc +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_MASK 0x1000 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_LSB 0xd +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_MASK 0x2000 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_LSB 0xe +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_MASK 0x4000 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_LSB 0xf +#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_MASK 0x8000 +#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_LSB 0x10 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_MASK 0x10000 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_LSB 0x11 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_MASK 0x20000 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_LSB 0x12 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_MASK 0x40000 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_LSB 0x13 +#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_MASK 0x80000 +#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_LSB 0x14 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_MASK 0x100000 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_LSB 0x15 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_MASK 0x200000 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_LSB 0x16 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_MASK 0x400000 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_LSB 0x17 +#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_MASK 0x800000 +#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_OFFSET 0xc +#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_LSB 0x18 +#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_MASK 0x1000000 +#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_OFFSET 0xc +#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_LSB 0x0 +#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_MASK 0x1 +#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_LSB 0x1 +#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_MASK 0x2 +#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_LSB 0x2 +#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_MASK 0x4 +#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_LSB 0x3 +#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_MASK 0x8 +#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_LSB 0x4 +#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_MASK 0x10 +#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_LSB 0x5 +#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_MASK 0x20 +#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_LSB 0x6 +#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_MASK 0x40 +#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_LSB 0x7 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_MASK 0x80 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_LSB 0x8 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_MASK 0x100 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_LSB 0x9 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_MASK 0x200 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_OFFSET 0x10 +#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_LSB 0xa +#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_MASK 0x400 +#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_SIZE 0x1 +#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_DEFAULT 0x0 +#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_OFFSET 0x10 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_LSB 0x0 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_MASK 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_LSB 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_MASK 0x2 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_LSB 0x2 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_MASK 0x4 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_LSB 0x3 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_MASK 0x8 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_LSB 0x4 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_MASK 0x10 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_LSB 0x5 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_MASK 0x20 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_LSB 0x6 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_MASK 0x40 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_LSB 0x7 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_MASK 0x80 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_LSB 0x8 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_MASK 0x100 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_LSB 0x9 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_MASK 0x200 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_LSB 0xa +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_MASK 0x400 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_LSB 0xb +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_MASK 0x800 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_LSB 0xc +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_MASK 0x1000 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_LSB 0xd +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_MASK 0x2000 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_LSB 0xe +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_MASK 0x4000 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_LSB 0xf +#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_MASK 0x8000 +#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_LSB 0x10 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_MASK 0x10000 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_LSB 0x11 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_MASK 0x20000 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_LSB 0x12 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_MASK 0x40000 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_LSB 0x13 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_MASK 0x80000 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_LSB 0x14 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_MASK 0x100000 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_LSB 0x15 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_MASK 0x200000 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_LSB 0x16 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_MASK 0x400000 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_LSB 0x17 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_MASK 0x800000 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_LSB 0x18 +#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_MASK 0x1000000 +#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_OFFSET 0x14 +#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_LSB 0x0 +#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_MASK 0x1 +#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_LSB 0x1 +#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_MASK 0x2 +#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_LSB 0x2 +#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_MASK 0x4 +#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_LSB 0x3 +#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_MASK 0x8 +#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_LSB 0x4 +#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_MASK 0x10 +#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_LSB 0x5 +#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_MASK 0x20 +#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_LSB 0x6 +#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_MASK 0x40 +#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_LSB 0x7 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_MASK 0x80 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_LSB 0x8 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_MASK 0x100 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_DEFAULT 0x0 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_LSB 0x9 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_MASK 0x200 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_OFFSET 0x18 +#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_LSB 0xa +#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_MASK 0x400 +#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_SIZE 0x1 +#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_DEFAULT 0x1 +#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_OFFSET 0x18 +#define GC_I2C_CTRL_AL_EN_LSB 0x0 +#define GC_I2C_CTRL_AL_EN_MASK 0x1 +#define GC_I2C_CTRL_AL_EN_SIZE 0x1 +#define GC_I2C_CTRL_AL_EN_DEFAULT 0x1 +#define GC_I2C_CTRL_AL_EN_OFFSET 0x20 +#define GC_I2C_CTRL_AL_PHASEMASK_LSB 0x1 +#define GC_I2C_CTRL_AL_PHASEMASK_MASK 0x1e +#define GC_I2C_CTRL_AL_PHASEMASK_SIZE 0x4 +#define GC_I2C_CTRL_AL_PHASEMASK_DEFAULT 0xf +#define GC_I2C_CTRL_AL_PHASEMASK_OFFSET 0x20 +#define GC_I2C_CTRL_CS_EN_LSB 0x0 +#define GC_I2C_CTRL_CS_EN_MASK 0x1 +#define GC_I2C_CTRL_CS_EN_SIZE 0x1 +#define GC_I2C_CTRL_CS_EN_DEFAULT 0x1 +#define GC_I2C_CTRL_CS_EN_OFFSET 0x24 +#define GC_I2C_CTRL_CS_TIMEOUTEN_LSB 0x1 +#define GC_I2C_CTRL_CS_TIMEOUTEN_MASK 0x2 +#define GC_I2C_CTRL_CS_TIMEOUTEN_SIZE 0x1 +#define GC_I2C_CTRL_CS_TIMEOUTEN_DEFAULT 0x1 +#define GC_I2C_CTRL_CS_TIMEOUTEN_OFFSET 0x24 +#define GC_I2C_CTRL_CS_TIMEOUTVAL_LSB 0x2 +#define GC_I2C_CTRL_CS_TIMEOUTVAL_MASK 0x3ffffc +#define GC_I2C_CTRL_CS_TIMEOUTVAL_SIZE 0x14 +#define GC_I2C_CTRL_CS_TIMEOUTVAL_DEFAULT 0x4e20 +#define GC_I2C_CTRL_CS_TIMEOUTVAL_OFFSET 0x24 +#define GC_I2C_INST_RESERVED0_LSB 0x0 +#define GC_I2C_INST_RESERVED0_MASK 0x1 +#define GC_I2C_INST_RESERVED0_SIZE 0x1 +#define GC_I2C_INST_RESERVED0_DEFAULT 0x0 +#define GC_I2C_INST_RESERVED0_OFFSET 0x28 +#define GC_I2C_INST_START_LSB 0x1 +#define GC_I2C_INST_START_MASK 0x2 +#define GC_I2C_INST_START_SIZE 0x1 +#define GC_I2C_INST_START_DEFAULT 0x0 +#define GC_I2C_INST_START_OFFSET 0x28 +#define GC_I2C_INST_FWDEVADDR_LSB 0x2 +#define GC_I2C_INST_FWDEVADDR_MASK 0x4 +#define GC_I2C_INST_FWDEVADDR_SIZE 0x1 +#define GC_I2C_INST_FWDEVADDR_DEFAULT 0x0 +#define GC_I2C_INST_FWDEVADDR_OFFSET 0x28 +#define GC_I2C_INST_FWBYTESCOUNT_LSB 0x3 +#define GC_I2C_INST_FWBYTESCOUNT_MASK 0x38 +#define GC_I2C_INST_FWBYTESCOUNT_SIZE 0x3 +#define GC_I2C_INST_FWBYTESCOUNT_DEFAULT 0x0 +#define GC_I2C_INST_FWBYTESCOUNT_OFFSET 0x28 +#define GC_I2C_INST_SCL0_LSB 0x6 +#define GC_I2C_INST_SCL0_MASK 0x40 +#define GC_I2C_INST_SCL0_SIZE 0x1 +#define GC_I2C_INST_SCL0_DEFAULT 0x0 +#define GC_I2C_INST_SCL0_OFFSET 0x28 +#define GC_I2C_INST_FREE_BUS_LSB 0x7 +#define GC_I2C_INST_FREE_BUS_MASK 0x80 +#define GC_I2C_INST_FREE_BUS_SIZE 0x1 +#define GC_I2C_INST_FREE_BUS_DEFAULT 0x0 +#define GC_I2C_INST_FREE_BUS_OFFSET 0x28 +#define GC_I2C_INST_FIRSTSTOP_LSB 0x8 +#define GC_I2C_INST_FIRSTSTOP_MASK 0x100 +#define GC_I2C_INST_FIRSTSTOP_SIZE 0x1 +#define GC_I2C_INST_FIRSTSTOP_DEFAULT 0x0 +#define GC_I2C_INST_FIRSTSTOP_OFFSET 0x28 +#define GC_I2C_INST_REPEATEDSTART_LSB 0x9 +#define GC_I2C_INST_REPEATEDSTART_MASK 0x200 +#define GC_I2C_INST_REPEATEDSTART_SIZE 0x1 +#define GC_I2C_INST_REPEATEDSTART_DEFAULT 0x0 +#define GC_I2C_INST_REPEATEDSTART_OFFSET 0x28 +#define GC_I2C_INST_RWDEVADDR_LSB 0xa +#define GC_I2C_INST_RWDEVADDR_MASK 0x400 +#define GC_I2C_INST_RWDEVADDR_SIZE 0x1 +#define GC_I2C_INST_RWDEVADDR_DEFAULT 0x0 +#define GC_I2C_INST_RWDEVADDR_OFFSET 0x28 +#define GC_I2C_INST_RWDEVADDR_RWB_LSB 0xb +#define GC_I2C_INST_RWDEVADDR_RWB_MASK 0x800 +#define GC_I2C_INST_RWDEVADDR_RWB_SIZE 0x1 +#define GC_I2C_INST_RWDEVADDR_RWB_DEFAULT 0x0 +#define GC_I2C_INST_RWDEVADDR_RWB_OFFSET 0x28 +#define GC_I2C_INST_RWBYTESCOUNT_LSB 0xc +#define GC_I2C_INST_RWBYTESCOUNT_MASK 0x7f000 +#define GC_I2C_INST_RWBYTESCOUNT_SIZE 0x7 +#define GC_I2C_INST_RWBYTESCOUNT_DEFAULT 0x0 +#define GC_I2C_INST_RWBYTESCOUNT_OFFSET 0x28 +#define GC_I2C_INST_FINALNA_LSB 0x13 +#define GC_I2C_INST_FINALNA_MASK 0x80000 +#define GC_I2C_INST_FINALNA_SIZE 0x1 +#define GC_I2C_INST_FINALNA_DEFAULT 0x0 +#define GC_I2C_INST_FINALNA_OFFSET 0x28 +#define GC_I2C_INST_RWBIT_LSB 0x14 +#define GC_I2C_INST_RWBIT_MASK 0x300000 +#define GC_I2C_INST_RWBIT_SIZE 0x2 +#define GC_I2C_INST_RWBIT_DEFAULT 0x0 +#define GC_I2C_INST_RWBIT_OFFSET 0x28 +#define GC_I2C_INST_HOLD0_LSB 0x16 +#define GC_I2C_INST_HOLD0_MASK 0x400000 +#define GC_I2C_INST_HOLD0_SIZE 0x1 +#define GC_I2C_INST_HOLD0_DEFAULT 0x0 +#define GC_I2C_INST_HOLD0_OFFSET 0x28 +#define GC_I2C_INST_FINALSTOP_LSB 0x17 +#define GC_I2C_INST_FINALSTOP_MASK 0x800000 +#define GC_I2C_INST_FINALSTOP_SIZE 0x1 +#define GC_I2C_INST_FINALSTOP_DEFAULT 0x0 +#define GC_I2C_INST_FINALSTOP_OFFSET 0x28 +#define GC_I2C_INST_RESETB_RWPTR_LSB 0x18 +#define GC_I2C_INST_RESETB_RWPTR_MASK 0x1000000 +#define GC_I2C_INST_RESETB_RWPTR_SIZE 0x1 +#define GC_I2C_INST_RESETB_RWPTR_DEFAULT 0x0 +#define GC_I2C_INST_RESETB_RWPTR_OFFSET 0x28 +#define GC_I2C_INST_DEVADDRVAL_LSB 0x19 +#define GC_I2C_INST_DEVADDRVAL_MASK 0xfe000000 +#define GC_I2C_INST_DEVADDRVAL_SIZE 0x7 +#define GC_I2C_INST_DEVADDRVAL_DEFAULT 0x0 +#define GC_I2C_INST_DEVADDRVAL_OFFSET 0x28 +#define GC_I2C_STATUS_RESERVED0_LSB 0x0 +#define GC_I2C_STATUS_RESERVED0_MASK 0x1 +#define GC_I2C_STATUS_RESERVED0_SIZE 0x1 +#define GC_I2C_STATUS_RESERVED0_DEFAULT 0x0 +#define GC_I2C_STATUS_RESERVED0_OFFSET 0x2c +#define GC_I2C_STATUS_START_LSB 0x1 +#define GC_I2C_STATUS_START_MASK 0x2 +#define GC_I2C_STATUS_START_SIZE 0x1 +#define GC_I2C_STATUS_START_DEFAULT 0x0 +#define GC_I2C_STATUS_START_OFFSET 0x2c +#define GC_I2C_STATUS_FWDEVADDR_LSB 0x2 +#define GC_I2C_STATUS_FWDEVADDR_MASK 0x4 +#define GC_I2C_STATUS_FWDEVADDR_SIZE 0x1 +#define GC_I2C_STATUS_FWDEVADDR_DEFAULT 0x0 +#define GC_I2C_STATUS_FWDEVADDR_OFFSET 0x2c +#define GC_I2C_STATUS_FWBYTESCOUNT_LSB 0x3 +#define GC_I2C_STATUS_FWBYTESCOUNT_MASK 0x38 +#define GC_I2C_STATUS_FWBYTESCOUNT_SIZE 0x3 +#define GC_I2C_STATUS_FWBYTESCOUNT_DEFAULT 0x0 +#define GC_I2C_STATUS_FWBYTESCOUNT_OFFSET 0x2c +#define GC_I2C_STATUS_SCL0_LSB 0x6 +#define GC_I2C_STATUS_SCL0_MASK 0x40 +#define GC_I2C_STATUS_SCL0_SIZE 0x1 +#define GC_I2C_STATUS_SCL0_DEFAULT 0x0 +#define GC_I2C_STATUS_SCL0_OFFSET 0x2c +#define GC_I2C_STATUS_FREE_BUS_LSB 0x7 +#define GC_I2C_STATUS_FREE_BUS_MASK 0x80 +#define GC_I2C_STATUS_FREE_BUS_SIZE 0x1 +#define GC_I2C_STATUS_FREE_BUS_DEFAULT 0x0 +#define GC_I2C_STATUS_FREE_BUS_OFFSET 0x2c +#define GC_I2C_STATUS_FIRSTSTOP_LSB 0x8 +#define GC_I2C_STATUS_FIRSTSTOP_MASK 0x100 +#define GC_I2C_STATUS_FIRSTSTOP_SIZE 0x1 +#define GC_I2C_STATUS_FIRSTSTOP_DEFAULT 0x0 +#define GC_I2C_STATUS_FIRSTSTOP_OFFSET 0x2c +#define GC_I2C_STATUS_REPEATEDSTART_LSB 0x9 +#define GC_I2C_STATUS_REPEATEDSTART_MASK 0x200 +#define GC_I2C_STATUS_REPEATEDSTART_SIZE 0x1 +#define GC_I2C_STATUS_REPEATEDSTART_DEFAULT 0x0 +#define GC_I2C_STATUS_REPEATEDSTART_OFFSET 0x2c +#define GC_I2C_STATUS_RWDEVADDR_LSB 0xa +#define GC_I2C_STATUS_RWDEVADDR_MASK 0x400 +#define GC_I2C_STATUS_RWDEVADDR_SIZE 0x1 +#define GC_I2C_STATUS_RWDEVADDR_DEFAULT 0x0 +#define GC_I2C_STATUS_RWDEVADDR_OFFSET 0x2c +#define GC_I2C_STATUS_RWDEVADDR_RWB_LSB 0xb +#define GC_I2C_STATUS_RWDEVADDR_RWB_MASK 0x800 +#define GC_I2C_STATUS_RWDEVADDR_RWB_SIZE 0x1 +#define GC_I2C_STATUS_RWDEVADDR_RWB_DEFAULT 0x0 +#define GC_I2C_STATUS_RWDEVADDR_RWB_OFFSET 0x2c +#define GC_I2C_STATUS_RWBYTESCOUNT_LSB 0xc +#define GC_I2C_STATUS_RWBYTESCOUNT_MASK 0x7f000 +#define GC_I2C_STATUS_RWBYTESCOUNT_SIZE 0x7 +#define GC_I2C_STATUS_RWBYTESCOUNT_DEFAULT 0x0 +#define GC_I2C_STATUS_RWBYTESCOUNT_OFFSET 0x2c +#define GC_I2C_STATUS_FINALNA_LSB 0x13 +#define GC_I2C_STATUS_FINALNA_MASK 0x80000 +#define GC_I2C_STATUS_FINALNA_SIZE 0x1 +#define GC_I2C_STATUS_FINALNA_DEFAULT 0x0 +#define GC_I2C_STATUS_FINALNA_OFFSET 0x2c +#define GC_I2C_STATUS_RWBIT_LSB 0x14 +#define GC_I2C_STATUS_RWBIT_MASK 0x300000 +#define GC_I2C_STATUS_RWBIT_SIZE 0x2 +#define GC_I2C_STATUS_RWBIT_DEFAULT 0x0 +#define GC_I2C_STATUS_RWBIT_OFFSET 0x2c +#define GC_I2C_STATUS_HOLD0_LSB 0x16 +#define GC_I2C_STATUS_HOLD0_MASK 0x400000 +#define GC_I2C_STATUS_HOLD0_SIZE 0x1 +#define GC_I2C_STATUS_HOLD0_DEFAULT 0x0 +#define GC_I2C_STATUS_HOLD0_OFFSET 0x2c +#define GC_I2C_STATUS_FINALSTOP_LSB 0x17 +#define GC_I2C_STATUS_FINALSTOP_MASK 0x800000 +#define GC_I2C_STATUS_FINALSTOP_SIZE 0x1 +#define GC_I2C_STATUS_FINALSTOP_DEFAULT 0x0 +#define GC_I2C_STATUS_FINALSTOP_OFFSET 0x2c +#define GC_I2C_STATUS_INTB_LSB 0x18 +#define GC_I2C_STATUS_INTB_MASK 0x1000000 +#define GC_I2C_STATUS_INTB_SIZE 0x1 +#define GC_I2C_STATUS_INTB_DEFAULT 0x0 +#define GC_I2C_STATUS_INTB_OFFSET 0x2c +#define GC_I2C_STATUS_CA_NACK_LSB 0x19 +#define GC_I2C_STATUS_CA_NACK_MASK 0x2000000 +#define GC_I2C_STATUS_CA_NACK_SIZE 0x1 +#define GC_I2C_STATUS_CA_NACK_DEFAULT 0x0 +#define GC_I2C_STATUS_CA_NACK_OFFSET 0x2c +#define GC_I2C_STATUS_AL_LSB 0x1a +#define GC_I2C_STATUS_AL_MASK 0x4000000 +#define GC_I2C_STATUS_AL_SIZE 0x1 +#define GC_I2C_STATUS_AL_DEFAULT 0x0 +#define GC_I2C_STATUS_AL_OFFSET 0x2c +#define GC_I2C_STATUS_ALBITPTR_LSB 0x1b +#define GC_I2C_STATUS_ALBITPTR_MASK 0x78000000 +#define GC_I2C_STATUS_ALBITPTR_SIZE 0x4 +#define GC_I2C_STATUS_ALBITPTR_DEFAULT 0x0 +#define GC_I2C_STATUS_ALBITPTR_OFFSET 0x2c +#define GC_I2C_STATUS_CSTIMEOUT_LSB 0x1f +#define GC_I2C_STATUS_CSTIMEOUT_MASK 0x80000000 +#define GC_I2C_STATUS_CSTIMEOUT_SIZE 0x1 +#define GC_I2C_STATUS_CSTIMEOUT_DEFAULT 0x0 +#define GC_I2C_STATUS_CSTIMEOUT_OFFSET 0x2c +#define GC_I2C_READVAL_SDA_LSB 0x0 +#define GC_I2C_READVAL_SDA_MASK 0x1 +#define GC_I2C_READVAL_SDA_SIZE 0x1 +#define GC_I2C_READVAL_SDA_DEFAULT 0x0 +#define GC_I2C_READVAL_SDA_OFFSET 0x78 +#define GC_I2C_READVAL_SCL_LSB 0x1 +#define GC_I2C_READVAL_SCL_MASK 0x2 +#define GC_I2C_READVAL_SCL_SIZE 0x1 +#define GC_I2C_READVAL_SCL_DEFAULT 0x0 +#define GC_I2C_READVAL_SCL_OFFSET 0x78 +#define GC_I2C_CTRL_MSR_SDA_LSB 0x0 +#define GC_I2C_CTRL_MSR_SDA_MASK 0x3 +#define GC_I2C_CTRL_MSR_SDA_SIZE 0x2 +#define GC_I2C_CTRL_MSR_SDA_DEFAULT 0x2 +#define GC_I2C_CTRL_MSR_SDA_OFFSET 0x7c +#define GC_I2C_CTRL_MSR_SCL_LSB 0x2 +#define GC_I2C_CTRL_MSR_SCL_MASK 0xc +#define GC_I2C_CTRL_MSR_SCL_SIZE 0x2 +#define GC_I2C_CTRL_MSR_SCL_DEFAULT 0x2 +#define GC_I2C_CTRL_MSR_SCL_OFFSET 0x7c +#define GC_I2CS_VERSION_CHANGE_LSB 0x0 +#define GC_I2CS_VERSION_CHANGE_MASK 0xffffff +#define GC_I2CS_VERSION_CHANGE_SIZE 0x18 +#define GC_I2CS_VERSION_CHANGE_DEFAULT 0xb99f +#define GC_I2CS_VERSION_CHANGE_OFFSET 0x0 +#define GC_I2CS_VERSION_REVISION_LSB 0x18 +#define GC_I2CS_VERSION_REVISION_MASK 0xff000000 +#define GC_I2CS_VERSION_REVISION_SIZE 0x8 +#define GC_I2CS_VERSION_REVISION_DEFAULT 0x4 +#define GC_I2CS_VERSION_REVISION_OFFSET 0x0 +#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_LSB 0x0 +#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_MASK 0x1 +#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_SIZE 0x1 +#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_DEFAULT 0x0 +#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_OFFSET 0x4 +#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_LSB 0x1 +#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_MASK 0x2 +#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_SIZE 0x1 +#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_DEFAULT 0x0 +#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_OFFSET 0x4 +#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_LSB 0x2 +#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_MASK 0x4 +#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_SIZE 0x1 +#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_DEFAULT 0x0 +#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_OFFSET 0x4 +#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_LSB 0x0 +#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_MASK 0x1 +#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_SIZE 0x1 +#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_DEFAULT 0x0 +#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_OFFSET 0x8 +#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_LSB 0x1 +#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_MASK 0x2 +#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_SIZE 0x1 +#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_DEFAULT 0x0 +#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_OFFSET 0x8 +#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_LSB 0x2 +#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_MASK 0x4 +#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_SIZE 0x1 +#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_DEFAULT 0x0 +#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_OFFSET 0x8 +#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_LSB 0x0 +#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_MASK 0x1 +#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_SIZE 0x1 +#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_DEFAULT 0x0 +#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_OFFSET 0xc +#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_LSB 0x1 +#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_MASK 0x2 +#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_SIZE 0x1 +#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_DEFAULT 0x0 +#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_OFFSET 0xc +#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_LSB 0x2 +#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_MASK 0x4 +#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_SIZE 0x1 +#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_DEFAULT 0x0 +#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_OFFSET 0xc +#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_LSB 0x0 +#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_MASK 0x1 +#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_SIZE 0x1 +#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_DEFAULT 0x1 +#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_OFFSET 0x10 +#define GC_I2CS_CTRL_SDA_VAL_READ0_S_LSB 0x1 +#define GC_I2CS_CTRL_SDA_VAL_READ0_S_MASK 0x2 +#define GC_I2CS_CTRL_SDA_VAL_READ0_S_SIZE 0x1 +#define GC_I2CS_CTRL_SDA_VAL_READ0_S_DEFAULT 0x0 +#define GC_I2CS_CTRL_SDA_VAL_READ0_S_OFFSET 0x10 +#define GC_I2CS_CTRL_SDA_VAL_READ1_S_LSB 0x2 +#define GC_I2CS_CTRL_SDA_VAL_READ1_S_MASK 0x4 +#define GC_I2CS_CTRL_SDA_VAL_READ1_S_SIZE 0x1 +#define GC_I2CS_CTRL_SDA_VAL_READ1_S_DEFAULT 0x1 +#define GC_I2CS_CTRL_SDA_VAL_READ1_S_OFFSET 0x10 +#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_LSB 0x3 +#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_MASK 0x8 +#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_SIZE 0x1 +#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_DEFAULT 0x1 +#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_OFFSET 0x10 +#define GC_I2CS_CTRL_SDA_VAL_START_S_LSB 0x4 +#define GC_I2CS_CTRL_SDA_VAL_START_S_MASK 0x10 +#define GC_I2CS_CTRL_SDA_VAL_START_S_SIZE 0x1 +#define GC_I2CS_CTRL_SDA_VAL_START_S_DEFAULT 0x1 +#define GC_I2CS_CTRL_SDA_VAL_START_S_OFFSET 0x10 +#define GC_I2CS_CTRL_SDA_VAL_STOP_S_LSB 0x5 +#define GC_I2CS_CTRL_SDA_VAL_STOP_S_MASK 0x20 +#define GC_I2CS_CTRL_SDA_VAL_STOP_S_SIZE 0x1 +#define GC_I2CS_CTRL_SDA_VAL_STOP_S_DEFAULT 0x1 +#define GC_I2CS_CTRL_SDA_VAL_STOP_S_OFFSET 0x10 +#define GC_I2CS_READVAL_SDA_LSB 0x0 +#define GC_I2CS_READVAL_SDA_MASK 0x1 +#define GC_I2CS_READVAL_SDA_SIZE 0x1 +#define GC_I2CS_READVAL_SDA_DEFAULT 0x0 +#define GC_I2CS_READVAL_SDA_OFFSET 0x20 +#define GC_I2CS_READVAL_SCL_LSB 0x1 +#define GC_I2CS_READVAL_SCL_MASK 0x2 +#define GC_I2CS_READVAL_SCL_SIZE 0x1 +#define GC_I2CS_READVAL_SCL_DEFAULT 0x0 +#define GC_I2CS_READVAL_SCL_OFFSET 0x20 +#define GC_I2CS_CTRL_MSR_SDA_LSB 0x0 +#define GC_I2CS_CTRL_MSR_SDA_MASK 0x3 +#define GC_I2CS_CTRL_MSR_SDA_SIZE 0x2 +#define GC_I2CS_CTRL_MSR_SDA_DEFAULT 0x2 +#define GC_I2CS_CTRL_MSR_SDA_OFFSET 0x24 +#define GC_I2CS_CTRL_MSR_SCL_LSB 0x2 +#define GC_I2CS_CTRL_MSR_SCL_MASK 0xc +#define GC_I2CS_CTRL_MSR_SCL_SIZE 0x2 +#define GC_I2CS_CTRL_MSR_SCL_DEFAULT 0x2 +#define GC_I2CS_CTRL_MSR_SCL_OFFSET 0x24 +#define GC_MAU_EN_SYSIBUS_LSB 0x0 +#define GC_MAU_EN_SYSIBUS_MASK 0x1 +#define GC_MAU_EN_SYSIBUS_SIZE 0x1 +#define GC_MAU_EN_SYSIBUS_DEFAULT 0x1 +#define GC_MAU_EN_SYSIBUS_OFFSET 0x0 +#define GC_MAU_EN_SYSDBUS_LSB 0x1 +#define GC_MAU_EN_SYSDBUS_MASK 0x2 +#define GC_MAU_EN_SYSDBUS_SIZE 0x1 +#define GC_MAU_EN_SYSDBUS_DEFAULT 0x1 +#define GC_MAU_EN_SYSDBUS_OFFSET 0x0 +#define GC_MAU_TRACECLR_SYSIBUS_LSB 0x0 +#define GC_MAU_TRACECLR_SYSIBUS_MASK 0x1 +#define GC_MAU_TRACECLR_SYSIBUS_SIZE 0x1 +#define GC_MAU_TRACECLR_SYSIBUS_DEFAULT 0x1 +#define GC_MAU_TRACECLR_SYSIBUS_OFFSET 0x4 +#define GC_MAU_TRACECLR_SYSDBUS_LSB 0x1 +#define GC_MAU_TRACECLR_SYSDBUS_MASK 0x2 +#define GC_MAU_TRACECLR_SYSDBUS_SIZE 0x1 +#define GC_MAU_TRACECLR_SYSDBUS_DEFAULT 0x1 +#define GC_MAU_TRACECLR_SYSDBUS_OFFSET 0x4 +#define GC_MAU_TRACEIDX_SYSIBUS_LSB 0x0 +#define GC_MAU_TRACEIDX_SYSIBUS_MASK 0x1 +#define GC_MAU_TRACEIDX_SYSIBUS_SIZE 0x1 +#define GC_MAU_TRACEIDX_SYSIBUS_DEFAULT 0x1 +#define GC_MAU_TRACEIDX_SYSIBUS_OFFSET 0x8 +#define GC_MAU_TRACEIDX_SYSDBUS_LSB 0x1 +#define GC_MAU_TRACEIDX_SYSDBUS_MASK 0x2 +#define GC_MAU_TRACEIDX_SYSDBUS_SIZE 0x1 +#define GC_MAU_TRACEIDX_SYSDBUS_DEFAULT 0x1 +#define GC_MAU_TRACEIDX_SYSDBUS_OFFSET 0x8 +#define GC_PAU_EN_SYSSBUS_LSB 0x0 +#define GC_PAU_EN_SYSSBUS_MASK 0x1 +#define GC_PAU_EN_SYSSBUS_SIZE 0x1 +#define GC_PAU_EN_SYSSBUS_DEFAULT 0x1 +#define GC_PAU_EN_SYSSBUS_OFFSET 0x0 +#define GC_PAU_TRACECLR_SYSSBUS_LSB 0x0 +#define GC_PAU_TRACECLR_SYSSBUS_MASK 0x1 +#define GC_PAU_TRACECLR_SYSSBUS_SIZE 0x1 +#define GC_PAU_TRACECLR_SYSSBUS_DEFAULT 0x1 +#define GC_PAU_TRACECLR_SYSSBUS_OFFSET 0x4 +#define GC_PAU_TRACEIDX_SYSSBUS_LSB 0x0 +#define GC_PAU_TRACEIDX_SYSSBUS_MASK 0x1 +#define GC_PAU_TRACEIDX_SYSSBUS_SIZE 0x1 +#define GC_PAU_TRACEIDX_SYSSBUS_DEFAULT 0x1 +#define GC_PAU_TRACEIDX_SYSSBUS_OFFSET 0x8 +#define GC_PINMUX_DIOM0_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOM0_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOM0_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOM0_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOM0_CTL_DS_OFFSET 0x4 +#define GC_PINMUX_DIOM0_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOM0_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOM0_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOM0_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOM0_CTL_IE_OFFSET 0x4 +#define GC_PINMUX_DIOM0_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOM0_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOM0_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOM0_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOM0_CTL_PD_OFFSET 0x4 +#define GC_PINMUX_DIOM0_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOM0_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOM0_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOM0_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOM0_CTL_PU_OFFSET 0x4 +#define GC_PINMUX_DIOM0_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOM0_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOM0_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOM0_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOM0_CTL_INV_OFFSET 0x4 +#define GC_PINMUX_DIOM1_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOM1_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOM1_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOM1_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOM1_CTL_DS_OFFSET 0xc +#define GC_PINMUX_DIOM1_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOM1_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOM1_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOM1_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOM1_CTL_IE_OFFSET 0xc +#define GC_PINMUX_DIOM1_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOM1_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOM1_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOM1_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOM1_CTL_PD_OFFSET 0xc +#define GC_PINMUX_DIOM1_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOM1_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOM1_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOM1_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOM1_CTL_PU_OFFSET 0xc +#define GC_PINMUX_DIOM1_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOM1_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOM1_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOM1_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOM1_CTL_INV_OFFSET 0xc +#define GC_PINMUX_DIOM2_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOM2_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOM2_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOM2_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOM2_CTL_DS_OFFSET 0x14 +#define GC_PINMUX_DIOM2_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOM2_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOM2_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOM2_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOM2_CTL_IE_OFFSET 0x14 +#define GC_PINMUX_DIOM2_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOM2_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOM2_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOM2_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOM2_CTL_PD_OFFSET 0x14 +#define GC_PINMUX_DIOM2_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOM2_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOM2_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOM2_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOM2_CTL_PU_OFFSET 0x14 +#define GC_PINMUX_DIOM2_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOM2_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOM2_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOM2_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOM2_CTL_INV_OFFSET 0x14 +#define GC_PINMUX_DIOM3_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOM3_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOM3_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOM3_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOM3_CTL_DS_OFFSET 0x1c +#define GC_PINMUX_DIOM3_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOM3_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOM3_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOM3_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOM3_CTL_IE_OFFSET 0x1c +#define GC_PINMUX_DIOM3_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOM3_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOM3_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOM3_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOM3_CTL_PD_OFFSET 0x1c +#define GC_PINMUX_DIOM3_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOM3_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOM3_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOM3_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOM3_CTL_PU_OFFSET 0x1c +#define GC_PINMUX_DIOM3_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOM3_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOM3_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOM3_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOM3_CTL_INV_OFFSET 0x1c +#define GC_PINMUX_DIOM4_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOM4_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOM4_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOM4_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOM4_CTL_DS_OFFSET 0x24 +#define GC_PINMUX_DIOM4_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOM4_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOM4_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOM4_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOM4_CTL_IE_OFFSET 0x24 +#define GC_PINMUX_DIOM4_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOM4_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOM4_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOM4_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOM4_CTL_PD_OFFSET 0x24 +#define GC_PINMUX_DIOM4_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOM4_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOM4_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOM4_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOM4_CTL_PU_OFFSET 0x24 +#define GC_PINMUX_DIOM4_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOM4_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOM4_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOM4_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOM4_CTL_INV_OFFSET 0x24 +#define GC_PINMUX_DIOA0_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA0_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA0_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA0_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA0_CTL_DS_OFFSET 0x2c +#define GC_PINMUX_DIOA0_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA0_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA0_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA0_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA0_CTL_IE_OFFSET 0x2c +#define GC_PINMUX_DIOA0_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA0_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA0_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA0_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA0_CTL_PD_OFFSET 0x2c +#define GC_PINMUX_DIOA0_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA0_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA0_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA0_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA0_CTL_PU_OFFSET 0x2c +#define GC_PINMUX_DIOA0_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA0_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA0_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA0_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA0_CTL_INV_OFFSET 0x2c +#define GC_PINMUX_DIOA1_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA1_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA1_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA1_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA1_CTL_DS_OFFSET 0x34 +#define GC_PINMUX_DIOA1_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA1_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA1_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA1_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA1_CTL_IE_OFFSET 0x34 +#define GC_PINMUX_DIOA1_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA1_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA1_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA1_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA1_CTL_PD_OFFSET 0x34 +#define GC_PINMUX_DIOA1_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA1_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA1_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA1_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA1_CTL_PU_OFFSET 0x34 +#define GC_PINMUX_DIOA1_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA1_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA1_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA1_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA1_CTL_INV_OFFSET 0x34 +#define GC_PINMUX_DIOA2_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA2_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA2_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA2_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA2_CTL_DS_OFFSET 0x3c +#define GC_PINMUX_DIOA2_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA2_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA2_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA2_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA2_CTL_IE_OFFSET 0x3c +#define GC_PINMUX_DIOA2_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA2_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA2_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA2_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA2_CTL_PD_OFFSET 0x3c +#define GC_PINMUX_DIOA2_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA2_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA2_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA2_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA2_CTL_PU_OFFSET 0x3c +#define GC_PINMUX_DIOA2_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA2_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA2_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA2_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA2_CTL_INV_OFFSET 0x3c +#define GC_PINMUX_DIOA3_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA3_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA3_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA3_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA3_CTL_DS_OFFSET 0x44 +#define GC_PINMUX_DIOA3_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA3_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA3_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA3_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA3_CTL_IE_OFFSET 0x44 +#define GC_PINMUX_DIOA3_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA3_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA3_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA3_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA3_CTL_PD_OFFSET 0x44 +#define GC_PINMUX_DIOA3_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA3_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA3_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA3_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA3_CTL_PU_OFFSET 0x44 +#define GC_PINMUX_DIOA3_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA3_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA3_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA3_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA3_CTL_INV_OFFSET 0x44 +#define GC_PINMUX_DIOA4_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA4_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA4_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA4_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA4_CTL_DS_OFFSET 0x4c +#define GC_PINMUX_DIOA4_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA4_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA4_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA4_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA4_CTL_IE_OFFSET 0x4c +#define GC_PINMUX_DIOA4_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA4_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA4_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA4_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA4_CTL_PD_OFFSET 0x4c +#define GC_PINMUX_DIOA4_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA4_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA4_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA4_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA4_CTL_PU_OFFSET 0x4c +#define GC_PINMUX_DIOA4_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA4_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA4_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA4_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA4_CTL_INV_OFFSET 0x4c +#define GC_PINMUX_DIOA5_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA5_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA5_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA5_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA5_CTL_DS_OFFSET 0x54 +#define GC_PINMUX_DIOA5_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA5_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA5_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA5_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA5_CTL_IE_OFFSET 0x54 +#define GC_PINMUX_DIOA5_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA5_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA5_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA5_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA5_CTL_PD_OFFSET 0x54 +#define GC_PINMUX_DIOA5_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA5_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA5_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA5_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA5_CTL_PU_OFFSET 0x54 +#define GC_PINMUX_DIOA5_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA5_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA5_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA5_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA5_CTL_INV_OFFSET 0x54 +#define GC_PINMUX_DIOA6_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA6_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA6_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA6_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA6_CTL_DS_OFFSET 0x5c +#define GC_PINMUX_DIOA6_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA6_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA6_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA6_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA6_CTL_IE_OFFSET 0x5c +#define GC_PINMUX_DIOA6_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA6_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA6_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA6_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA6_CTL_PD_OFFSET 0x5c +#define GC_PINMUX_DIOA6_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA6_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA6_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA6_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA6_CTL_PU_OFFSET 0x5c +#define GC_PINMUX_DIOA6_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA6_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA6_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA6_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA6_CTL_INV_OFFSET 0x5c +#define GC_PINMUX_DIOA7_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA7_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA7_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA7_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA7_CTL_DS_OFFSET 0x64 +#define GC_PINMUX_DIOA7_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA7_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA7_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA7_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA7_CTL_IE_OFFSET 0x64 +#define GC_PINMUX_DIOA7_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA7_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA7_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA7_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA7_CTL_PD_OFFSET 0x64 +#define GC_PINMUX_DIOA7_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA7_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA7_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA7_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA7_CTL_PU_OFFSET 0x64 +#define GC_PINMUX_DIOA7_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA7_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA7_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA7_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA7_CTL_INV_OFFSET 0x64 +#define GC_PINMUX_DIOA8_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA8_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA8_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA8_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA8_CTL_DS_OFFSET 0x6c +#define GC_PINMUX_DIOA8_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA8_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA8_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA8_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA8_CTL_IE_OFFSET 0x6c +#define GC_PINMUX_DIOA8_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA8_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA8_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA8_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA8_CTL_PD_OFFSET 0x6c +#define GC_PINMUX_DIOA8_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA8_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA8_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA8_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA8_CTL_PU_OFFSET 0x6c +#define GC_PINMUX_DIOA8_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA8_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA8_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA8_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA8_CTL_INV_OFFSET 0x6c +#define GC_PINMUX_DIOA9_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA9_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA9_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA9_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA9_CTL_DS_OFFSET 0x74 +#define GC_PINMUX_DIOA9_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA9_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA9_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA9_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA9_CTL_IE_OFFSET 0x74 +#define GC_PINMUX_DIOA9_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA9_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA9_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA9_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA9_CTL_PD_OFFSET 0x74 +#define GC_PINMUX_DIOA9_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA9_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA9_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA9_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA9_CTL_PU_OFFSET 0x74 +#define GC_PINMUX_DIOA9_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA9_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA9_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA9_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA9_CTL_INV_OFFSET 0x74 +#define GC_PINMUX_DIOA10_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA10_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA10_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA10_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA10_CTL_DS_OFFSET 0x7c +#define GC_PINMUX_DIOA10_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA10_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA10_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA10_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA10_CTL_IE_OFFSET 0x7c +#define GC_PINMUX_DIOA10_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA10_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA10_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA10_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA10_CTL_PD_OFFSET 0x7c +#define GC_PINMUX_DIOA10_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA10_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA10_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA10_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA10_CTL_PU_OFFSET 0x7c +#define GC_PINMUX_DIOA10_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA10_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA10_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA10_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA10_CTL_INV_OFFSET 0x7c +#define GC_PINMUX_DIOA11_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA11_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA11_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA11_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA11_CTL_DS_OFFSET 0x84 +#define GC_PINMUX_DIOA11_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA11_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA11_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA11_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA11_CTL_IE_OFFSET 0x84 +#define GC_PINMUX_DIOA11_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA11_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA11_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA11_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA11_CTL_PD_OFFSET 0x84 +#define GC_PINMUX_DIOA11_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA11_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA11_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA11_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA11_CTL_PU_OFFSET 0x84 +#define GC_PINMUX_DIOA11_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA11_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA11_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA11_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA11_CTL_INV_OFFSET 0x84 +#define GC_PINMUX_DIOA12_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA12_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA12_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA12_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA12_CTL_DS_OFFSET 0x8c +#define GC_PINMUX_DIOA12_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA12_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA12_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA12_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA12_CTL_IE_OFFSET 0x8c +#define GC_PINMUX_DIOA12_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA12_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA12_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA12_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA12_CTL_PD_OFFSET 0x8c +#define GC_PINMUX_DIOA12_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA12_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA12_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA12_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA12_CTL_PU_OFFSET 0x8c +#define GC_PINMUX_DIOA12_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA12_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA12_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA12_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA12_CTL_INV_OFFSET 0x8c +#define GC_PINMUX_DIOA13_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA13_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA13_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA13_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA13_CTL_DS_OFFSET 0x94 +#define GC_PINMUX_DIOA13_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA13_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA13_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA13_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA13_CTL_IE_OFFSET 0x94 +#define GC_PINMUX_DIOA13_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA13_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA13_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA13_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA13_CTL_PD_OFFSET 0x94 +#define GC_PINMUX_DIOA13_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA13_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA13_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA13_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA13_CTL_PU_OFFSET 0x94 +#define GC_PINMUX_DIOA13_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA13_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA13_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA13_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA13_CTL_INV_OFFSET 0x94 +#define GC_PINMUX_DIOA14_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOA14_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOA14_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOA14_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOA14_CTL_DS_OFFSET 0x9c +#define GC_PINMUX_DIOA14_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOA14_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOA14_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOA14_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOA14_CTL_IE_OFFSET 0x9c +#define GC_PINMUX_DIOA14_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOA14_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOA14_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOA14_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOA14_CTL_PD_OFFSET 0x9c +#define GC_PINMUX_DIOA14_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOA14_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOA14_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOA14_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOA14_CTL_PU_OFFSET 0x9c +#define GC_PINMUX_DIOA14_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOA14_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOA14_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOA14_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOA14_CTL_INV_OFFSET 0x9c +#define GC_PINMUX_DIOB0_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB0_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB0_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB0_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB0_CTL_DS_OFFSET 0xa4 +#define GC_PINMUX_DIOB0_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB0_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB0_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB0_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB0_CTL_IE_OFFSET 0xa4 +#define GC_PINMUX_DIOB0_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB0_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB0_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB0_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB0_CTL_PD_OFFSET 0xa4 +#define GC_PINMUX_DIOB0_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB0_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB0_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB0_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB0_CTL_PU_OFFSET 0xa4 +#define GC_PINMUX_DIOB0_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB0_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB0_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB0_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB0_CTL_INV_OFFSET 0xa4 +#define GC_PINMUX_DIOB1_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB1_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB1_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB1_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB1_CTL_DS_OFFSET 0xac +#define GC_PINMUX_DIOB1_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB1_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB1_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB1_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB1_CTL_IE_OFFSET 0xac +#define GC_PINMUX_DIOB1_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB1_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB1_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB1_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB1_CTL_PD_OFFSET 0xac +#define GC_PINMUX_DIOB1_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB1_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB1_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB1_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB1_CTL_PU_OFFSET 0xac +#define GC_PINMUX_DIOB1_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB1_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB1_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB1_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB1_CTL_INV_OFFSET 0xac +#define GC_PINMUX_DIOB2_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB2_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB2_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB2_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB2_CTL_DS_OFFSET 0xb4 +#define GC_PINMUX_DIOB2_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB2_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB2_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB2_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB2_CTL_IE_OFFSET 0xb4 +#define GC_PINMUX_DIOB2_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB2_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB2_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB2_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB2_CTL_PD_OFFSET 0xb4 +#define GC_PINMUX_DIOB2_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB2_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB2_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB2_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB2_CTL_PU_OFFSET 0xb4 +#define GC_PINMUX_DIOB2_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB2_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB2_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB2_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB2_CTL_INV_OFFSET 0xb4 +#define GC_PINMUX_DIOB3_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB3_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB3_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB3_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB3_CTL_DS_OFFSET 0xbc +#define GC_PINMUX_DIOB3_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB3_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB3_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB3_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB3_CTL_IE_OFFSET 0xbc +#define GC_PINMUX_DIOB3_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB3_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB3_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB3_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB3_CTL_PD_OFFSET 0xbc +#define GC_PINMUX_DIOB3_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB3_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB3_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB3_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB3_CTL_PU_OFFSET 0xbc +#define GC_PINMUX_DIOB3_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB3_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB3_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB3_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB3_CTL_INV_OFFSET 0xbc +#define GC_PINMUX_DIOB4_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB4_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB4_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB4_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB4_CTL_DS_OFFSET 0xc4 +#define GC_PINMUX_DIOB4_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB4_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB4_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB4_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB4_CTL_IE_OFFSET 0xc4 +#define GC_PINMUX_DIOB4_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB4_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB4_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB4_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB4_CTL_PD_OFFSET 0xc4 +#define GC_PINMUX_DIOB4_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB4_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB4_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB4_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB4_CTL_PU_OFFSET 0xc4 +#define GC_PINMUX_DIOB4_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB4_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB4_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB4_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB4_CTL_INV_OFFSET 0xc4 +#define GC_PINMUX_DIOB5_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB5_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB5_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB5_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB5_CTL_DS_OFFSET 0xcc +#define GC_PINMUX_DIOB5_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB5_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB5_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB5_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB5_CTL_IE_OFFSET 0xcc +#define GC_PINMUX_DIOB5_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB5_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB5_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB5_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB5_CTL_PD_OFFSET 0xcc +#define GC_PINMUX_DIOB5_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB5_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB5_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB5_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB5_CTL_PU_OFFSET 0xcc +#define GC_PINMUX_DIOB5_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB5_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB5_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB5_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB5_CTL_INV_OFFSET 0xcc +#define GC_PINMUX_DIOB6_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB6_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB6_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB6_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB6_CTL_DS_OFFSET 0xd4 +#define GC_PINMUX_DIOB6_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB6_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB6_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB6_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB6_CTL_IE_OFFSET 0xd4 +#define GC_PINMUX_DIOB6_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB6_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB6_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB6_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB6_CTL_PD_OFFSET 0xd4 +#define GC_PINMUX_DIOB6_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB6_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB6_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB6_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB6_CTL_PU_OFFSET 0xd4 +#define GC_PINMUX_DIOB6_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB6_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB6_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB6_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB6_CTL_INV_OFFSET 0xd4 +#define GC_PINMUX_DIOB7_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB7_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB7_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB7_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB7_CTL_DS_OFFSET 0xdc +#define GC_PINMUX_DIOB7_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB7_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB7_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB7_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB7_CTL_IE_OFFSET 0xdc +#define GC_PINMUX_DIOB7_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB7_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB7_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB7_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB7_CTL_PD_OFFSET 0xdc +#define GC_PINMUX_DIOB7_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB7_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB7_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB7_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB7_CTL_PU_OFFSET 0xdc +#define GC_PINMUX_DIOB7_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB7_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB7_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB7_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB7_CTL_INV_OFFSET 0xdc +#define GC_PINMUX_DIOB8_CTL_DS_LSB 0x0 +#define GC_PINMUX_DIOB8_CTL_DS_MASK 0x3 +#define GC_PINMUX_DIOB8_CTL_DS_SIZE 0x2 +#define GC_PINMUX_DIOB8_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_DIOB8_CTL_DS_OFFSET 0xe4 +#define GC_PINMUX_DIOB8_CTL_IE_LSB 0x2 +#define GC_PINMUX_DIOB8_CTL_IE_MASK 0x4 +#define GC_PINMUX_DIOB8_CTL_IE_SIZE 0x1 +#define GC_PINMUX_DIOB8_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_DIOB8_CTL_IE_OFFSET 0xe4 +#define GC_PINMUX_DIOB8_CTL_PD_LSB 0x3 +#define GC_PINMUX_DIOB8_CTL_PD_MASK 0x8 +#define GC_PINMUX_DIOB8_CTL_PD_SIZE 0x1 +#define GC_PINMUX_DIOB8_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_DIOB8_CTL_PD_OFFSET 0xe4 +#define GC_PINMUX_DIOB8_CTL_PU_LSB 0x4 +#define GC_PINMUX_DIOB8_CTL_PU_MASK 0x10 +#define GC_PINMUX_DIOB8_CTL_PU_SIZE 0x1 +#define GC_PINMUX_DIOB8_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_DIOB8_CTL_PU_OFFSET 0xe4 +#define GC_PINMUX_DIOB8_CTL_INV_LSB 0x5 +#define GC_PINMUX_DIOB8_CTL_INV_MASK 0x20 +#define GC_PINMUX_DIOB8_CTL_INV_SIZE 0x1 +#define GC_PINMUX_DIOB8_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_DIOB8_CTL_INV_OFFSET 0xe4 +#define GC_PINMUX_RTCXOP_CTL_DS_LSB 0x0 +#define GC_PINMUX_RTCXOP_CTL_DS_MASK 0x3 +#define GC_PINMUX_RTCXOP_CTL_DS_SIZE 0x2 +#define GC_PINMUX_RTCXOP_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_RTCXOP_CTL_DS_OFFSET 0xec +#define GC_PINMUX_RTCXOP_CTL_IE_LSB 0x2 +#define GC_PINMUX_RTCXOP_CTL_IE_MASK 0x4 +#define GC_PINMUX_RTCXOP_CTL_IE_SIZE 0x1 +#define GC_PINMUX_RTCXOP_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_RTCXOP_CTL_IE_OFFSET 0xec +#define GC_PINMUX_RTCXOP_CTL_PD_LSB 0x3 +#define GC_PINMUX_RTCXOP_CTL_PD_MASK 0x8 +#define GC_PINMUX_RTCXOP_CTL_PD_SIZE 0x1 +#define GC_PINMUX_RTCXOP_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_RTCXOP_CTL_PD_OFFSET 0xec +#define GC_PINMUX_RTCXOP_CTL_PU_LSB 0x4 +#define GC_PINMUX_RTCXOP_CTL_PU_MASK 0x10 +#define GC_PINMUX_RTCXOP_CTL_PU_SIZE 0x1 +#define GC_PINMUX_RTCXOP_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_RTCXOP_CTL_PU_OFFSET 0xec +#define GC_PINMUX_RTCXOP_CTL_INV_LSB 0x5 +#define GC_PINMUX_RTCXOP_CTL_INV_MASK 0x20 +#define GC_PINMUX_RTCXOP_CTL_INV_SIZE 0x1 +#define GC_PINMUX_RTCXOP_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_RTCXOP_CTL_INV_OFFSET 0xec +#define GC_PINMUX_SWDPTRACE_CTL_DS_LSB 0x0 +#define GC_PINMUX_SWDPTRACE_CTL_DS_MASK 0x3 +#define GC_PINMUX_SWDPTRACE_CTL_DS_SIZE 0x2 +#define GC_PINMUX_SWDPTRACE_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_SWDPTRACE_CTL_DS_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_IE_LSB 0x2 +#define GC_PINMUX_SWDPTRACE_CTL_IE_MASK 0x4 +#define GC_PINMUX_SWDPTRACE_CTL_IE_SIZE 0x1 +#define GC_PINMUX_SWDPTRACE_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_SWDPTRACE_CTL_IE_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_PD_LSB 0x3 +#define GC_PINMUX_SWDPTRACE_CTL_PD_MASK 0x8 +#define GC_PINMUX_SWDPTRACE_CTL_PD_SIZE 0x1 +#define GC_PINMUX_SWDPTRACE_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_SWDPTRACE_CTL_PD_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_PU_LSB 0x4 +#define GC_PINMUX_SWDPTRACE_CTL_PU_MASK 0x10 +#define GC_PINMUX_SWDPTRACE_CTL_PU_SIZE 0x1 +#define GC_PINMUX_SWDPTRACE_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_SWDPTRACE_CTL_PU_OFFSET 0xf4 +#define GC_PINMUX_SWDPTRACE_CTL_INV_LSB 0x5 +#define GC_PINMUX_SWDPTRACE_CTL_INV_MASK 0x20 +#define GC_PINMUX_SWDPTRACE_CTL_INV_SIZE 0x1 +#define GC_PINMUX_SWDPTRACE_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_SWDPTRACE_CTL_INV_OFFSET 0xf4 +#define GC_PINMUX_SWDPDATA_CTL_DS_LSB 0x0 +#define GC_PINMUX_SWDPDATA_CTL_DS_MASK 0x3 +#define GC_PINMUX_SWDPDATA_CTL_DS_SIZE 0x2 +#define GC_PINMUX_SWDPDATA_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_SWDPDATA_CTL_DS_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_IE_LSB 0x2 +#define GC_PINMUX_SWDPDATA_CTL_IE_MASK 0x4 +#define GC_PINMUX_SWDPDATA_CTL_IE_SIZE 0x1 +#define GC_PINMUX_SWDPDATA_CTL_IE_DEFAULT 0x1 +#define GC_PINMUX_SWDPDATA_CTL_IE_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_PD_LSB 0x3 +#define GC_PINMUX_SWDPDATA_CTL_PD_MASK 0x8 +#define GC_PINMUX_SWDPDATA_CTL_PD_SIZE 0x1 +#define GC_PINMUX_SWDPDATA_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_SWDPDATA_CTL_PD_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_PU_LSB 0x4 +#define GC_PINMUX_SWDPDATA_CTL_PU_MASK 0x10 +#define GC_PINMUX_SWDPDATA_CTL_PU_SIZE 0x1 +#define GC_PINMUX_SWDPDATA_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_SWDPDATA_CTL_PU_OFFSET 0xfc +#define GC_PINMUX_SWDPDATA_CTL_INV_LSB 0x5 +#define GC_PINMUX_SWDPDATA_CTL_INV_MASK 0x20 +#define GC_PINMUX_SWDPDATA_CTL_INV_SIZE 0x1 +#define GC_PINMUX_SWDPDATA_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_SWDPDATA_CTL_INV_OFFSET 0xfc +#define GC_PINMUX_TESTMODE_CTL_DS_LSB 0x0 +#define GC_PINMUX_TESTMODE_CTL_DS_MASK 0x3 +#define GC_PINMUX_TESTMODE_CTL_DS_SIZE 0x2 +#define GC_PINMUX_TESTMODE_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_TESTMODE_CTL_DS_OFFSET 0x104 +#define GC_PINMUX_TESTMODE_CTL_IE_LSB 0x2 +#define GC_PINMUX_TESTMODE_CTL_IE_MASK 0x4 +#define GC_PINMUX_TESTMODE_CTL_IE_SIZE 0x1 +#define GC_PINMUX_TESTMODE_CTL_IE_DEFAULT 0x1 +#define GC_PINMUX_TESTMODE_CTL_IE_OFFSET 0x104 +#define GC_PINMUX_TESTMODE_CTL_PD_LSB 0x3 +#define GC_PINMUX_TESTMODE_CTL_PD_MASK 0x8 +#define GC_PINMUX_TESTMODE_CTL_PD_SIZE 0x1 +#define GC_PINMUX_TESTMODE_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_TESTMODE_CTL_PD_OFFSET 0x104 +#define GC_PINMUX_TESTMODE_CTL_PU_LSB 0x4 +#define GC_PINMUX_TESTMODE_CTL_PU_MASK 0x10 +#define GC_PINMUX_TESTMODE_CTL_PU_SIZE 0x1 +#define GC_PINMUX_TESTMODE_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_TESTMODE_CTL_PU_OFFSET 0x104 +#define GC_PINMUX_TESTMODE_CTL_INV_LSB 0x5 +#define GC_PINMUX_TESTMODE_CTL_INV_MASK 0x20 +#define GC_PINMUX_TESTMODE_CTL_INV_SIZE 0x1 +#define GC_PINMUX_TESTMODE_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_TESTMODE_CTL_INV_OFFSET 0x104 +#define GC_PINMUX_RESETB_CTL_DS_LSB 0x0 +#define GC_PINMUX_RESETB_CTL_DS_MASK 0x3 +#define GC_PINMUX_RESETB_CTL_DS_SIZE 0x2 +#define GC_PINMUX_RESETB_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_RESETB_CTL_DS_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_IE_LSB 0x2 +#define GC_PINMUX_RESETB_CTL_IE_MASK 0x4 +#define GC_PINMUX_RESETB_CTL_IE_SIZE 0x1 +#define GC_PINMUX_RESETB_CTL_IE_DEFAULT 0x1 +#define GC_PINMUX_RESETB_CTL_IE_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_PD_LSB 0x3 +#define GC_PINMUX_RESETB_CTL_PD_MASK 0x8 +#define GC_PINMUX_RESETB_CTL_PD_SIZE 0x1 +#define GC_PINMUX_RESETB_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_RESETB_CTL_PD_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_PU_LSB 0x4 +#define GC_PINMUX_RESETB_CTL_PU_MASK 0x10 +#define GC_PINMUX_RESETB_CTL_PU_SIZE 0x1 +#define GC_PINMUX_RESETB_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_RESETB_CTL_PU_OFFSET 0x10c +#define GC_PINMUX_RESETB_CTL_INV_LSB 0x5 +#define GC_PINMUX_RESETB_CTL_INV_MASK 0x20 +#define GC_PINMUX_RESETB_CTL_INV_SIZE 0x1 +#define GC_PINMUX_RESETB_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_RESETB_CTL_INV_OFFSET 0x10c +#define GC_PINMUX_VIO0_CTL_DS_LSB 0x0 +#define GC_PINMUX_VIO0_CTL_DS_MASK 0x3 +#define GC_PINMUX_VIO0_CTL_DS_SIZE 0x2 +#define GC_PINMUX_VIO0_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_VIO0_CTL_DS_OFFSET 0x114 +#define GC_PINMUX_VIO0_CTL_IE_LSB 0x2 +#define GC_PINMUX_VIO0_CTL_IE_MASK 0x4 +#define GC_PINMUX_VIO0_CTL_IE_SIZE 0x1 +#define GC_PINMUX_VIO0_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_IE_OFFSET 0x114 +#define GC_PINMUX_VIO0_CTL_PD_LSB 0x3 +#define GC_PINMUX_VIO0_CTL_PD_MASK 0x8 +#define GC_PINMUX_VIO0_CTL_PD_SIZE 0x1 +#define GC_PINMUX_VIO0_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_PD_OFFSET 0x114 +#define GC_PINMUX_VIO0_CTL_PU_LSB 0x4 +#define GC_PINMUX_VIO0_CTL_PU_MASK 0x10 +#define GC_PINMUX_VIO0_CTL_PU_SIZE 0x1 +#define GC_PINMUX_VIO0_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_PU_OFFSET 0x114 +#define GC_PINMUX_VIO0_CTL_INV_LSB 0x5 +#define GC_PINMUX_VIO0_CTL_INV_MASK 0x20 +#define GC_PINMUX_VIO0_CTL_INV_SIZE 0x1 +#define GC_PINMUX_VIO0_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_VIO0_CTL_INV_OFFSET 0x114 +#define GC_PINMUX_VIO1_CTL_DS_LSB 0x0 +#define GC_PINMUX_VIO1_CTL_DS_MASK 0x3 +#define GC_PINMUX_VIO1_CTL_DS_SIZE 0x2 +#define GC_PINMUX_VIO1_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_VIO1_CTL_DS_OFFSET 0x11c +#define GC_PINMUX_VIO1_CTL_IE_LSB 0x2 +#define GC_PINMUX_VIO1_CTL_IE_MASK 0x4 +#define GC_PINMUX_VIO1_CTL_IE_SIZE 0x1 +#define GC_PINMUX_VIO1_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_IE_OFFSET 0x11c +#define GC_PINMUX_VIO1_CTL_PD_LSB 0x3 +#define GC_PINMUX_VIO1_CTL_PD_MASK 0x8 +#define GC_PINMUX_VIO1_CTL_PD_SIZE 0x1 +#define GC_PINMUX_VIO1_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_PD_OFFSET 0x11c +#define GC_PINMUX_VIO1_CTL_PU_LSB 0x4 +#define GC_PINMUX_VIO1_CTL_PU_MASK 0x10 +#define GC_PINMUX_VIO1_CTL_PU_SIZE 0x1 +#define GC_PINMUX_VIO1_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_PU_OFFSET 0x11c +#define GC_PINMUX_VIO1_CTL_INV_LSB 0x5 +#define GC_PINMUX_VIO1_CTL_INV_MASK 0x20 +#define GC_PINMUX_VIO1_CTL_INV_SIZE 0x1 +#define GC_PINMUX_VIO1_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_VIO1_CTL_INV_OFFSET 0x11c +#define GC_PINMUX_TDI_CTL_DS_LSB 0x0 +#define GC_PINMUX_TDI_CTL_DS_MASK 0x3 +#define GC_PINMUX_TDI_CTL_DS_SIZE 0x2 +#define GC_PINMUX_TDI_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_TDI_CTL_DS_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_IE_LSB 0x2 +#define GC_PINMUX_TDI_CTL_IE_MASK 0x4 +#define GC_PINMUX_TDI_CTL_IE_SIZE 0x1 +#define GC_PINMUX_TDI_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_TDI_CTL_IE_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_PD_LSB 0x3 +#define GC_PINMUX_TDI_CTL_PD_MASK 0x8 +#define GC_PINMUX_TDI_CTL_PD_SIZE 0x1 +#define GC_PINMUX_TDI_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_TDI_CTL_PD_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_PU_LSB 0x4 +#define GC_PINMUX_TDI_CTL_PU_MASK 0x10 +#define GC_PINMUX_TDI_CTL_PU_SIZE 0x1 +#define GC_PINMUX_TDI_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_TDI_CTL_PU_OFFSET 0x124 +#define GC_PINMUX_TDI_CTL_INV_LSB 0x5 +#define GC_PINMUX_TDI_CTL_INV_MASK 0x20 +#define GC_PINMUX_TDI_CTL_INV_SIZE 0x1 +#define GC_PINMUX_TDI_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_TDI_CTL_INV_OFFSET 0x124 +#define GC_PINMUX_TMS_CTL_DS_LSB 0x0 +#define GC_PINMUX_TMS_CTL_DS_MASK 0x3 +#define GC_PINMUX_TMS_CTL_DS_SIZE 0x2 +#define GC_PINMUX_TMS_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_TMS_CTL_DS_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_IE_LSB 0x2 +#define GC_PINMUX_TMS_CTL_IE_MASK 0x4 +#define GC_PINMUX_TMS_CTL_IE_SIZE 0x1 +#define GC_PINMUX_TMS_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_TMS_CTL_IE_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_PD_LSB 0x3 +#define GC_PINMUX_TMS_CTL_PD_MASK 0x8 +#define GC_PINMUX_TMS_CTL_PD_SIZE 0x1 +#define GC_PINMUX_TMS_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_TMS_CTL_PD_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_PU_LSB 0x4 +#define GC_PINMUX_TMS_CTL_PU_MASK 0x10 +#define GC_PINMUX_TMS_CTL_PU_SIZE 0x1 +#define GC_PINMUX_TMS_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_TMS_CTL_PU_OFFSET 0x12c +#define GC_PINMUX_TMS_CTL_INV_LSB 0x5 +#define GC_PINMUX_TMS_CTL_INV_MASK 0x20 +#define GC_PINMUX_TMS_CTL_INV_SIZE 0x1 +#define GC_PINMUX_TMS_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_TMS_CTL_INV_OFFSET 0x12c +#define GC_PINMUX_TCK_CTL_DS_LSB 0x0 +#define GC_PINMUX_TCK_CTL_DS_MASK 0x3 +#define GC_PINMUX_TCK_CTL_DS_SIZE 0x2 +#define GC_PINMUX_TCK_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_TCK_CTL_DS_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_IE_LSB 0x2 +#define GC_PINMUX_TCK_CTL_IE_MASK 0x4 +#define GC_PINMUX_TCK_CTL_IE_SIZE 0x1 +#define GC_PINMUX_TCK_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_TCK_CTL_IE_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_PD_LSB 0x3 +#define GC_PINMUX_TCK_CTL_PD_MASK 0x8 +#define GC_PINMUX_TCK_CTL_PD_SIZE 0x1 +#define GC_PINMUX_TCK_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_TCK_CTL_PD_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_PU_LSB 0x4 +#define GC_PINMUX_TCK_CTL_PU_MASK 0x10 +#define GC_PINMUX_TCK_CTL_PU_SIZE 0x1 +#define GC_PINMUX_TCK_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_TCK_CTL_PU_OFFSET 0x134 +#define GC_PINMUX_TCK_CTL_INV_LSB 0x5 +#define GC_PINMUX_TCK_CTL_INV_MASK 0x20 +#define GC_PINMUX_TCK_CTL_INV_SIZE 0x1 +#define GC_PINMUX_TCK_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_TCK_CTL_INV_OFFSET 0x134 +#define GC_PINMUX_TDO_CTL_DS_LSB 0x0 +#define GC_PINMUX_TDO_CTL_DS_MASK 0x3 +#define GC_PINMUX_TDO_CTL_DS_SIZE 0x2 +#define GC_PINMUX_TDO_CTL_DS_DEFAULT 0x3 +#define GC_PINMUX_TDO_CTL_DS_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_IE_LSB 0x2 +#define GC_PINMUX_TDO_CTL_IE_MASK 0x4 +#define GC_PINMUX_TDO_CTL_IE_SIZE 0x1 +#define GC_PINMUX_TDO_CTL_IE_DEFAULT 0x0 +#define GC_PINMUX_TDO_CTL_IE_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_PD_LSB 0x3 +#define GC_PINMUX_TDO_CTL_PD_MASK 0x8 +#define GC_PINMUX_TDO_CTL_PD_SIZE 0x1 +#define GC_PINMUX_TDO_CTL_PD_DEFAULT 0x0 +#define GC_PINMUX_TDO_CTL_PD_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_PU_LSB 0x4 +#define GC_PINMUX_TDO_CTL_PU_MASK 0x10 +#define GC_PINMUX_TDO_CTL_PU_SIZE 0x1 +#define GC_PINMUX_TDO_CTL_PU_DEFAULT 0x0 +#define GC_PINMUX_TDO_CTL_PU_OFFSET 0x13c +#define GC_PINMUX_TDO_CTL_INV_LSB 0x5 +#define GC_PINMUX_TDO_CTL_INV_MASK 0x20 +#define GC_PINMUX_TDO_CTL_INV_SIZE 0x1 +#define GC_PINMUX_TDO_CTL_INV_DEFAULT 0x0 +#define GC_PINMUX_TDO_CTL_INV_OFFSET 0x13c +#define GC_PINMUX_SETHOLD0_DIOM0_LSB 0x0 +#define GC_PINMUX_SETHOLD0_DIOM0_MASK 0x1 +#define GC_PINMUX_SETHOLD0_DIOM0_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOM0_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOM0_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOM1_LSB 0x1 +#define GC_PINMUX_SETHOLD0_DIOM1_MASK 0x2 +#define GC_PINMUX_SETHOLD0_DIOM1_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOM1_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOM1_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOM2_LSB 0x2 +#define GC_PINMUX_SETHOLD0_DIOM2_MASK 0x4 +#define GC_PINMUX_SETHOLD0_DIOM2_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOM2_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOM2_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOM3_LSB 0x3 +#define GC_PINMUX_SETHOLD0_DIOM3_MASK 0x8 +#define GC_PINMUX_SETHOLD0_DIOM3_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOM3_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOM3_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOM4_LSB 0x4 +#define GC_PINMUX_SETHOLD0_DIOM4_MASK 0x10 +#define GC_PINMUX_SETHOLD0_DIOM4_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOM4_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOM4_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA0_LSB 0x5 +#define GC_PINMUX_SETHOLD0_DIOA0_MASK 0x20 +#define GC_PINMUX_SETHOLD0_DIOA0_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA0_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA0_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA1_LSB 0x6 +#define GC_PINMUX_SETHOLD0_DIOA1_MASK 0x40 +#define GC_PINMUX_SETHOLD0_DIOA1_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA1_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA1_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA2_LSB 0x7 +#define GC_PINMUX_SETHOLD0_DIOA2_MASK 0x80 +#define GC_PINMUX_SETHOLD0_DIOA2_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA2_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA2_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA3_LSB 0x8 +#define GC_PINMUX_SETHOLD0_DIOA3_MASK 0x100 +#define GC_PINMUX_SETHOLD0_DIOA3_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA3_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA3_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA4_LSB 0x9 +#define GC_PINMUX_SETHOLD0_DIOA4_MASK 0x200 +#define GC_PINMUX_SETHOLD0_DIOA4_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA4_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA4_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA5_LSB 0xa +#define GC_PINMUX_SETHOLD0_DIOA5_MASK 0x400 +#define GC_PINMUX_SETHOLD0_DIOA5_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA5_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA5_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA6_LSB 0xb +#define GC_PINMUX_SETHOLD0_DIOA6_MASK 0x800 +#define GC_PINMUX_SETHOLD0_DIOA6_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA6_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA6_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA7_LSB 0xc +#define GC_PINMUX_SETHOLD0_DIOA7_MASK 0x1000 +#define GC_PINMUX_SETHOLD0_DIOA7_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA7_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA7_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA8_LSB 0xd +#define GC_PINMUX_SETHOLD0_DIOA8_MASK 0x2000 +#define GC_PINMUX_SETHOLD0_DIOA8_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA8_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA8_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA9_LSB 0xe +#define GC_PINMUX_SETHOLD0_DIOA9_MASK 0x4000 +#define GC_PINMUX_SETHOLD0_DIOA9_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA9_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA9_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA10_LSB 0xf +#define GC_PINMUX_SETHOLD0_DIOA10_MASK 0x8000 +#define GC_PINMUX_SETHOLD0_DIOA10_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA10_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA10_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA11_LSB 0x10 +#define GC_PINMUX_SETHOLD0_DIOA11_MASK 0x10000 +#define GC_PINMUX_SETHOLD0_DIOA11_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA11_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA11_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA12_LSB 0x11 +#define GC_PINMUX_SETHOLD0_DIOA12_MASK 0x20000 +#define GC_PINMUX_SETHOLD0_DIOA12_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA12_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA12_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA13_LSB 0x12 +#define GC_PINMUX_SETHOLD0_DIOA13_MASK 0x40000 +#define GC_PINMUX_SETHOLD0_DIOA13_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA13_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA13_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOA14_LSB 0x13 +#define GC_PINMUX_SETHOLD0_DIOA14_MASK 0x80000 +#define GC_PINMUX_SETHOLD0_DIOA14_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOA14_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOA14_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB0_LSB 0x14 +#define GC_PINMUX_SETHOLD0_DIOB0_MASK 0x100000 +#define GC_PINMUX_SETHOLD0_DIOB0_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB0_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB0_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB1_LSB 0x15 +#define GC_PINMUX_SETHOLD0_DIOB1_MASK 0x200000 +#define GC_PINMUX_SETHOLD0_DIOB1_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB1_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB1_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB2_LSB 0x16 +#define GC_PINMUX_SETHOLD0_DIOB2_MASK 0x400000 +#define GC_PINMUX_SETHOLD0_DIOB2_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB2_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB2_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB3_LSB 0x17 +#define GC_PINMUX_SETHOLD0_DIOB3_MASK 0x800000 +#define GC_PINMUX_SETHOLD0_DIOB3_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB3_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB3_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB4_LSB 0x18 +#define GC_PINMUX_SETHOLD0_DIOB4_MASK 0x1000000 +#define GC_PINMUX_SETHOLD0_DIOB4_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB4_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB4_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB5_LSB 0x19 +#define GC_PINMUX_SETHOLD0_DIOB5_MASK 0x2000000 +#define GC_PINMUX_SETHOLD0_DIOB5_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB5_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB5_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB6_LSB 0x1a +#define GC_PINMUX_SETHOLD0_DIOB6_MASK 0x4000000 +#define GC_PINMUX_SETHOLD0_DIOB6_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB6_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB6_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB7_LSB 0x1b +#define GC_PINMUX_SETHOLD0_DIOB7_MASK 0x8000000 +#define GC_PINMUX_SETHOLD0_DIOB7_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB7_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB7_OFFSET 0x140 +#define GC_PINMUX_SETHOLD0_DIOB8_LSB 0x1c +#define GC_PINMUX_SETHOLD0_DIOB8_MASK 0x10000000 +#define GC_PINMUX_SETHOLD0_DIOB8_SIZE 0x1 +#define GC_PINMUX_SETHOLD0_DIOB8_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD0_DIOB8_OFFSET 0x140 +#define GC_PINMUX_SETHOLD1_RTCXOP_LSB 0xc +#define GC_PINMUX_SETHOLD1_RTCXOP_MASK 0x1000 +#define GC_PINMUX_SETHOLD1_RTCXOP_SIZE 0x1 +#define GC_PINMUX_SETHOLD1_RTCXOP_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD1_RTCXOP_OFFSET 0x144 +#define GC_PINMUX_SETHOLD1_SWDPTRACE_LSB 0xd +#define GC_PINMUX_SETHOLD1_SWDPTRACE_MASK 0x2000 +#define GC_PINMUX_SETHOLD1_SWDPTRACE_SIZE 0x1 +#define GC_PINMUX_SETHOLD1_SWDPTRACE_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD1_SWDPTRACE_OFFSET 0x144 +#define GC_PINMUX_SETHOLD1_SWDPDATA_LSB 0xe +#define GC_PINMUX_SETHOLD1_SWDPDATA_MASK 0x4000 +#define GC_PINMUX_SETHOLD1_SWDPDATA_SIZE 0x1 +#define GC_PINMUX_SETHOLD1_SWDPDATA_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD1_SWDPDATA_OFFSET 0x144 +#define GC_PINMUX_SETHOLD1_VIO0_LSB 0x12 +#define GC_PINMUX_SETHOLD1_VIO0_MASK 0x40000 +#define GC_PINMUX_SETHOLD1_VIO0_SIZE 0x1 +#define GC_PINMUX_SETHOLD1_VIO0_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD1_VIO0_OFFSET 0x144 +#define GC_PINMUX_SETHOLD1_VIO1_LSB 0x13 +#define GC_PINMUX_SETHOLD1_VIO1_MASK 0x80000 +#define GC_PINMUX_SETHOLD1_VIO1_SIZE 0x1 +#define GC_PINMUX_SETHOLD1_VIO1_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD1_VIO1_OFFSET 0x144 +#define GC_PINMUX_SETHOLD1_TDO_LSB 0x17 +#define GC_PINMUX_SETHOLD1_TDO_MASK 0x800000 +#define GC_PINMUX_SETHOLD1_TDO_SIZE 0x1 +#define GC_PINMUX_SETHOLD1_TDO_DEFAULT 0x0 +#define GC_PINMUX_SETHOLD1_TDO_OFFSET 0x144 +#define GC_PINMUX_CLRHOLD0_DIOM0_LSB 0x0 +#define GC_PINMUX_CLRHOLD0_DIOM0_MASK 0x1 +#define GC_PINMUX_CLRHOLD0_DIOM0_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOM0_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOM0_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOM1_LSB 0x1 +#define GC_PINMUX_CLRHOLD0_DIOM1_MASK 0x2 +#define GC_PINMUX_CLRHOLD0_DIOM1_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOM1_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOM1_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOM2_LSB 0x2 +#define GC_PINMUX_CLRHOLD0_DIOM2_MASK 0x4 +#define GC_PINMUX_CLRHOLD0_DIOM2_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOM2_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOM2_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOM3_LSB 0x3 +#define GC_PINMUX_CLRHOLD0_DIOM3_MASK 0x8 +#define GC_PINMUX_CLRHOLD0_DIOM3_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOM3_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOM3_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOM4_LSB 0x4 +#define GC_PINMUX_CLRHOLD0_DIOM4_MASK 0x10 +#define GC_PINMUX_CLRHOLD0_DIOM4_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOM4_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOM4_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA0_LSB 0x5 +#define GC_PINMUX_CLRHOLD0_DIOA0_MASK 0x20 +#define GC_PINMUX_CLRHOLD0_DIOA0_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA0_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA0_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA1_LSB 0x6 +#define GC_PINMUX_CLRHOLD0_DIOA1_MASK 0x40 +#define GC_PINMUX_CLRHOLD0_DIOA1_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA1_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA1_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA2_LSB 0x7 +#define GC_PINMUX_CLRHOLD0_DIOA2_MASK 0x80 +#define GC_PINMUX_CLRHOLD0_DIOA2_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA2_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA2_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA3_LSB 0x8 +#define GC_PINMUX_CLRHOLD0_DIOA3_MASK 0x100 +#define GC_PINMUX_CLRHOLD0_DIOA3_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA3_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA3_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA4_LSB 0x9 +#define GC_PINMUX_CLRHOLD0_DIOA4_MASK 0x200 +#define GC_PINMUX_CLRHOLD0_DIOA4_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA4_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA4_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA5_LSB 0xa +#define GC_PINMUX_CLRHOLD0_DIOA5_MASK 0x400 +#define GC_PINMUX_CLRHOLD0_DIOA5_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA5_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA5_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA6_LSB 0xb +#define GC_PINMUX_CLRHOLD0_DIOA6_MASK 0x800 +#define GC_PINMUX_CLRHOLD0_DIOA6_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA6_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA6_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA7_LSB 0xc +#define GC_PINMUX_CLRHOLD0_DIOA7_MASK 0x1000 +#define GC_PINMUX_CLRHOLD0_DIOA7_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA7_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA7_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA8_LSB 0xd +#define GC_PINMUX_CLRHOLD0_DIOA8_MASK 0x2000 +#define GC_PINMUX_CLRHOLD0_DIOA8_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA8_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA8_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA9_LSB 0xe +#define GC_PINMUX_CLRHOLD0_DIOA9_MASK 0x4000 +#define GC_PINMUX_CLRHOLD0_DIOA9_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA9_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA9_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA10_LSB 0xf +#define GC_PINMUX_CLRHOLD0_DIOA10_MASK 0x8000 +#define GC_PINMUX_CLRHOLD0_DIOA10_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA10_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA10_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA11_LSB 0x10 +#define GC_PINMUX_CLRHOLD0_DIOA11_MASK 0x10000 +#define GC_PINMUX_CLRHOLD0_DIOA11_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA11_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA11_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA12_LSB 0x11 +#define GC_PINMUX_CLRHOLD0_DIOA12_MASK 0x20000 +#define GC_PINMUX_CLRHOLD0_DIOA12_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA12_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA12_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA13_LSB 0x12 +#define GC_PINMUX_CLRHOLD0_DIOA13_MASK 0x40000 +#define GC_PINMUX_CLRHOLD0_DIOA13_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA13_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA13_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOA14_LSB 0x13 +#define GC_PINMUX_CLRHOLD0_DIOA14_MASK 0x80000 +#define GC_PINMUX_CLRHOLD0_DIOA14_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOA14_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOA14_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB0_LSB 0x14 +#define GC_PINMUX_CLRHOLD0_DIOB0_MASK 0x100000 +#define GC_PINMUX_CLRHOLD0_DIOB0_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB0_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB0_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB1_LSB 0x15 +#define GC_PINMUX_CLRHOLD0_DIOB1_MASK 0x200000 +#define GC_PINMUX_CLRHOLD0_DIOB1_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB1_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB1_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB2_LSB 0x16 +#define GC_PINMUX_CLRHOLD0_DIOB2_MASK 0x400000 +#define GC_PINMUX_CLRHOLD0_DIOB2_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB2_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB2_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB3_LSB 0x17 +#define GC_PINMUX_CLRHOLD0_DIOB3_MASK 0x800000 +#define GC_PINMUX_CLRHOLD0_DIOB3_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB3_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB3_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB4_LSB 0x18 +#define GC_PINMUX_CLRHOLD0_DIOB4_MASK 0x1000000 +#define GC_PINMUX_CLRHOLD0_DIOB4_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB4_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB4_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB5_LSB 0x19 +#define GC_PINMUX_CLRHOLD0_DIOB5_MASK 0x2000000 +#define GC_PINMUX_CLRHOLD0_DIOB5_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB5_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB5_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB6_LSB 0x1a +#define GC_PINMUX_CLRHOLD0_DIOB6_MASK 0x4000000 +#define GC_PINMUX_CLRHOLD0_DIOB6_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB6_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB6_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB7_LSB 0x1b +#define GC_PINMUX_CLRHOLD0_DIOB7_MASK 0x8000000 +#define GC_PINMUX_CLRHOLD0_DIOB7_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB7_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB7_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD0_DIOB8_LSB 0x1c +#define GC_PINMUX_CLRHOLD0_DIOB8_MASK 0x10000000 +#define GC_PINMUX_CLRHOLD0_DIOB8_SIZE 0x1 +#define GC_PINMUX_CLRHOLD0_DIOB8_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD0_DIOB8_OFFSET 0x148 +#define GC_PINMUX_CLRHOLD1_RTCXOP_LSB 0xc +#define GC_PINMUX_CLRHOLD1_RTCXOP_MASK 0x1000 +#define GC_PINMUX_CLRHOLD1_RTCXOP_SIZE 0x1 +#define GC_PINMUX_CLRHOLD1_RTCXOP_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD1_RTCXOP_OFFSET 0x14c +#define GC_PINMUX_CLRHOLD1_SWDPTRACE_LSB 0xd +#define GC_PINMUX_CLRHOLD1_SWDPTRACE_MASK 0x2000 +#define GC_PINMUX_CLRHOLD1_SWDPTRACE_SIZE 0x1 +#define GC_PINMUX_CLRHOLD1_SWDPTRACE_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD1_SWDPTRACE_OFFSET 0x14c +#define GC_PINMUX_CLRHOLD1_SWDPDATA_LSB 0xe +#define GC_PINMUX_CLRHOLD1_SWDPDATA_MASK 0x4000 +#define GC_PINMUX_CLRHOLD1_SWDPDATA_SIZE 0x1 +#define GC_PINMUX_CLRHOLD1_SWDPDATA_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD1_SWDPDATA_OFFSET 0x14c +#define GC_PINMUX_CLRHOLD1_VIO0_LSB 0x12 +#define GC_PINMUX_CLRHOLD1_VIO0_MASK 0x40000 +#define GC_PINMUX_CLRHOLD1_VIO0_SIZE 0x1 +#define GC_PINMUX_CLRHOLD1_VIO0_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD1_VIO0_OFFSET 0x14c +#define GC_PINMUX_CLRHOLD1_VIO1_LSB 0x13 +#define GC_PINMUX_CLRHOLD1_VIO1_MASK 0x80000 +#define GC_PINMUX_CLRHOLD1_VIO1_SIZE 0x1 +#define GC_PINMUX_CLRHOLD1_VIO1_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD1_VIO1_OFFSET 0x14c +#define GC_PINMUX_CLRHOLD1_TDO_LSB 0x17 +#define GC_PINMUX_CLRHOLD1_TDO_MASK 0x800000 +#define GC_PINMUX_CLRHOLD1_TDO_SIZE 0x1 +#define GC_PINMUX_CLRHOLD1_TDO_DEFAULT 0x0 +#define GC_PINMUX_CLRHOLD1_TDO_OFFSET 0x14c +#define GC_PINMUX_EXITEN0_DIOM0_LSB 0x0 +#define GC_PINMUX_EXITEN0_DIOM0_MASK 0x1 +#define GC_PINMUX_EXITEN0_DIOM0_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOM0_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOM0_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM1_LSB 0x1 +#define GC_PINMUX_EXITEN0_DIOM1_MASK 0x2 +#define GC_PINMUX_EXITEN0_DIOM1_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOM1_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOM1_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM2_LSB 0x2 +#define GC_PINMUX_EXITEN0_DIOM2_MASK 0x4 +#define GC_PINMUX_EXITEN0_DIOM2_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOM2_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOM2_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM3_LSB 0x3 +#define GC_PINMUX_EXITEN0_DIOM3_MASK 0x8 +#define GC_PINMUX_EXITEN0_DIOM3_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOM3_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOM3_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOM4_LSB 0x4 +#define GC_PINMUX_EXITEN0_DIOM4_MASK 0x10 +#define GC_PINMUX_EXITEN0_DIOM4_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOM4_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOM4_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA0_LSB 0x5 +#define GC_PINMUX_EXITEN0_DIOA0_MASK 0x20 +#define GC_PINMUX_EXITEN0_DIOA0_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA0_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA0_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA1_LSB 0x6 +#define GC_PINMUX_EXITEN0_DIOA1_MASK 0x40 +#define GC_PINMUX_EXITEN0_DIOA1_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA1_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA1_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA2_LSB 0x7 +#define GC_PINMUX_EXITEN0_DIOA2_MASK 0x80 +#define GC_PINMUX_EXITEN0_DIOA2_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA2_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA2_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA3_LSB 0x8 +#define GC_PINMUX_EXITEN0_DIOA3_MASK 0x100 +#define GC_PINMUX_EXITEN0_DIOA3_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA3_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA3_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA4_LSB 0x9 +#define GC_PINMUX_EXITEN0_DIOA4_MASK 0x200 +#define GC_PINMUX_EXITEN0_DIOA4_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA4_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA4_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA5_LSB 0xa +#define GC_PINMUX_EXITEN0_DIOA5_MASK 0x400 +#define GC_PINMUX_EXITEN0_DIOA5_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA5_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA5_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA6_LSB 0xb +#define GC_PINMUX_EXITEN0_DIOA6_MASK 0x800 +#define GC_PINMUX_EXITEN0_DIOA6_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA6_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA6_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA7_LSB 0xc +#define GC_PINMUX_EXITEN0_DIOA7_MASK 0x1000 +#define GC_PINMUX_EXITEN0_DIOA7_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA7_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA7_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA8_LSB 0xd +#define GC_PINMUX_EXITEN0_DIOA8_MASK 0x2000 +#define GC_PINMUX_EXITEN0_DIOA8_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA8_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA8_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA9_LSB 0xe +#define GC_PINMUX_EXITEN0_DIOA9_MASK 0x4000 +#define GC_PINMUX_EXITEN0_DIOA9_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA9_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA9_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA10_LSB 0xf +#define GC_PINMUX_EXITEN0_DIOA10_MASK 0x8000 +#define GC_PINMUX_EXITEN0_DIOA10_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA10_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA10_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA11_LSB 0x10 +#define GC_PINMUX_EXITEN0_DIOA11_MASK 0x10000 +#define GC_PINMUX_EXITEN0_DIOA11_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA11_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA11_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA12_LSB 0x11 +#define GC_PINMUX_EXITEN0_DIOA12_MASK 0x20000 +#define GC_PINMUX_EXITEN0_DIOA12_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA12_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA12_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA13_LSB 0x12 +#define GC_PINMUX_EXITEN0_DIOA13_MASK 0x40000 +#define GC_PINMUX_EXITEN0_DIOA13_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA13_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA13_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOA14_LSB 0x13 +#define GC_PINMUX_EXITEN0_DIOA14_MASK 0x80000 +#define GC_PINMUX_EXITEN0_DIOA14_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOA14_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOA14_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB0_LSB 0x14 +#define GC_PINMUX_EXITEN0_DIOB0_MASK 0x100000 +#define GC_PINMUX_EXITEN0_DIOB0_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB0_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB0_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB1_LSB 0x15 +#define GC_PINMUX_EXITEN0_DIOB1_MASK 0x200000 +#define GC_PINMUX_EXITEN0_DIOB1_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB1_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB1_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB2_LSB 0x16 +#define GC_PINMUX_EXITEN0_DIOB2_MASK 0x400000 +#define GC_PINMUX_EXITEN0_DIOB2_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB2_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB2_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB3_LSB 0x17 +#define GC_PINMUX_EXITEN0_DIOB3_MASK 0x800000 +#define GC_PINMUX_EXITEN0_DIOB3_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB3_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB3_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB4_LSB 0x18 +#define GC_PINMUX_EXITEN0_DIOB4_MASK 0x1000000 +#define GC_PINMUX_EXITEN0_DIOB4_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB4_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB4_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB5_LSB 0x19 +#define GC_PINMUX_EXITEN0_DIOB5_MASK 0x2000000 +#define GC_PINMUX_EXITEN0_DIOB5_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB5_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB5_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB6_LSB 0x1a +#define GC_PINMUX_EXITEN0_DIOB6_MASK 0x4000000 +#define GC_PINMUX_EXITEN0_DIOB6_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB6_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB6_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB7_LSB 0x1b +#define GC_PINMUX_EXITEN0_DIOB7_MASK 0x8000000 +#define GC_PINMUX_EXITEN0_DIOB7_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB7_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB7_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN0_DIOB8_LSB 0x1c +#define GC_PINMUX_EXITEN0_DIOB8_MASK 0x10000000 +#define GC_PINMUX_EXITEN0_DIOB8_SIZE 0x1 +#define GC_PINMUX_EXITEN0_DIOB8_DEFAULT 0x0 +#define GC_PINMUX_EXITEN0_DIOB8_OFFSET 0x2e0 +#define GC_PINMUX_EXITEN1_RTCXOP_LSB 0xc +#define GC_PINMUX_EXITEN1_RTCXOP_MASK 0x1000 +#define GC_PINMUX_EXITEN1_RTCXOP_SIZE 0x1 +#define GC_PINMUX_EXITEN1_RTCXOP_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_RTCXOP_OFFSET 0x2e4 +#define GC_PINMUX_EXITEN1_SWDPTRACE_LSB 0xd +#define GC_PINMUX_EXITEN1_SWDPTRACE_MASK 0x2000 +#define GC_PINMUX_EXITEN1_SWDPTRACE_SIZE 0x1 +#define GC_PINMUX_EXITEN1_SWDPTRACE_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_SWDPTRACE_OFFSET 0x2e4 +#define GC_PINMUX_EXITEN1_SWDPDATA_LSB 0xe +#define GC_PINMUX_EXITEN1_SWDPDATA_MASK 0x4000 +#define GC_PINMUX_EXITEN1_SWDPDATA_SIZE 0x1 +#define GC_PINMUX_EXITEN1_SWDPDATA_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_SWDPDATA_OFFSET 0x2e4 +#define GC_PINMUX_EXITEN1_VIO0_LSB 0x12 +#define GC_PINMUX_EXITEN1_VIO0_MASK 0x40000 +#define GC_PINMUX_EXITEN1_VIO0_SIZE 0x1 +#define GC_PINMUX_EXITEN1_VIO0_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_VIO0_OFFSET 0x2e4 +#define GC_PINMUX_EXITEN1_VIO1_LSB 0x13 +#define GC_PINMUX_EXITEN1_VIO1_MASK 0x80000 +#define GC_PINMUX_EXITEN1_VIO1_SIZE 0x1 +#define GC_PINMUX_EXITEN1_VIO1_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_VIO1_OFFSET 0x2e4 +#define GC_PINMUX_EXITEN1_TDO_LSB 0x17 +#define GC_PINMUX_EXITEN1_TDO_MASK 0x800000 +#define GC_PINMUX_EXITEN1_TDO_SIZE 0x1 +#define GC_PINMUX_EXITEN1_TDO_DEFAULT 0x0 +#define GC_PINMUX_EXITEN1_TDO_OFFSET 0x2e4 +#define GC_PINMUX_EXITEDGE0_DIOM0_LSB 0x0 +#define GC_PINMUX_EXITEDGE0_DIOM0_MASK 0x1 +#define GC_PINMUX_EXITEDGE0_DIOM0_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOM0_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOM0_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM1_LSB 0x1 +#define GC_PINMUX_EXITEDGE0_DIOM1_MASK 0x2 +#define GC_PINMUX_EXITEDGE0_DIOM1_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOM1_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOM1_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM2_LSB 0x2 +#define GC_PINMUX_EXITEDGE0_DIOM2_MASK 0x4 +#define GC_PINMUX_EXITEDGE0_DIOM2_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOM2_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOM2_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM3_LSB 0x3 +#define GC_PINMUX_EXITEDGE0_DIOM3_MASK 0x8 +#define GC_PINMUX_EXITEDGE0_DIOM3_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOM3_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOM3_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOM4_LSB 0x4 +#define GC_PINMUX_EXITEDGE0_DIOM4_MASK 0x10 +#define GC_PINMUX_EXITEDGE0_DIOM4_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOM4_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOM4_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA0_LSB 0x5 +#define GC_PINMUX_EXITEDGE0_DIOA0_MASK 0x20 +#define GC_PINMUX_EXITEDGE0_DIOA0_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA0_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA0_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA1_LSB 0x6 +#define GC_PINMUX_EXITEDGE0_DIOA1_MASK 0x40 +#define GC_PINMUX_EXITEDGE0_DIOA1_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA1_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA1_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA2_LSB 0x7 +#define GC_PINMUX_EXITEDGE0_DIOA2_MASK 0x80 +#define GC_PINMUX_EXITEDGE0_DIOA2_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA2_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA2_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA3_LSB 0x8 +#define GC_PINMUX_EXITEDGE0_DIOA3_MASK 0x100 +#define GC_PINMUX_EXITEDGE0_DIOA3_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA3_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA3_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA4_LSB 0x9 +#define GC_PINMUX_EXITEDGE0_DIOA4_MASK 0x200 +#define GC_PINMUX_EXITEDGE0_DIOA4_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA4_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA4_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA5_LSB 0xa +#define GC_PINMUX_EXITEDGE0_DIOA5_MASK 0x400 +#define GC_PINMUX_EXITEDGE0_DIOA5_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA5_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA5_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA6_LSB 0xb +#define GC_PINMUX_EXITEDGE0_DIOA6_MASK 0x800 +#define GC_PINMUX_EXITEDGE0_DIOA6_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA6_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA6_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA7_LSB 0xc +#define GC_PINMUX_EXITEDGE0_DIOA7_MASK 0x1000 +#define GC_PINMUX_EXITEDGE0_DIOA7_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA7_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA7_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA8_LSB 0xd +#define GC_PINMUX_EXITEDGE0_DIOA8_MASK 0x2000 +#define GC_PINMUX_EXITEDGE0_DIOA8_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA8_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA8_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA9_LSB 0xe +#define GC_PINMUX_EXITEDGE0_DIOA9_MASK 0x4000 +#define GC_PINMUX_EXITEDGE0_DIOA9_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA9_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA9_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA10_LSB 0xf +#define GC_PINMUX_EXITEDGE0_DIOA10_MASK 0x8000 +#define GC_PINMUX_EXITEDGE0_DIOA10_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA10_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA10_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA11_LSB 0x10 +#define GC_PINMUX_EXITEDGE0_DIOA11_MASK 0x10000 +#define GC_PINMUX_EXITEDGE0_DIOA11_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA11_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA11_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA12_LSB 0x11 +#define GC_PINMUX_EXITEDGE0_DIOA12_MASK 0x20000 +#define GC_PINMUX_EXITEDGE0_DIOA12_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA12_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA12_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA13_LSB 0x12 +#define GC_PINMUX_EXITEDGE0_DIOA13_MASK 0x40000 +#define GC_PINMUX_EXITEDGE0_DIOA13_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA13_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA13_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOA14_LSB 0x13 +#define GC_PINMUX_EXITEDGE0_DIOA14_MASK 0x80000 +#define GC_PINMUX_EXITEDGE0_DIOA14_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOA14_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOA14_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB0_LSB 0x14 +#define GC_PINMUX_EXITEDGE0_DIOB0_MASK 0x100000 +#define GC_PINMUX_EXITEDGE0_DIOB0_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB0_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB0_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB1_LSB 0x15 +#define GC_PINMUX_EXITEDGE0_DIOB1_MASK 0x200000 +#define GC_PINMUX_EXITEDGE0_DIOB1_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB1_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB1_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB2_LSB 0x16 +#define GC_PINMUX_EXITEDGE0_DIOB2_MASK 0x400000 +#define GC_PINMUX_EXITEDGE0_DIOB2_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB2_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB2_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB3_LSB 0x17 +#define GC_PINMUX_EXITEDGE0_DIOB3_MASK 0x800000 +#define GC_PINMUX_EXITEDGE0_DIOB3_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB3_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB3_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB4_LSB 0x18 +#define GC_PINMUX_EXITEDGE0_DIOB4_MASK 0x1000000 +#define GC_PINMUX_EXITEDGE0_DIOB4_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB4_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB4_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB5_LSB 0x19 +#define GC_PINMUX_EXITEDGE0_DIOB5_MASK 0x2000000 +#define GC_PINMUX_EXITEDGE0_DIOB5_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB5_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB5_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB6_LSB 0x1a +#define GC_PINMUX_EXITEDGE0_DIOB6_MASK 0x4000000 +#define GC_PINMUX_EXITEDGE0_DIOB6_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB6_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB6_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB7_LSB 0x1b +#define GC_PINMUX_EXITEDGE0_DIOB7_MASK 0x8000000 +#define GC_PINMUX_EXITEDGE0_DIOB7_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB7_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB7_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE0_DIOB8_LSB 0x1c +#define GC_PINMUX_EXITEDGE0_DIOB8_MASK 0x10000000 +#define GC_PINMUX_EXITEDGE0_DIOB8_SIZE 0x1 +#define GC_PINMUX_EXITEDGE0_DIOB8_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE0_DIOB8_OFFSET 0x2e8 +#define GC_PINMUX_EXITEDGE1_RTCXOP_LSB 0xc +#define GC_PINMUX_EXITEDGE1_RTCXOP_MASK 0x1000 +#define GC_PINMUX_EXITEDGE1_RTCXOP_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_RTCXOP_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_RTCXOP_OFFSET 0x2ec +#define GC_PINMUX_EXITEDGE1_SWDPTRACE_LSB 0xd +#define GC_PINMUX_EXITEDGE1_SWDPTRACE_MASK 0x2000 +#define GC_PINMUX_EXITEDGE1_SWDPTRACE_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_SWDPTRACE_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_SWDPTRACE_OFFSET 0x2ec +#define GC_PINMUX_EXITEDGE1_SWDPDATA_LSB 0xe +#define GC_PINMUX_EXITEDGE1_SWDPDATA_MASK 0x4000 +#define GC_PINMUX_EXITEDGE1_SWDPDATA_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_SWDPDATA_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_SWDPDATA_OFFSET 0x2ec +#define GC_PINMUX_EXITEDGE1_VIO0_LSB 0x12 +#define GC_PINMUX_EXITEDGE1_VIO0_MASK 0x40000 +#define GC_PINMUX_EXITEDGE1_VIO0_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_VIO0_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_VIO0_OFFSET 0x2ec +#define GC_PINMUX_EXITEDGE1_VIO1_LSB 0x13 +#define GC_PINMUX_EXITEDGE1_VIO1_MASK 0x80000 +#define GC_PINMUX_EXITEDGE1_VIO1_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_VIO1_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_VIO1_OFFSET 0x2ec +#define GC_PINMUX_EXITEDGE1_TDO_LSB 0x17 +#define GC_PINMUX_EXITEDGE1_TDO_MASK 0x800000 +#define GC_PINMUX_EXITEDGE1_TDO_SIZE 0x1 +#define GC_PINMUX_EXITEDGE1_TDO_DEFAULT 0x0 +#define GC_PINMUX_EXITEDGE1_TDO_OFFSET 0x2ec +#define GC_PINMUX_EXITINV0_DIOM0_LSB 0x0 +#define GC_PINMUX_EXITINV0_DIOM0_MASK 0x1 +#define GC_PINMUX_EXITINV0_DIOM0_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOM0_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOM0_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM1_LSB 0x1 +#define GC_PINMUX_EXITINV0_DIOM1_MASK 0x2 +#define GC_PINMUX_EXITINV0_DIOM1_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOM1_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOM1_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM2_LSB 0x2 +#define GC_PINMUX_EXITINV0_DIOM2_MASK 0x4 +#define GC_PINMUX_EXITINV0_DIOM2_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOM2_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOM2_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM3_LSB 0x3 +#define GC_PINMUX_EXITINV0_DIOM3_MASK 0x8 +#define GC_PINMUX_EXITINV0_DIOM3_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOM3_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOM3_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOM4_LSB 0x4 +#define GC_PINMUX_EXITINV0_DIOM4_MASK 0x10 +#define GC_PINMUX_EXITINV0_DIOM4_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOM4_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOM4_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA0_LSB 0x5 +#define GC_PINMUX_EXITINV0_DIOA0_MASK 0x20 +#define GC_PINMUX_EXITINV0_DIOA0_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA0_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA0_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA1_LSB 0x6 +#define GC_PINMUX_EXITINV0_DIOA1_MASK 0x40 +#define GC_PINMUX_EXITINV0_DIOA1_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA1_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA1_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA2_LSB 0x7 +#define GC_PINMUX_EXITINV0_DIOA2_MASK 0x80 +#define GC_PINMUX_EXITINV0_DIOA2_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA2_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA2_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA3_LSB 0x8 +#define GC_PINMUX_EXITINV0_DIOA3_MASK 0x100 +#define GC_PINMUX_EXITINV0_DIOA3_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA3_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA3_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA4_LSB 0x9 +#define GC_PINMUX_EXITINV0_DIOA4_MASK 0x200 +#define GC_PINMUX_EXITINV0_DIOA4_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA4_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA4_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA5_LSB 0xa +#define GC_PINMUX_EXITINV0_DIOA5_MASK 0x400 +#define GC_PINMUX_EXITINV0_DIOA5_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA5_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA5_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA6_LSB 0xb +#define GC_PINMUX_EXITINV0_DIOA6_MASK 0x800 +#define GC_PINMUX_EXITINV0_DIOA6_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA6_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA6_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA7_LSB 0xc +#define GC_PINMUX_EXITINV0_DIOA7_MASK 0x1000 +#define GC_PINMUX_EXITINV0_DIOA7_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA7_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA7_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA8_LSB 0xd +#define GC_PINMUX_EXITINV0_DIOA8_MASK 0x2000 +#define GC_PINMUX_EXITINV0_DIOA8_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA8_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA8_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA9_LSB 0xe +#define GC_PINMUX_EXITINV0_DIOA9_MASK 0x4000 +#define GC_PINMUX_EXITINV0_DIOA9_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA9_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA9_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA10_LSB 0xf +#define GC_PINMUX_EXITINV0_DIOA10_MASK 0x8000 +#define GC_PINMUX_EXITINV0_DIOA10_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA10_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA10_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA11_LSB 0x10 +#define GC_PINMUX_EXITINV0_DIOA11_MASK 0x10000 +#define GC_PINMUX_EXITINV0_DIOA11_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA11_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA11_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA12_LSB 0x11 +#define GC_PINMUX_EXITINV0_DIOA12_MASK 0x20000 +#define GC_PINMUX_EXITINV0_DIOA12_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA12_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA12_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA13_LSB 0x12 +#define GC_PINMUX_EXITINV0_DIOA13_MASK 0x40000 +#define GC_PINMUX_EXITINV0_DIOA13_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA13_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA13_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOA14_LSB 0x13 +#define GC_PINMUX_EXITINV0_DIOA14_MASK 0x80000 +#define GC_PINMUX_EXITINV0_DIOA14_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOA14_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOA14_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB0_LSB 0x14 +#define GC_PINMUX_EXITINV0_DIOB0_MASK 0x100000 +#define GC_PINMUX_EXITINV0_DIOB0_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB0_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB0_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB1_LSB 0x15 +#define GC_PINMUX_EXITINV0_DIOB1_MASK 0x200000 +#define GC_PINMUX_EXITINV0_DIOB1_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB1_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB1_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB2_LSB 0x16 +#define GC_PINMUX_EXITINV0_DIOB2_MASK 0x400000 +#define GC_PINMUX_EXITINV0_DIOB2_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB2_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB2_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB3_LSB 0x17 +#define GC_PINMUX_EXITINV0_DIOB3_MASK 0x800000 +#define GC_PINMUX_EXITINV0_DIOB3_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB3_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB3_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB4_LSB 0x18 +#define GC_PINMUX_EXITINV0_DIOB4_MASK 0x1000000 +#define GC_PINMUX_EXITINV0_DIOB4_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB4_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB4_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB5_LSB 0x19 +#define GC_PINMUX_EXITINV0_DIOB5_MASK 0x2000000 +#define GC_PINMUX_EXITINV0_DIOB5_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB5_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB5_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB6_LSB 0x1a +#define GC_PINMUX_EXITINV0_DIOB6_MASK 0x4000000 +#define GC_PINMUX_EXITINV0_DIOB6_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB6_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB6_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB7_LSB 0x1b +#define GC_PINMUX_EXITINV0_DIOB7_MASK 0x8000000 +#define GC_PINMUX_EXITINV0_DIOB7_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB7_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB7_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV0_DIOB8_LSB 0x1c +#define GC_PINMUX_EXITINV0_DIOB8_MASK 0x10000000 +#define GC_PINMUX_EXITINV0_DIOB8_SIZE 0x1 +#define GC_PINMUX_EXITINV0_DIOB8_DEFAULT 0x0 +#define GC_PINMUX_EXITINV0_DIOB8_OFFSET 0x2f0 +#define GC_PINMUX_EXITINV1_RTCXOP_LSB 0xc +#define GC_PINMUX_EXITINV1_RTCXOP_MASK 0x1000 +#define GC_PINMUX_EXITINV1_RTCXOP_SIZE 0x1 +#define GC_PINMUX_EXITINV1_RTCXOP_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_RTCXOP_OFFSET 0x2f4 +#define GC_PINMUX_EXITINV1_SWDPTRACE_LSB 0xd +#define GC_PINMUX_EXITINV1_SWDPTRACE_MASK 0x2000 +#define GC_PINMUX_EXITINV1_SWDPTRACE_SIZE 0x1 +#define GC_PINMUX_EXITINV1_SWDPTRACE_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_SWDPTRACE_OFFSET 0x2f4 +#define GC_PINMUX_EXITINV1_SWDPDATA_LSB 0xe +#define GC_PINMUX_EXITINV1_SWDPDATA_MASK 0x4000 +#define GC_PINMUX_EXITINV1_SWDPDATA_SIZE 0x1 +#define GC_PINMUX_EXITINV1_SWDPDATA_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_SWDPDATA_OFFSET 0x2f4 +#define GC_PINMUX_EXITINV1_VIO0_LSB 0x12 +#define GC_PINMUX_EXITINV1_VIO0_MASK 0x40000 +#define GC_PINMUX_EXITINV1_VIO0_SIZE 0x1 +#define GC_PINMUX_EXITINV1_VIO0_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_VIO0_OFFSET 0x2f4 +#define GC_PINMUX_EXITINV1_VIO1_LSB 0x13 +#define GC_PINMUX_EXITINV1_VIO1_MASK 0x80000 +#define GC_PINMUX_EXITINV1_VIO1_SIZE 0x1 +#define GC_PINMUX_EXITINV1_VIO1_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_VIO1_OFFSET 0x2f4 +#define GC_PINMUX_EXITINV1_TDO_LSB 0x17 +#define GC_PINMUX_EXITINV1_TDO_MASK 0x800000 +#define GC_PINMUX_EXITINV1_TDO_SIZE 0x1 +#define GC_PINMUX_EXITINV1_TDO_DEFAULT 0x0 +#define GC_PINMUX_EXITINV1_TDO_OFFSET 0x2f4 +#define GC_PMU_RESET_PORESETB1_LSB 0x0 +#define GC_PMU_RESET_PORESETB1_MASK 0x1 +#define GC_PMU_RESET_PORESETB1_SIZE 0x1 +#define GC_PMU_RESET_PORESETB1_DEFAULT 0x1 +#define GC_PMU_RESET_PORESETB1_OFFSET 0x0 +#define GC_PMU_RESET_DAPRESETB1_LSB 0x1 +#define GC_PMU_RESET_DAPRESETB1_MASK 0x2 +#define GC_PMU_RESET_DAPRESETB1_SIZE 0x1 +#define GC_PMU_RESET_DAPRESETB1_DEFAULT 0x1 +#define GC_PMU_RESET_DAPRESETB1_OFFSET 0x0 +#define GC_PMU_SETRST_SRC_LSB 0x0 +#define GC_PMU_SETRST_SRC_MASK 0x1 +#define GC_PMU_SETRST_SRC_SIZE 0x1 +#define GC_PMU_SETRST_SRC_DEFAULT 0x0 +#define GC_PMU_SETRST_SRC_OFFSET 0x4 +#define GC_PMU_CLRRST_SRC_LSB 0x0 +#define GC_PMU_CLRRST_SRC_MASK 0x1 +#define GC_PMU_CLRRST_SRC_SIZE 0x1 +#define GC_PMU_CLRRST_SRC_DEFAULT 0x0 +#define GC_PMU_CLRRST_SRC_OFFSET 0x8 +#define GC_PMU_RSTSRC_POR_LSB 0x0 +#define GC_PMU_RSTSRC_POR_MASK 0x1 +#define GC_PMU_RSTSRC_POR_SIZE 0x1 +#define GC_PMU_RSTSRC_POR_DEFAULT 0x0 +#define GC_PMU_RSTSRC_POR_OFFSET 0xc +#define GC_PMU_RSTSRC_RESETB_LSB 0x1 +#define GC_PMU_RSTSRC_RESETB_MASK 0x2 +#define GC_PMU_RSTSRC_RESETB_SIZE 0x1 +#define GC_PMU_RSTSRC_RESETB_DEFAULT 0x0 +#define GC_PMU_RSTSRC_RESETB_OFFSET 0xc +#define GC_PMU_RSTSRC_EXIT_LSB 0x2 +#define GC_PMU_RSTSRC_EXIT_MASK 0x4 +#define GC_PMU_RSTSRC_EXIT_SIZE 0x1 +#define GC_PMU_RSTSRC_EXIT_DEFAULT 0x0 +#define GC_PMU_RSTSRC_EXIT_OFFSET 0xc +#define GC_PMU_RSTSRC_WDOG_LSB 0x3 +#define GC_PMU_RSTSRC_WDOG_MASK 0x8 +#define GC_PMU_RSTSRC_WDOG_SIZE 0x1 +#define GC_PMU_RSTSRC_WDOG_DEFAULT 0x0 +#define GC_PMU_RSTSRC_WDOG_OFFSET 0xc +#define GC_PMU_RSTSRC_LOCKUP_LSB 0x4 +#define GC_PMU_RSTSRC_LOCKUP_MASK 0x10 +#define GC_PMU_RSTSRC_LOCKUP_SIZE 0x1 +#define GC_PMU_RSTSRC_LOCKUP_DEFAULT 0x0 +#define GC_PMU_RSTSRC_LOCKUP_OFFSET 0xc +#define GC_PMU_RSTSRC_SYSRESET_LSB 0x5 +#define GC_PMU_RSTSRC_SYSRESET_MASK 0x20 +#define GC_PMU_RSTSRC_SYSRESET_SIZE 0x1 +#define GC_PMU_RSTSRC_SYSRESET_DEFAULT 0x0 +#define GC_PMU_RSTSRC_SYSRESET_OFFSET 0xc +#define GC_PMU_RSTSRC_SOFTWARE_LSB 0x6 +#define GC_PMU_RSTSRC_SOFTWARE_MASK 0x40 +#define GC_PMU_RSTSRC_SOFTWARE_SIZE 0x1 +#define GC_PMU_RSTSRC_SOFTWARE_DEFAULT 0x0 +#define GC_PMU_RSTSRC_SOFTWARE_OFFSET 0xc +#define GC_PMU_RSTSRC_FST_BRNOUT_LSB 0x7 +#define GC_PMU_RSTSRC_FST_BRNOUT_MASK 0x80 +#define GC_PMU_RSTSRC_FST_BRNOUT_SIZE 0x1 +#define GC_PMU_RSTSRC_FST_BRNOUT_DEFAULT 0x0 +#define GC_PMU_RSTSRC_FST_BRNOUT_OFFSET 0xc +#define GC_PMU_SETDIS_START_LSB 0x0 +#define GC_PMU_SETDIS_START_MASK 0x1 +#define GC_PMU_SETDIS_START_SIZE 0x1 +#define GC_PMU_SETDIS_START_DEFAULT 0x0 +#define GC_PMU_SETDIS_START_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDL_LSB 0x1 +#define GC_PMU_SETDIS_VDDL_MASK 0x2 +#define GC_PMU_SETDIS_VDDL_SIZE 0x1 +#define GC_PMU_SETDIS_VDDL_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDL_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDA_LSB 0x2 +#define GC_PMU_SETDIS_VDDA_MASK 0x4 +#define GC_PMU_SETDIS_VDDA_SIZE 0x1 +#define GC_PMU_SETDIS_VDDA_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDA_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDSRM_LSB 0x3 +#define GC_PMU_SETDIS_VDDSRM_MASK 0x8 +#define GC_PMU_SETDIS_VDDSRM_SIZE 0x1 +#define GC_PMU_SETDIS_VDDSRM_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDSRM_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDIOF_LSB 0x4 +#define GC_PMU_SETDIS_VDDIOF_MASK 0x10 +#define GC_PMU_SETDIS_VDDIOF_SIZE 0x1 +#define GC_PMU_SETDIS_VDDIOF_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDIOF_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDLK_LSB 0x5 +#define GC_PMU_SETDIS_VDDLK_MASK 0x20 +#define GC_PMU_SETDIS_VDDLK_SIZE 0x1 +#define GC_PMU_SETDIS_VDDLK_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDLK_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDSK_LSB 0x6 +#define GC_PMU_SETDIS_VDDSK_MASK 0x40 +#define GC_PMU_SETDIS_VDDSK_SIZE 0x1 +#define GC_PMU_SETDIS_VDDSK_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDSK_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDSRK_LSB 0x7 +#define GC_PMU_SETDIS_VDDSRK_MASK 0x80 +#define GC_PMU_SETDIS_VDDSRK_SIZE 0x1 +#define GC_PMU_SETDIS_VDDSRK_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDSRK_OFFSET 0x14 +#define GC_PMU_SETDIS_RETCOMPREF_LSB 0x8 +#define GC_PMU_SETDIS_RETCOMPREF_MASK 0x100 +#define GC_PMU_SETDIS_RETCOMPREF_SIZE 0x1 +#define GC_PMU_SETDIS_RETCOMPREF_DEFAULT 0x0 +#define GC_PMU_SETDIS_RETCOMPREF_OFFSET 0x14 +#define GC_PMU_SETDIS_BIAS_LSB 0x9 +#define GC_PMU_SETDIS_BIAS_MASK 0x200 +#define GC_PMU_SETDIS_BIAS_SIZE 0x1 +#define GC_PMU_SETDIS_BIAS_DEFAULT 0x0 +#define GC_PMU_SETDIS_BIAS_OFFSET 0x14 +#define GC_PMU_SETDIS_BGAP_LSB 0xa +#define GC_PMU_SETDIS_BGAP_MASK 0x400 +#define GC_PMU_SETDIS_BGAP_SIZE 0x1 +#define GC_PMU_SETDIS_BGAP_DEFAULT 0x0 +#define GC_PMU_SETDIS_BGAP_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDXO_LSB 0xb +#define GC_PMU_SETDIS_VDDXO_MASK 0x800 +#define GC_PMU_SETDIS_VDDXO_SIZE 0x1 +#define GC_PMU_SETDIS_VDDXO_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDXO_OFFSET 0x14 +#define GC_PMU_SETDIS_VDDXOLP_LSB 0xc +#define GC_PMU_SETDIS_VDDXOLP_MASK 0x1000 +#define GC_PMU_SETDIS_VDDXOLP_SIZE 0x1 +#define GC_PMU_SETDIS_VDDXOLP_DEFAULT 0x0 +#define GC_PMU_SETDIS_VDDXOLP_OFFSET 0x14 +#define GC_PMU_SETDIS_SEL_VDDXOLP_LSB 0xd +#define GC_PMU_SETDIS_SEL_VDDXOLP_MASK 0x2000 +#define GC_PMU_SETDIS_SEL_VDDXOLP_SIZE 0x1 +#define GC_PMU_SETDIS_SEL_VDDXOLP_DEFAULT 0x0 +#define GC_PMU_SETDIS_SEL_VDDXOLP_OFFSET 0x14 +#define GC_PMU_SETDIS_XTL_LSB 0xe +#define GC_PMU_SETDIS_XTL_MASK 0x4000 +#define GC_PMU_SETDIS_XTL_SIZE 0x1 +#define GC_PMU_SETDIS_XTL_DEFAULT 0x0 +#define GC_PMU_SETDIS_XTL_OFFSET 0x14 +#define GC_PMU_SETDIS_RC_TRIM_LSB 0xf +#define GC_PMU_SETDIS_RC_TRIM_MASK 0x8000 +#define GC_PMU_SETDIS_RC_TRIM_SIZE 0x1 +#define GC_PMU_SETDIS_RC_TRIM_DEFAULT 0x0 +#define GC_PMU_SETDIS_RC_TRIM_OFFSET 0x14 +#define GC_PMU_SETDIS_RC_NOTRIM_LSB 0x10 +#define GC_PMU_SETDIS_RC_NOTRIM_MASK 0x10000 +#define GC_PMU_SETDIS_RC_NOTRIM_SIZE 0x1 +#define GC_PMU_SETDIS_RC_NOTRIM_DEFAULT 0x0 +#define GC_PMU_SETDIS_RC_NOTRIM_OFFSET 0x14 +#define GC_PMU_SETDIS_BATMON_LSB 0x11 +#define GC_PMU_SETDIS_BATMON_MASK 0x20000 +#define GC_PMU_SETDIS_BATMON_SIZE 0x1 +#define GC_PMU_SETDIS_BATMON_DEFAULT 0x0 +#define GC_PMU_SETDIS_BATMON_OFFSET 0x14 +#define GC_PMU_SETDIS_FST_BRNOUT_PWR_LSB 0x12 +#define GC_PMU_SETDIS_FST_BRNOUT_PWR_MASK 0x40000 +#define GC_PMU_SETDIS_FST_BRNOUT_PWR_SIZE 0x1 +#define GC_PMU_SETDIS_FST_BRNOUT_PWR_DEFAULT 0x0 +#define GC_PMU_SETDIS_FST_BRNOUT_PWR_OFFSET 0x14 +#define GC_PMU_SETDIS_FST_BRNOUT_LSB 0x13 +#define GC_PMU_SETDIS_FST_BRNOUT_MASK 0x80000 +#define GC_PMU_SETDIS_FST_BRNOUT_SIZE 0x1 +#define GC_PMU_SETDIS_FST_BRNOUT_DEFAULT 0x0 +#define GC_PMU_SETDIS_FST_BRNOUT_OFFSET 0x14 +#define GC_PMU_CLRDIS_START_LSB 0x0 +#define GC_PMU_CLRDIS_START_MASK 0x1 +#define GC_PMU_CLRDIS_START_SIZE 0x1 +#define GC_PMU_CLRDIS_START_DEFAULT 0x0 +#define GC_PMU_CLRDIS_START_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDL_LSB 0x1 +#define GC_PMU_CLRDIS_VDDL_MASK 0x2 +#define GC_PMU_CLRDIS_VDDL_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDL_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDL_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDA_LSB 0x2 +#define GC_PMU_CLRDIS_VDDA_MASK 0x4 +#define GC_PMU_CLRDIS_VDDA_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDA_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDA_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDSRM_LSB 0x3 +#define GC_PMU_CLRDIS_VDDSRM_MASK 0x8 +#define GC_PMU_CLRDIS_VDDSRM_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDSRM_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDSRM_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDIOF_LSB 0x4 +#define GC_PMU_CLRDIS_VDDIOF_MASK 0x10 +#define GC_PMU_CLRDIS_VDDIOF_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDIOF_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDIOF_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDLK_LSB 0x5 +#define GC_PMU_CLRDIS_VDDLK_MASK 0x20 +#define GC_PMU_CLRDIS_VDDLK_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDLK_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDLK_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDSK_LSB 0x6 +#define GC_PMU_CLRDIS_VDDSK_MASK 0x40 +#define GC_PMU_CLRDIS_VDDSK_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDSK_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDSK_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDSRK_LSB 0x7 +#define GC_PMU_CLRDIS_VDDSRK_MASK 0x80 +#define GC_PMU_CLRDIS_VDDSRK_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDSRK_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDSRK_OFFSET 0x18 +#define GC_PMU_CLRDIS_RETCOMPREF_LSB 0x8 +#define GC_PMU_CLRDIS_RETCOMPREF_MASK 0x100 +#define GC_PMU_CLRDIS_RETCOMPREF_SIZE 0x1 +#define GC_PMU_CLRDIS_RETCOMPREF_DEFAULT 0x0 +#define GC_PMU_CLRDIS_RETCOMPREF_OFFSET 0x18 +#define GC_PMU_CLRDIS_BIAS_LSB 0x9 +#define GC_PMU_CLRDIS_BIAS_MASK 0x200 +#define GC_PMU_CLRDIS_BIAS_SIZE 0x1 +#define GC_PMU_CLRDIS_BIAS_DEFAULT 0x0 +#define GC_PMU_CLRDIS_BIAS_OFFSET 0x18 +#define GC_PMU_CLRDIS_BGAP_LSB 0xa +#define GC_PMU_CLRDIS_BGAP_MASK 0x400 +#define GC_PMU_CLRDIS_BGAP_SIZE 0x1 +#define GC_PMU_CLRDIS_BGAP_DEFAULT 0x0 +#define GC_PMU_CLRDIS_BGAP_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDXO_LSB 0xb +#define GC_PMU_CLRDIS_VDDXO_MASK 0x800 +#define GC_PMU_CLRDIS_VDDXO_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDXO_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDXO_OFFSET 0x18 +#define GC_PMU_CLRDIS_VDDXOLP_LSB 0xc +#define GC_PMU_CLRDIS_VDDXOLP_MASK 0x1000 +#define GC_PMU_CLRDIS_VDDXOLP_SIZE 0x1 +#define GC_PMU_CLRDIS_VDDXOLP_DEFAULT 0x0 +#define GC_PMU_CLRDIS_VDDXOLP_OFFSET 0x18 +#define GC_PMU_CLRDIS_SEL_VDDXOLP_LSB 0xd +#define GC_PMU_CLRDIS_SEL_VDDXOLP_MASK 0x2000 +#define GC_PMU_CLRDIS_SEL_VDDXOLP_SIZE 0x1 +#define GC_PMU_CLRDIS_SEL_VDDXOLP_DEFAULT 0x0 +#define GC_PMU_CLRDIS_SEL_VDDXOLP_OFFSET 0x18 +#define GC_PMU_CLRDIS_XTL_LSB 0xe +#define GC_PMU_CLRDIS_XTL_MASK 0x4000 +#define GC_PMU_CLRDIS_XTL_SIZE 0x1 +#define GC_PMU_CLRDIS_XTL_DEFAULT 0x0 +#define GC_PMU_CLRDIS_XTL_OFFSET 0x18 +#define GC_PMU_CLRDIS_RC_TRIM_LSB 0xf +#define GC_PMU_CLRDIS_RC_TRIM_MASK 0x8000 +#define GC_PMU_CLRDIS_RC_TRIM_SIZE 0x1 +#define GC_PMU_CLRDIS_RC_TRIM_DEFAULT 0x0 +#define GC_PMU_CLRDIS_RC_TRIM_OFFSET 0x18 +#define GC_PMU_CLRDIS_RC_NOTRIM_LSB 0x10 +#define GC_PMU_CLRDIS_RC_NOTRIM_MASK 0x10000 +#define GC_PMU_CLRDIS_RC_NOTRIM_SIZE 0x1 +#define GC_PMU_CLRDIS_RC_NOTRIM_DEFAULT 0x0 +#define GC_PMU_CLRDIS_RC_NOTRIM_OFFSET 0x18 +#define GC_PMU_CLRDIS_BATMON_LSB 0x11 +#define GC_PMU_CLRDIS_BATMON_MASK 0x20000 +#define GC_PMU_CLRDIS_BATMON_SIZE 0x1 +#define GC_PMU_CLRDIS_BATMON_DEFAULT 0x0 +#define GC_PMU_CLRDIS_BATMON_OFFSET 0x18 +#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_LSB 0x12 +#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_MASK 0x40000 +#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_SIZE 0x1 +#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_DEFAULT 0x0 +#define GC_PMU_CLRDIS_FST_BRNOUT_PWR_OFFSET 0x18 +#define GC_PMU_CLRDIS_FST_BRNOUT_LSB 0x13 +#define GC_PMU_CLRDIS_FST_BRNOUT_MASK 0x80000 +#define GC_PMU_CLRDIS_FST_BRNOUT_SIZE 0x1 +#define GC_PMU_CLRDIS_FST_BRNOUT_DEFAULT 0x0 +#define GC_PMU_CLRDIS_FST_BRNOUT_OFFSET 0x18 +#define GC_PMU_STATDIS_START_LSB 0x0 +#define GC_PMU_STATDIS_START_MASK 0x1 +#define GC_PMU_STATDIS_START_SIZE 0x1 +#define GC_PMU_STATDIS_START_DEFAULT 0x0 +#define GC_PMU_STATDIS_START_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDL_LSB 0x1 +#define GC_PMU_STATDIS_VDDL_MASK 0x2 +#define GC_PMU_STATDIS_VDDL_SIZE 0x1 +#define GC_PMU_STATDIS_VDDL_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDL_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDA_LSB 0x2 +#define GC_PMU_STATDIS_VDDA_MASK 0x4 +#define GC_PMU_STATDIS_VDDA_SIZE 0x1 +#define GC_PMU_STATDIS_VDDA_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDA_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDSRM_LSB 0x3 +#define GC_PMU_STATDIS_VDDSRM_MASK 0x8 +#define GC_PMU_STATDIS_VDDSRM_SIZE 0x1 +#define GC_PMU_STATDIS_VDDSRM_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDSRM_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDIOF_LSB 0x4 +#define GC_PMU_STATDIS_VDDIOF_MASK 0x10 +#define GC_PMU_STATDIS_VDDIOF_SIZE 0x1 +#define GC_PMU_STATDIS_VDDIOF_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDIOF_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDLK_LSB 0x5 +#define GC_PMU_STATDIS_VDDLK_MASK 0x20 +#define GC_PMU_STATDIS_VDDLK_SIZE 0x1 +#define GC_PMU_STATDIS_VDDLK_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDLK_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDSK_LSB 0x6 +#define GC_PMU_STATDIS_VDDSK_MASK 0x40 +#define GC_PMU_STATDIS_VDDSK_SIZE 0x1 +#define GC_PMU_STATDIS_VDDSK_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDSK_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDSRK_LSB 0x7 +#define GC_PMU_STATDIS_VDDSRK_MASK 0x80 +#define GC_PMU_STATDIS_VDDSRK_SIZE 0x1 +#define GC_PMU_STATDIS_VDDSRK_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDSRK_OFFSET 0x1c +#define GC_PMU_STATDIS_RETCOMPREF_LSB 0x8 +#define GC_PMU_STATDIS_RETCOMPREF_MASK 0x100 +#define GC_PMU_STATDIS_RETCOMPREF_SIZE 0x1 +#define GC_PMU_STATDIS_RETCOMPREF_DEFAULT 0x0 +#define GC_PMU_STATDIS_RETCOMPREF_OFFSET 0x1c +#define GC_PMU_STATDIS_BIAS_LSB 0x9 +#define GC_PMU_STATDIS_BIAS_MASK 0x200 +#define GC_PMU_STATDIS_BIAS_SIZE 0x1 +#define GC_PMU_STATDIS_BIAS_DEFAULT 0x0 +#define GC_PMU_STATDIS_BIAS_OFFSET 0x1c +#define GC_PMU_STATDIS_BGAP_LSB 0xa +#define GC_PMU_STATDIS_BGAP_MASK 0x400 +#define GC_PMU_STATDIS_BGAP_SIZE 0x1 +#define GC_PMU_STATDIS_BGAP_DEFAULT 0x0 +#define GC_PMU_STATDIS_BGAP_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDXO_LSB 0xb +#define GC_PMU_STATDIS_VDDXO_MASK 0x800 +#define GC_PMU_STATDIS_VDDXO_SIZE 0x1 +#define GC_PMU_STATDIS_VDDXO_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDXO_OFFSET 0x1c +#define GC_PMU_STATDIS_VDDXOLP_LSB 0xc +#define GC_PMU_STATDIS_VDDXOLP_MASK 0x1000 +#define GC_PMU_STATDIS_VDDXOLP_SIZE 0x1 +#define GC_PMU_STATDIS_VDDXOLP_DEFAULT 0x0 +#define GC_PMU_STATDIS_VDDXOLP_OFFSET 0x1c +#define GC_PMU_STATDIS_SEL_VDDXOLP_LSB 0xd +#define GC_PMU_STATDIS_SEL_VDDXOLP_MASK 0x2000 +#define GC_PMU_STATDIS_SEL_VDDXOLP_SIZE 0x1 +#define GC_PMU_STATDIS_SEL_VDDXOLP_DEFAULT 0x0 +#define GC_PMU_STATDIS_SEL_VDDXOLP_OFFSET 0x1c +#define GC_PMU_STATDIS_XTL_LSB 0xe +#define GC_PMU_STATDIS_XTL_MASK 0x4000 +#define GC_PMU_STATDIS_XTL_SIZE 0x1 +#define GC_PMU_STATDIS_XTL_DEFAULT 0x1 +#define GC_PMU_STATDIS_XTL_OFFSET 0x1c +#define GC_PMU_STATDIS_RC_TRIM_LSB 0xf +#define GC_PMU_STATDIS_RC_TRIM_MASK 0x8000 +#define GC_PMU_STATDIS_RC_TRIM_SIZE 0x1 +#define GC_PMU_STATDIS_RC_TRIM_DEFAULT 0x1 +#define GC_PMU_STATDIS_RC_TRIM_OFFSET 0x1c +#define GC_PMU_STATDIS_RC_NOTRIM_LSB 0x10 +#define GC_PMU_STATDIS_RC_NOTRIM_MASK 0x10000 +#define GC_PMU_STATDIS_RC_NOTRIM_SIZE 0x1 +#define GC_PMU_STATDIS_RC_NOTRIM_DEFAULT 0x0 +#define GC_PMU_STATDIS_RC_NOTRIM_OFFSET 0x1c +#define GC_PMU_STATDIS_BATMON_LSB 0x11 +#define GC_PMU_STATDIS_BATMON_MASK 0x20000 +#define GC_PMU_STATDIS_BATMON_SIZE 0x1 +#define GC_PMU_STATDIS_BATMON_DEFAULT 0x1 +#define GC_PMU_STATDIS_BATMON_OFFSET 0x1c +#define GC_PMU_STATDIS_FST_BRNOUT_PWR_LSB 0x12 +#define GC_PMU_STATDIS_FST_BRNOUT_PWR_MASK 0x40000 +#define GC_PMU_STATDIS_FST_BRNOUT_PWR_SIZE 0x1 +#define GC_PMU_STATDIS_FST_BRNOUT_PWR_DEFAULT 0x1 +#define GC_PMU_STATDIS_FST_BRNOUT_PWR_OFFSET 0x1c +#define GC_PMU_STATDIS_FST_BRNOUT_LSB 0x13 +#define GC_PMU_STATDIS_FST_BRNOUT_MASK 0x80000 +#define GC_PMU_STATDIS_FST_BRNOUT_SIZE 0x1 +#define GC_PMU_STATDIS_FST_BRNOUT_DEFAULT 0x1 +#define GC_PMU_STATDIS_FST_BRNOUT_OFFSET 0x1c +#define GC_PMU_SETWIC_PROC0_LSB 0x0 +#define GC_PMU_SETWIC_PROC0_MASK 0x1 +#define GC_PMU_SETWIC_PROC0_SIZE 0x1 +#define GC_PMU_SETWIC_PROC0_DEFAULT 0x0 +#define GC_PMU_SETWIC_PROC0_OFFSET 0x20 +#define GC_PMU_CLRWIC_PROC0_LSB 0x0 +#define GC_PMU_CLRWIC_PROC0_MASK 0x1 +#define GC_PMU_CLRWIC_PROC0_SIZE 0x1 +#define GC_PMU_CLRWIC_PROC0_DEFAULT 0x0 +#define GC_PMU_CLRWIC_PROC0_OFFSET 0x24 +#define GC_PMU_EXCLUSIVE_PROC0_LSB 0x0 +#define GC_PMU_EXCLUSIVE_PROC0_MASK 0x1 +#define GC_PMU_EXCLUSIVE_PROC0_SIZE 0x1 +#define GC_PMU_EXCLUSIVE_PROC0_DEFAULT 0x0 +#define GC_PMU_EXCLUSIVE_PROC0_OFFSET 0x2c +#define GC_PMUU_ADC_ADC_PDB_LSB 0x0 +#define GC_PMUU_ADC_ADC_PDB_MASK 0x1 +#define GC_PMUU_ADC_ADC_PDB_SIZE 0x1 +#define GC_PMUU_ADC_ADC_PDB_DEFAULT 0x0 +#define GC_PMUU_ADC_ADC_PDB_OFFSET 0x44 +#define GC_PMUSETU_ADC_ADC_PDB_3P3_LSB 0x0 +#define GC_PMUSETU_ADC_ADC_PDB_3P3_MASK 0x1 +#define GC_PMUSETU_ADC_ADC_PDB_3P3_SIZE 0x1 +#define GC_PMUSETU_ADC_ADC_PDB_3P3_DEFAULT 0x0 +#define GC_PMUSETU_ADC_ADC_PDB_3P3_OFFSET 0x48 +#define GC_PMUCLRU_ADC_ADC_PDB_3P3_LSB 0x0 +#define GC_PMUCLRU_ADC_ADC_PDB_3P3_MASK 0x1 +#define GC_PMUCLRU_ADC_ADC_PDB_3P3_SIZE 0x1 +#define GC_PMUCLRU_ADC_ADC_PDB_3P3_DEFAULT 0x0 +#define GC_PMUCLRU_ADC_ADC_PDB_3P3_OFFSET 0x4c +#define GC_PMUSETU_TRNG_TOP_TRNG_LDO_PDB_3P3_LSB 0x0 +#define GC_PMUSETU_TRNG_TOP_TRNG_LDO_PDB_3P3_MASK 0x1 +#define GC_PMUSETU_TRNG_TOP_TRNG_LDO_PDB_3P3_SIZE 0x1 +#define GC_PMUSETU_TRNG_TOP_TRNG_LDO_PDB_3P3_DEFAULT 0x0 +#define GC_PMUSETU_TRNG_TOP_TRNG_LDO_PDB_3P3_OFFSET 0x50 +#define GC_PMUCLRU_TRNG_TOP_TRNG_LDO_PDB_3P3_LSB 0x0 +#define GC_PMUCLRU_TRNG_TOP_TRNG_LDO_PDB_3P3_MASK 0x1 +#define GC_PMUCLRU_TRNG_TOP_TRNG_LDO_PDB_3P3_SIZE 0x1 +#define GC_PMUCLRU_TRNG_TOP_TRNG_LDO_PDB_3P3_DEFAULT 0x0 +#define GC_PMUCLRU_TRNG_TOP_TRNG_LDO_PDB_3P3_OFFSET 0x54 +#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_LSB 0x0 +#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_MASK 0x1 +#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_SIZE 0x1 +#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_DEFAULT 0x0 +#define GC_PMUSETRTC_X_RTC_RC_PDB_3P3_OFFSET 0x58 +#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_LSB 0x1 +#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_MASK 0x2 +#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_SIZE 0x1 +#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_DEFAULT 0x0 +#define GC_PMUSETRTC_X_RTC_XTL_PDB_3P3_OFFSET 0x58 +#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_LSB 0x0 +#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_MASK 0x1 +#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_SIZE 0x1 +#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_DEFAULT 0x0 +#define GC_PMUCLRRTC_X_RTC_RC_PDB_3P3_OFFSET 0x5c +#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_LSB 0x1 +#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_MASK 0x2 +#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_SIZE 0x1 +#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_DEFAULT 0x0 +#define GC_PMUCLRRTC_X_RTC_XTL_PDB_3P3_OFFSET 0x5c +#define GC_PMU_VREF_REG_LSB 0x0 +#define GC_PMU_VREF_REG_MASK 0xf +#define GC_PMU_VREF_REG_SIZE 0x4 +#define GC_PMU_VREF_REG_DEFAULT 0x8 +#define GC_PMU_VREF_REG_OFFSET 0x60 +#define GC_PMU_VREF_RET_LSB 0x4 +#define GC_PMU_VREF_RET_MASK 0xf0 +#define GC_PMU_VREF_RET_SIZE 0x4 +#define GC_PMU_VREF_RET_DEFAULT 0x8 +#define GC_PMU_VREF_RET_OFFSET 0x60 +#define GC_PMU_VREF_RLDOCTRL_LSB 0x8 +#define GC_PMU_VREF_RLDOCTRL_MASK 0xf00 +#define GC_PMU_VREF_RLDOCTRL_SIZE 0x4 +#define GC_PMU_VREF_RLDOCTRL_DEFAULT 0xf +#define GC_PMU_VREF_RLDOCTRL_OFFSET 0x60 +#define GC_PMU_VREF_RLDOLNA_LSB 0xc +#define GC_PMU_VREF_RLDOLNA_MASK 0xf000 +#define GC_PMU_VREF_RLDOLNA_SIZE 0x4 +#define GC_PMU_VREF_RLDOLNA_DEFAULT 0xf +#define GC_PMU_VREF_RLDOLNA_OFFSET 0x60 +#define GC_PMU_VREF_RLDOLO_LSB 0x10 +#define GC_PMU_VREF_RLDOLO_MASK 0xf0000 +#define GC_PMU_VREF_RLDOLO_SIZE 0x4 +#define GC_PMU_VREF_RLDOLO_DEFAULT 0xf +#define GC_PMU_VREF_RLDOLO_OFFSET 0x60 +#define GC_PMU_VREF_LDOXO_LSB 0x14 +#define GC_PMU_VREF_LDOXO_MASK 0xf00000 +#define GC_PMU_VREF_LDOXO_SIZE 0x4 +#define GC_PMU_VREF_LDOXO_DEFAULT 0xf +#define GC_PMU_VREF_LDOXO_OFFSET 0x60 +#define GC_PMU_VREF_BATMON_LSB 0x18 +#define GC_PMU_VREF_BATMON_MASK 0x7000000 +#define GC_PMU_VREF_BATMON_SIZE 0x3 +#define GC_PMU_VREF_BATMON_DEFAULT 0x0 +#define GC_PMU_VREF_BATMON_OFFSET 0x60 +#define GC_PMU_VREF_BATMON_V1P9 0x2 +#define GC_PMU_VREF_BATMON_V1P8 0x1 +#define GC_PMU_VREF_BATMON_V1P7 0x0 +#define GC_PMU_VREF_BATMON_V2P4 0x7 +#define GC_PMU_VREF_BATMON_V2P0 0x3 +#define GC_PMU_VREF_BATMON_V2P1 0x4 +#define GC_PMU_VREF_BATMON_V2P2 0x5 +#define GC_PMU_VREF_BATMON_V2P3 0x6 +#define GC_PMU_VREFCMP_CMP1_LSB 0x0 +#define GC_PMU_VREFCMP_CMP1_MASK 0x1f +#define GC_PMU_VREFCMP_CMP1_SIZE 0x5 +#define GC_PMU_VREFCMP_CMP1_DEFAULT 0x0 +#define GC_PMU_VREFCMP_CMP1_OFFSET 0x64 +#define GC_PMU_VREFCMP_CMP2_LSB 0x5 +#define GC_PMU_VREFCMP_CMP2_MASK 0x3e0 +#define GC_PMU_VREFCMP_CMP2_SIZE 0x5 +#define GC_PMU_VREFCMP_CMP2_DEFAULT 0x0 +#define GC_PMU_VREFCMP_CMP2_OFFSET 0x64 +#define GC_PMU_VREFCMP_VHYSTCMP1_LSB 0xa +#define GC_PMU_VREFCMP_VHYSTCMP1_MASK 0x1c00 +#define GC_PMU_VREFCMP_VHYSTCMP1_SIZE 0x3 +#define GC_PMU_VREFCMP_VHYSTCMP1_DEFAULT 0x0 +#define GC_PMU_VREFCMP_VHYSTCMP1_OFFSET 0x64 +#define GC_PMU_VREFCMP_VHYSTCMP2_LSB 0xd +#define GC_PMU_VREFCMP_VHYSTCMP2_MASK 0xe000 +#define GC_PMU_VREFCMP_VHYSTCMP2_SIZE 0x3 +#define GC_PMU_VREFCMP_VHYSTCMP2_DEFAULT 0x0 +#define GC_PMU_VREFCMP_VHYSTCMP2_OFFSET 0x64 +#define GC_PMU_RBIAS_CTRL_LSB 0x0 +#define GC_PMU_RBIAS_CTRL_MASK 0xff +#define GC_PMU_RBIAS_CTRL_SIZE 0x8 +#define GC_PMU_RBIAS_CTRL_DEFAULT 0x0 +#define GC_PMU_RBIAS_CTRL_OFFSET 0x68 +#define GC_PMU_RBIASLO_TUNEIR10ADC_LSB 0x0 +#define GC_PMU_RBIASLO_TUNEIR10ADC_MASK 0x3 +#define GC_PMU_RBIASLO_TUNEIR10ADC_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10ADC_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10ADC_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10ADC2_LSB 0x2 +#define GC_PMU_RBIASLO_TUNEIR10ADC2_MASK 0xc +#define GC_PMU_RBIASLO_TUNEIR10ADC2_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10ADC2_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10ADC2_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10ADC3_LSB 0x4 +#define GC_PMU_RBIASLO_TUNEIR10ADC3_MASK 0x30 +#define GC_PMU_RBIASLO_TUNEIR10ADC3_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10ADC3_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10ADC3_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_LSB 0x6 +#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_MASK 0xc0 +#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10XOPKDT_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10ADC4_LSB 0x8 +#define GC_PMU_RBIASLO_TUNEIR10ADC4_MASK 0x300 +#define GC_PMU_RBIASLO_TUNEIR10ADC4_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10ADC4_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10ADC4_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10COMP_LSB 0xa +#define GC_PMU_RBIASLO_TUNEIR10COMP_MASK 0xc00 +#define GC_PMU_RBIASLO_TUNEIR10COMP_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10COMP_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10COMP_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10COMP2_LSB 0xc +#define GC_PMU_RBIASLO_TUNEIR10COMP2_MASK 0x3000 +#define GC_PMU_RBIASLO_TUNEIR10COMP2_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10COMP2_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10COMP2_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGXO_LSB 0xe +#define GC_PMU_RBIASLO_TUNEIR10REGXO_MASK 0xc000 +#define GC_PMU_RBIASLO_TUNEIR10REGXO_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGXO_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGXO_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_LSB 0x10 +#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_MASK 0x30000 +#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGXOREF_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_LSB 0x12 +#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_MASK 0xc0000 +#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGSRAMRET_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_LSB 0x14 +#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_MASK 0x300000 +#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGSRAM_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGREF_LSB 0x16 +#define GC_PMU_RBIASLO_TUNEIR10REGREF_MASK 0xc00000 +#define GC_PMU_RBIASLO_TUNEIR10REGREF_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGREF_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGREF_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_LSB 0x18 +#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_MASK 0x3000000 +#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGLOGRET_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGLOG_LSB 0x1a +#define GC_PMU_RBIASLO_TUNEIR10REGLOG_MASK 0xc000000 +#define GC_PMU_RBIASLO_TUNEIR10REGLOG_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGLOG_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGLOG_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_LSB 0x1c +#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_MASK 0x30000000 +#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGLNAREF_OFFSET 0x6c +#define GC_PMU_RBIASLO_TUNEIR10REGLNA_LSB 0x1e +#define GC_PMU_RBIASLO_TUNEIR10REGLNA_MASK 0xc0000000 +#define GC_PMU_RBIASLO_TUNEIR10REGLNA_SIZE 0x2 +#define GC_PMU_RBIASLO_TUNEIR10REGLNA_DEFAULT 0x0 +#define GC_PMU_RBIASLO_TUNEIR10REGLNA_OFFSET 0x6c +#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_LSB 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_MASK 0x3 +#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REGLOREF_OFFSET 0x70 +#define GC_PMU_RBIASHI_TUNEIR10REGLO_LSB 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REGLO_MASK 0xc +#define GC_PMU_RBIASHI_TUNEIR10REGLO_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REGLO_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REGLO_OFFSET 0x70 +#define GC_PMU_RBIASHI_TUNEIR10REGAREF_LSB 0x4 +#define GC_PMU_RBIASHI_TUNEIR10REGAREF_MASK 0x30 +#define GC_PMU_RBIASHI_TUNEIR10REGAREF_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REGAREF_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REGAREF_OFFSET 0x70 +#define GC_PMU_RBIASHI_TUNEIR10REGA_LSB 0x6 +#define GC_PMU_RBIASHI_TUNEIR10REGA_MASK 0xc0 +#define GC_PMU_RBIASHI_TUNEIR10REGA_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REGA_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REGA_OFFSET 0x70 +#define GC_PMU_RBIASHI_TUNEIR10REG6_LSB 0x8 +#define GC_PMU_RBIASHI_TUNEIR10REG6_MASK 0x300 +#define GC_PMU_RBIASHI_TUNEIR10REG6_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REG6_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REG6_OFFSET 0x70 +#define GC_PMU_RBIASHI_TUNEIR10REG7_LSB 0xa +#define GC_PMU_RBIASHI_TUNEIR10REG7_MASK 0xc00 +#define GC_PMU_RBIASHI_TUNEIR10REG7_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REG7_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REG7_OFFSET 0x70 +#define GC_PMU_RBIASHI_TUNEIR10REG8_LSB 0xc +#define GC_PMU_RBIASHI_TUNEIR10REG8_MASK 0x3000 +#define GC_PMU_RBIASHI_TUNEIR10REG8_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REG8_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REG8_OFFSET 0x70 +#define GC_PMU_RBIASHI_TUNEIR10REG9_LSB 0xe +#define GC_PMU_RBIASHI_TUNEIR10REG9_MASK 0xc000 +#define GC_PMU_RBIASHI_TUNEIR10REG9_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10REG9_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10REG9_OFFSET 0x70 +#define GC_PMU_RBIASHI_TUNEIR10OPAMP_LSB 0x10 +#define GC_PMU_RBIASHI_TUNEIR10OPAMP_MASK 0x30000 +#define GC_PMU_RBIASHI_TUNEIR10OPAMP_SIZE 0x2 +#define GC_PMU_RBIASHI_TUNEIR10OPAMP_DEFAULT 0x0 +#define GC_PMU_RBIASHI_TUNEIR10OPAMP_OFFSET 0x70 +#define GC_PMU_SETHOLDVREF_REG_LSB 0x0 +#define GC_PMU_SETHOLDVREF_REG_MASK 0x1 +#define GC_PMU_SETHOLDVREF_REG_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_REG_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_REG_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_RET_LSB 0x1 +#define GC_PMU_SETHOLDVREF_RET_MASK 0x2 +#define GC_PMU_SETHOLDVREF_RET_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_RET_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_RET_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_BIASCTRL_LSB 0x2 +#define GC_PMU_SETHOLDVREF_BIASCTRL_MASK 0x4 +#define GC_PMU_SETHOLDVREF_BIASCTRL_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_BIASCTRL_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_BIASCTRL_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_BIASTUNER_LSB 0x3 +#define GC_PMU_SETHOLDVREF_BIASTUNER_MASK 0x8 +#define GC_PMU_SETHOLDVREF_BIASTUNER_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_BIASTUNER_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_BIASTUNER_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_LDOLNA_LSB 0x4 +#define GC_PMU_SETHOLDVREF_LDOLNA_MASK 0x10 +#define GC_PMU_SETHOLDVREF_LDOLNA_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_LDOLNA_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_LDOLNA_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_LDOLO_LSB 0x5 +#define GC_PMU_SETHOLDVREF_LDOLO_MASK 0x20 +#define GC_PMU_SETHOLDVREF_LDOLO_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_LDOLO_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_LDOLO_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_LDOCTRL_LSB 0x6 +#define GC_PMU_SETHOLDVREF_LDOCTRL_MASK 0x40 +#define GC_PMU_SETHOLDVREF_LDOCTRL_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_LDOCTRL_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_LDOCTRL_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_LDOXO_LSB 0x7 +#define GC_PMU_SETHOLDVREF_LDOXO_MASK 0x80 +#define GC_PMU_SETHOLDVREF_LDOXO_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_LDOXO_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_LDOXO_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_BATMON_LSB 0x8 +#define GC_PMU_SETHOLDVREF_BATMON_MASK 0x100 +#define GC_PMU_SETHOLDVREF_BATMON_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_BATMON_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_BATMON_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_CMP1_LSB 0x9 +#define GC_PMU_SETHOLDVREF_CMP1_MASK 0x200 +#define GC_PMU_SETHOLDVREF_CMP1_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_CMP1_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_CMP1_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_CMP2_LSB 0xa +#define GC_PMU_SETHOLDVREF_CMP2_MASK 0x400 +#define GC_PMU_SETHOLDVREF_CMP2_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_CMP2_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_CMP2_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_VHYSTCMP1_LSB 0xb +#define GC_PMU_SETHOLDVREF_VHYSTCMP1_MASK 0x800 +#define GC_PMU_SETHOLDVREF_VHYSTCMP1_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_VHYSTCMP1_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_VHYSTCMP1_OFFSET 0x74 +#define GC_PMU_SETHOLDVREF_VHYSTCMP2_LSB 0xc +#define GC_PMU_SETHOLDVREF_VHYSTCMP2_MASK 0x1000 +#define GC_PMU_SETHOLDVREF_VHYSTCMP2_SIZE 0x1 +#define GC_PMU_SETHOLDVREF_VHYSTCMP2_DEFAULT 0x0 +#define GC_PMU_SETHOLDVREF_VHYSTCMP2_OFFSET 0x74 +#define GC_PMU_CLRHOLDVREF_REG_LSB 0x0 +#define GC_PMU_CLRHOLDVREF_REG_MASK 0x1 +#define GC_PMU_CLRHOLDVREF_REG_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_REG_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_REG_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_RET_LSB 0x1 +#define GC_PMU_CLRHOLDVREF_RET_MASK 0x2 +#define GC_PMU_CLRHOLDVREF_RET_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_RET_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_RET_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_BIASCTRL_LSB 0x2 +#define GC_PMU_CLRHOLDVREF_BIASCTRL_MASK 0x4 +#define GC_PMU_CLRHOLDVREF_BIASCTRL_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_BIASCTRL_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_BIASCTRL_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_BIASTUNER_LSB 0x3 +#define GC_PMU_CLRHOLDVREF_BIASTUNER_MASK 0x8 +#define GC_PMU_CLRHOLDVREF_BIASTUNER_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_BIASTUNER_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_BIASTUNER_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_LDOLNA_LSB 0x4 +#define GC_PMU_CLRHOLDVREF_LDOLNA_MASK 0x10 +#define GC_PMU_CLRHOLDVREF_LDOLNA_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_LDOLNA_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_LDOLNA_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_LDOLO_LSB 0x5 +#define GC_PMU_CLRHOLDVREF_LDOLO_MASK 0x20 +#define GC_PMU_CLRHOLDVREF_LDOLO_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_LDOLO_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_LDOLO_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_LDOCTRL_LSB 0x6 +#define GC_PMU_CLRHOLDVREF_LDOCTRL_MASK 0x40 +#define GC_PMU_CLRHOLDVREF_LDOCTRL_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_LDOCTRL_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_LDOCTRL_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_LDOXO_LSB 0x7 +#define GC_PMU_CLRHOLDVREF_LDOXO_MASK 0x80 +#define GC_PMU_CLRHOLDVREF_LDOXO_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_LDOXO_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_LDOXO_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_BATMON_LSB 0x8 +#define GC_PMU_CLRHOLDVREF_BATMON_MASK 0x100 +#define GC_PMU_CLRHOLDVREF_BATMON_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_BATMON_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_BATMON_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_CMP1_LSB 0x9 +#define GC_PMU_CLRHOLDVREF_CMP1_MASK 0x200 +#define GC_PMU_CLRHOLDVREF_CMP1_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_CMP1_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_CMP1_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_CMP2_LSB 0xa +#define GC_PMU_CLRHOLDVREF_CMP2_MASK 0x400 +#define GC_PMU_CLRHOLDVREF_CMP2_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_CMP2_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_CMP2_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_LSB 0xb +#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_MASK 0x800 +#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_VHYSTCMP1_OFFSET 0x78 +#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_LSB 0xc +#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_MASK 0x1000 +#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_SIZE 0x1 +#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_DEFAULT 0x0 +#define GC_PMU_CLRHOLDVREF_VHYSTCMP2_OFFSET 0x78 +#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_LSB 0x0 +#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_MASK 0x3 +#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_SIZE 0x2 +#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_DEFAULT 0x0 +#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_OFFSET 0x80 +#define GC_PMU_B_REG_DIG_CTRL_SPARE_LSB 0x2 +#define GC_PMU_B_REG_DIG_CTRL_SPARE_MASK 0x3c +#define GC_PMU_B_REG_DIG_CTRL_SPARE_SIZE 0x4 +#define GC_PMU_B_REG_DIG_CTRL_SPARE_DEFAULT 0x0 +#define GC_PMU_B_REG_DIG_CTRL_SPARE_OFFSET 0x80 +#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_LSB 0x0 +#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_MASK 0x1 +#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_SIZE 0x1 +#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_DEFAULT 0x0 +#define GC_PMU_B_REG_DIG_LATCH_CTRL_WR_EN_OFFSET 0x84 +#define GC_PMU_EXITPD_MASK_PD_EXIT_LSB 0x0 +#define GC_PMU_EXITPD_MASK_PD_EXIT_MASK 0x1 +#define GC_PMU_EXITPD_MASK_PD_EXIT_SIZE 0x1 +#define GC_PMU_EXITPD_MASK_PD_EXIT_DEFAULT 0x1 +#define GC_PMU_EXITPD_MASK_PD_EXIT_OFFSET 0x90 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_LSB 0x1 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_MASK 0x2 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x1 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x90 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_LSB 0x2 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_MASK 0x4 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x1 +#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x90 +#define GC_PMU_EXITPD_SRC_PD_EXIT_LSB 0x0 +#define GC_PMU_EXITPD_SRC_PD_EXIT_MASK 0x1 +#define GC_PMU_EXITPD_SRC_PD_EXIT_SIZE 0x1 +#define GC_PMU_EXITPD_SRC_PD_EXIT_DEFAULT 0x0 +#define GC_PMU_EXITPD_SRC_PD_EXIT_OFFSET 0x94 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_LSB 0x1 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_MASK 0x2 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x0 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x94 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_LSB 0x2 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_MASK 0x4 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x0 +#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x94 +#define GC_PMU_EXITPD_MON_PD_EXIT_LSB 0x0 +#define GC_PMU_EXITPD_MON_PD_EXIT_MASK 0x1 +#define GC_PMU_EXITPD_MON_PD_EXIT_SIZE 0x1 +#define GC_PMU_EXITPD_MON_PD_EXIT_DEFAULT 0x0 +#define GC_PMU_EXITPD_MON_PD_EXIT_OFFSET 0x98 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_LSB 0x1 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_MASK 0x2 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x0 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x98 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_LSB 0x2 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_MASK 0x4 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x0 +#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x98 +#define GC_PMU_OSC_CTRL_XTL_READYB_LSB 0x0 +#define GC_PMU_OSC_CTRL_XTL_READYB_MASK 0x1 +#define GC_PMU_OSC_CTRL_XTL_READYB_SIZE 0x1 +#define GC_PMU_OSC_CTRL_XTL_READYB_DEFAULT 0x1 +#define GC_PMU_OSC_CTRL_XTL_READYB_OFFSET 0xac +#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_LSB 0x1 +#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_MASK 0x2 +#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_SIZE 0x1 +#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_DEFAULT 0x1 +#define GC_PMU_OSC_CTRL_RC_TRIM_READYB_OFFSET 0xac +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_LSB 0x0 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_MASK 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_SIZE 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_DEFAULT 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_OFFSET 0xb0 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_LSB 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_MASK 0x2 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_SIZE 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_DEFAULT 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_OFFSET 0xb0 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_LSB 0x2 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_MASK 0x4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_SIZE 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_DEFAULT 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_OFFSET 0xb0 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_LSB 0x3 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_MASK 0x8 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_SIZE 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_DEFAULT 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_OFFSET 0xb0 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_LSB 0x4 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_MASK 0x10 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_SIZE 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_DEFAULT 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_OFFSET 0xb0 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_LSB 0x5 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_MASK 0x20 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_SIZE 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_DEFAULT 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_OFFSET 0xb0 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_LSB 0x6 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_MASK 0x40 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_SIZE 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_DEFAULT 0x1 +#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_OFFSET 0xb0 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_LSB 0x0 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_MASK 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_SIZE 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_DEFAULT 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_OFFSET 0xb4 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_LSB 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_MASK 0x2 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_SIZE 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_DEFAULT 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_OFFSET 0xb4 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_LSB 0x2 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_MASK 0x4 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_SIZE 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_DEFAULT 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_OFFSET 0xb4 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_LSB 0x3 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_MASK 0x8 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_SIZE 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_DEFAULT 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_OFFSET 0xb4 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_LSB 0x4 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_MASK 0x10 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_SIZE 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_DEFAULT 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_OFFSET 0xb4 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_LSB 0x5 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_MASK 0x20 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_SIZE 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_DEFAULT 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_OFFSET 0xb4 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_LSB 0x6 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_MASK 0x40 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_SIZE 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_DEFAULT 0x1 +#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_OFFSET 0xb4 +#define GC_PMU_PERICLKSET0_DAES0_LSB 0x0 +#define GC_PMU_PERICLKSET0_DAES0_MASK 0x1 +#define GC_PMU_PERICLKSET0_DAES0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DAES0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DAES0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DAES1_LSB 0x1 +#define GC_PMU_PERICLKSET0_DAES1_MASK 0x2 +#define GC_PMU_PERICLKSET0_DAES1_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DAES1_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DAES1_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DCAMO0_LSB 0x2 +#define GC_PMU_PERICLKSET0_DCAMO0_MASK 0x4 +#define GC_PMU_PERICLKSET0_DCAMO0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DCAMO0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DCAMO0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DFLASH0_LSB 0x3 +#define GC_PMU_PERICLKSET0_DFLASH0_MASK 0x8 +#define GC_PMU_PERICLKSET0_DFLASH0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DFLASH0_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DFLASH0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DGLOBALSEC0_LSB 0x4 +#define GC_PMU_PERICLKSET0_DGLOBALSEC0_MASK 0x10 +#define GC_PMU_PERICLKSET0_DGLOBALSEC0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DGLOBALSEC0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DGLOBALSEC0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DGPIO0_LSB 0x5 +#define GC_PMU_PERICLKSET0_DGPIO0_MASK 0x20 +#define GC_PMU_PERICLKSET0_DGPIO0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DGPIO0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DGPIO0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DGPIO1_LSB 0x6 +#define GC_PMU_PERICLKSET0_DGPIO1_MASK 0x40 +#define GC_PMU_PERICLKSET0_DGPIO1_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DGPIO1_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DGPIO1_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DI2C0_LSB 0x7 +#define GC_PMU_PERICLKSET0_DI2C0_MASK 0x80 +#define GC_PMU_PERICLKSET0_DI2C0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DI2C0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DI2C0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DI2C1_LSB 0x8 +#define GC_PMU_PERICLKSET0_DI2C1_MASK 0x100 +#define GC_PMU_PERICLKSET0_DI2C1_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DI2C1_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DI2C1_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DI2CS0_LSB 0x9 +#define GC_PMU_PERICLKSET0_DI2CS0_MASK 0x200 +#define GC_PMU_PERICLKSET0_DI2CS0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DI2CS0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DI2CS0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DMAU_LSB 0xa +#define GC_PMU_PERICLKSET0_DMAU_MASK 0x400 +#define GC_PMU_PERICLKSET0_DMAU_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DMAU_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DMAU_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DPAU_LSB 0xb +#define GC_PMU_PERICLKSET0_DPAU_MASK 0x800 +#define GC_PMU_PERICLKSET0_DPAU_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPAU_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPAU_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DPINMUX_LSB 0xc +#define GC_PMU_PERICLKSET0_DPINMUX_MASK 0x1000 +#define GC_PMU_PERICLKSET0_DPINMUX_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPINMUX_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPINMUX_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DPMU_LSB 0xd +#define GC_PMU_PERICLKSET0_DPMU_MASK 0x2000 +#define GC_PMU_PERICLKSET0_DPMU_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DPMU_DEFAULT 0x1 +#define GC_PMU_PERICLKSET0_DPMU_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DRBOX0_LSB 0xe +#define GC_PMU_PERICLKSET0_DRBOX0_MASK 0x4000 +#define GC_PMU_PERICLKSET0_DRBOX0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DRBOX0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRBOX0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DRTC0_LSB 0xf +#define GC_PMU_PERICLKSET0_DRTC0_MASK 0x8000 +#define GC_PMU_PERICLKSET0_DRTC0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DRTC0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRTC0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DSHA0_LSB 0x10 +#define GC_PMU_PERICLKSET0_DSHA0_MASK 0x10000 +#define GC_PMU_PERICLKSET0_DSHA0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSHA0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DSHA0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DSPI0_LSB 0x11 +#define GC_PMU_PERICLKSET0_DSPI0_MASK 0x20000 +#define GC_PMU_PERICLKSET0_DSPI0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSPI0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DSPI0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DSPS0_LSB 0x12 +#define GC_PMU_PERICLKSET0_DSPS0_MASK 0x40000 +#define GC_PMU_PERICLKSET0_DSPS0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSPS0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DSPS0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DSWDP0_LSB 0x13 +#define GC_PMU_PERICLKSET0_DSWDP0_MASK 0x80000 +#define GC_PMU_PERICLKSET0_DSWDP0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DSWDP0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DSWDP0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DTEMP0_LSB 0x14 +#define GC_PMU_PERICLKSET0_DTEMP0_MASK 0x100000 +#define GC_PMU_PERICLKSET0_DTEMP0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DTEMP0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DTEMP0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DTIMEHS0_LSB 0x15 +#define GC_PMU_PERICLKSET0_DTIMEHS0_MASK 0x200000 +#define GC_PMU_PERICLKSET0_DTIMEHS0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DTIMEHS0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DTIMEHS0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DTIMEHS1_LSB 0x16 +#define GC_PMU_PERICLKSET0_DTIMEHS1_MASK 0x400000 +#define GC_PMU_PERICLKSET0_DTIMEHS1_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DTIMEHS1_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DTIMEHS1_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DTIMELS0_LSB 0x17 +#define GC_PMU_PERICLKSET0_DTIMELS0_MASK 0x800000 +#define GC_PMU_PERICLKSET0_DTIMELS0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DTIMELS0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DTIMELS0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DTRNG0_LSB 0x18 +#define GC_PMU_PERICLKSET0_DTRNG0_MASK 0x1000000 +#define GC_PMU_PERICLKSET0_DTRNG0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DTRNG0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DTRNG0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DUART0_LSB 0x19 +#define GC_PMU_PERICLKSET0_DUART0_MASK 0x2000000 +#define GC_PMU_PERICLKSET0_DUART0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DUART0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DUART0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DUART1_LSB 0x1a +#define GC_PMU_PERICLKSET0_DUART1_MASK 0x4000000 +#define GC_PMU_PERICLKSET0_DUART1_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DUART1_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DUART1_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DUART2_LSB 0x1b +#define GC_PMU_PERICLKSET0_DUART2_MASK 0x8000000 +#define GC_PMU_PERICLKSET0_DUART2_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DUART2_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DUART2_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DUSB0_LSB 0x1c +#define GC_PMU_PERICLKSET0_DUSB0_MASK 0x10000000 +#define GC_PMU_PERICLKSET0_DUSB0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DUSB0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DUSB0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_LSB 0x1d +#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_MASK 0x20000000 +#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DUSB0_USB_PHY_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DWATCHDOG0_LSB 0x1e +#define GC_PMU_PERICLKSET0_DWATCHDOG0_MASK 0x40000000 +#define GC_PMU_PERICLKSET0_DWATCHDOG0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DWATCHDOG0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DWATCHDOG0_OFFSET 0xb8 +#define GC_PMU_PERICLKSET0_DXO0_LSB 0x1f +#define GC_PMU_PERICLKSET0_DXO0_MASK 0x80000000 +#define GC_PMU_PERICLKSET0_DXO0_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DXO0_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DXO0_OFFSET 0xb8 +#define GC_PMU_PERICLKCLR0_DAES0_LSB 0x0 +#define GC_PMU_PERICLKCLR0_DAES0_MASK 0x1 +#define GC_PMU_PERICLKCLR0_DAES0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DAES0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DAES0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DAES1_LSB 0x1 +#define GC_PMU_PERICLKCLR0_DAES1_MASK 0x2 +#define GC_PMU_PERICLKCLR0_DAES1_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DAES1_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DAES1_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DCAMO0_LSB 0x2 +#define GC_PMU_PERICLKCLR0_DCAMO0_MASK 0x4 +#define GC_PMU_PERICLKCLR0_DCAMO0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DCAMO0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DCAMO0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DFLASH0_LSB 0x3 +#define GC_PMU_PERICLKCLR0_DFLASH0_MASK 0x8 +#define GC_PMU_PERICLKCLR0_DFLASH0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DFLASH0_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DFLASH0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DGLOBALSEC0_LSB 0x4 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC0_MASK 0x10 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DGPIO0_LSB 0x5 +#define GC_PMU_PERICLKCLR0_DGPIO0_MASK 0x20 +#define GC_PMU_PERICLKCLR0_DGPIO0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DGPIO0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DGPIO0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DGPIO1_LSB 0x6 +#define GC_PMU_PERICLKCLR0_DGPIO1_MASK 0x40 +#define GC_PMU_PERICLKCLR0_DGPIO1_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DGPIO1_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DGPIO1_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DI2C0_LSB 0x7 +#define GC_PMU_PERICLKCLR0_DI2C0_MASK 0x80 +#define GC_PMU_PERICLKCLR0_DI2C0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DI2C0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DI2C0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DI2C1_LSB 0x8 +#define GC_PMU_PERICLKCLR0_DI2C1_MASK 0x100 +#define GC_PMU_PERICLKCLR0_DI2C1_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DI2C1_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DI2C1_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DI2CS0_LSB 0x9 +#define GC_PMU_PERICLKCLR0_DI2CS0_MASK 0x200 +#define GC_PMU_PERICLKCLR0_DI2CS0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DI2CS0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DI2CS0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DMAU_LSB 0xa +#define GC_PMU_PERICLKCLR0_DMAU_MASK 0x400 +#define GC_PMU_PERICLKCLR0_DMAU_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DMAU_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DMAU_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DPAU_LSB 0xb +#define GC_PMU_PERICLKCLR0_DPAU_MASK 0x800 +#define GC_PMU_PERICLKCLR0_DPAU_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPAU_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPAU_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DPINMUX_LSB 0xc +#define GC_PMU_PERICLKCLR0_DPINMUX_MASK 0x1000 +#define GC_PMU_PERICLKCLR0_DPINMUX_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPINMUX_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPINMUX_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DPMU_LSB 0xd +#define GC_PMU_PERICLKCLR0_DPMU_MASK 0x2000 +#define GC_PMU_PERICLKCLR0_DPMU_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DPMU_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR0_DPMU_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DRBOX0_LSB 0xe +#define GC_PMU_PERICLKCLR0_DRBOX0_MASK 0x4000 +#define GC_PMU_PERICLKCLR0_DRBOX0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DRBOX0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRBOX0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DRTC0_LSB 0xf +#define GC_PMU_PERICLKCLR0_DRTC0_MASK 0x8000 +#define GC_PMU_PERICLKCLR0_DRTC0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DRTC0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRTC0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DSHA0_LSB 0x10 +#define GC_PMU_PERICLKCLR0_DSHA0_MASK 0x10000 +#define GC_PMU_PERICLKCLR0_DSHA0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSHA0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DSHA0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DSPI0_LSB 0x11 +#define GC_PMU_PERICLKCLR0_DSPI0_MASK 0x20000 +#define GC_PMU_PERICLKCLR0_DSPI0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSPI0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DSPI0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DSPS0_LSB 0x12 +#define GC_PMU_PERICLKCLR0_DSPS0_MASK 0x40000 +#define GC_PMU_PERICLKCLR0_DSPS0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSPS0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DSPS0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DSWDP0_LSB 0x13 +#define GC_PMU_PERICLKCLR0_DSWDP0_MASK 0x80000 +#define GC_PMU_PERICLKCLR0_DSWDP0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DSWDP0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DSWDP0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DTEMP0_LSB 0x14 +#define GC_PMU_PERICLKCLR0_DTEMP0_MASK 0x100000 +#define GC_PMU_PERICLKCLR0_DTEMP0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DTEMP0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DTEMP0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DTIMEHS0_LSB 0x15 +#define GC_PMU_PERICLKCLR0_DTIMEHS0_MASK 0x200000 +#define GC_PMU_PERICLKCLR0_DTIMEHS0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DTIMEHS0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DTIMEHS0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DTIMEHS1_LSB 0x16 +#define GC_PMU_PERICLKCLR0_DTIMEHS1_MASK 0x400000 +#define GC_PMU_PERICLKCLR0_DTIMEHS1_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DTIMEHS1_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DTIMEHS1_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DTIMELS0_LSB 0x17 +#define GC_PMU_PERICLKCLR0_DTIMELS0_MASK 0x800000 +#define GC_PMU_PERICLKCLR0_DTIMELS0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DTIMELS0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DTIMELS0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DTRNG0_LSB 0x18 +#define GC_PMU_PERICLKCLR0_DTRNG0_MASK 0x1000000 +#define GC_PMU_PERICLKCLR0_DTRNG0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DTRNG0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DTRNG0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DUART0_LSB 0x19 +#define GC_PMU_PERICLKCLR0_DUART0_MASK 0x2000000 +#define GC_PMU_PERICLKCLR0_DUART0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DUART0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DUART0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DUART1_LSB 0x1a +#define GC_PMU_PERICLKCLR0_DUART1_MASK 0x4000000 +#define GC_PMU_PERICLKCLR0_DUART1_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DUART1_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DUART1_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DUART2_LSB 0x1b +#define GC_PMU_PERICLKCLR0_DUART2_MASK 0x8000000 +#define GC_PMU_PERICLKCLR0_DUART2_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DUART2_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DUART2_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DUSB0_LSB 0x1c +#define GC_PMU_PERICLKCLR0_DUSB0_MASK 0x10000000 +#define GC_PMU_PERICLKCLR0_DUSB0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DUSB0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DUSB0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_LSB 0x1d +#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_MASK 0x20000000 +#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DUSB0_USB_PHY_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DWATCHDOG0_LSB 0x1e +#define GC_PMU_PERICLKCLR0_DWATCHDOG0_MASK 0x40000000 +#define GC_PMU_PERICLKCLR0_DWATCHDOG0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DWATCHDOG0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DWATCHDOG0_OFFSET 0xbc +#define GC_PMU_PERICLKCLR0_DXO0_LSB 0x1f +#define GC_PMU_PERICLKCLR0_DXO0_MASK 0x80000000 +#define GC_PMU_PERICLKCLR0_DXO0_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DXO0_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DXO0_OFFSET 0xbc +#define GC_PMU_PERICLKSET1_PERI0_LSB 0x0 +#define GC_PMU_PERICLKSET1_PERI0_MASK 0x1 +#define GC_PMU_PERICLKSET1_PERI0_SIZE 0x1 +#define GC_PMU_PERICLKSET1_PERI0_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_PERI0_OFFSET 0xc0 +#define GC_PMU_PERICLKSET1_PERI1_LSB 0x1 +#define GC_PMU_PERICLKSET1_PERI1_MASK 0x2 +#define GC_PMU_PERICLKSET1_PERI1_SIZE 0x1 +#define GC_PMU_PERICLKSET1_PERI1_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_PERI1_OFFSET 0xc0 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_LSB 0x2 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_MASK 0x4 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_SIZE 0x1 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_DEFAULT 0x1 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_OFFSET 0xc0 +#define GC_PMU_PERICLKCLR1_PERI0_LSB 0x0 +#define GC_PMU_PERICLKCLR1_PERI0_MASK 0x1 +#define GC_PMU_PERICLKCLR1_PERI0_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_PERI0_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_PERI0_OFFSET 0xc4 +#define GC_PMU_PERICLKCLR1_PERI1_LSB 0x1 +#define GC_PMU_PERICLKCLR1_PERI1_MASK 0x2 +#define GC_PMU_PERICLKCLR1_PERI1_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_PERI1_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_PERI1_OFFSET 0xc4 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_LSB 0x2 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_MASK 0x4 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_SIZE 0x1 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_DEFAULT 0x1 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_OFFSET 0xc4 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_MASK 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_MASK 0x2 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DAES1_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_MASK 0x8 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC0_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC0_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPAU_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_LSB 0xe +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_LSB 0xf +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_LSB 0x10 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSHA0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_LSB 0x11 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_MASK 0x20000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_LSB 0x12 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_MASK 0x40000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_LSB 0x13 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_MASK 0x80000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_LSB 0x14 +#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_MASK 0x100000 +#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_LSB 0x15 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_MASK 0x200000 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_LSB 0x16 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_MASK 0x400000 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_LSB 0x17 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_MASK 0x800000 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMELS0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_LSB 0x18 +#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_MASK 0x1000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DTRNG0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_LSB 0x19 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_MASK 0x2000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_LSB 0x1a +#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_MASK 0x4000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART1_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_LSB 0x1b +#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_MASK 0x8000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DUART2_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_LSB 0x1c +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_MASK 0x10000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_LSB 0x1d +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_MASK 0x20000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DUSB0_USB_PHY_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_LSB 0x1e +#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_MASK 0x40000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DWATCHDOG0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_LSB 0x1f +#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_MASK 0x80000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DXO0_OFFSET 0xc8 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_MASK 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_MASK 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DAES1_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_MASK 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC0_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC0_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPAU_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_LSB 0xe +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_LSB 0xf +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_LSB 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSHA0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_LSB 0x11 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_MASK 0x20000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_LSB 0x12 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_MASK 0x40000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_LSB 0x13 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_MASK 0x80000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_LSB 0x14 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_MASK 0x100000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_LSB 0x15 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_MASK 0x200000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_LSB 0x16 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_MASK 0x400000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_LSB 0x17 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_MASK 0x800000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMELS0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_LSB 0x18 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_MASK 0x1000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTRNG0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_LSB 0x19 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_MASK 0x2000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_LSB 0x1a +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_MASK 0x4000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART1_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_LSB 0x1b +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_MASK 0x8000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUART2_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_LSB 0x1c +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_MASK 0x10000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_LSB 0x1d +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_MASK 0x20000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DUSB0_USB_PHY_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_LSB 0x1e +#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_MASK 0x40000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DWATCHDOG0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_LSB 0x1f +#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_MASK 0x80000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DXO0_OFFSET 0xcc +#define GC_PMU_PERIGATEONSLEEPSET1_PERI0_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI0_MASK 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI0_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI0_OFFSET 0xd0 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_MASK 0x2 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI1_OFFSET 0xd0 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_OFFSET 0xd0 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI0_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI0_MASK 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI0_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI0_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI0_OFFSET 0xd4 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_MASK 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI1_OFFSET 0xd4 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_DEFAULT 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_OFFSET 0xd4 +#define GC_PMU_CLK0_HCLKGATEEN_LSB 0x0 +#define GC_PMU_CLK0_HCLKGATEEN_MASK 0x1 +#define GC_PMU_CLK0_HCLKGATEEN_SIZE 0x1 +#define GC_PMU_CLK0_HCLKGATEEN_DEFAULT 0x1 +#define GC_PMU_CLK0_HCLKGATEEN_OFFSET 0xd8 +#define GC_PMU_CLK0_DAPCLKGATEEN_LSB 0x1 +#define GC_PMU_CLK0_DAPCLKGATEEN_MASK 0x2 +#define GC_PMU_CLK0_DAPCLKGATEEN_SIZE 0x1 +#define GC_PMU_CLK0_DAPCLKGATEEN_DEFAULT 0x1 +#define GC_PMU_CLK0_DAPCLKGATEEN_OFFSET 0xd8 +#define GC_PMU_CLK0_TPIUGATEEN_LSB 0x2 +#define GC_PMU_CLK0_TPIUGATEEN_MASK 0x4 +#define GC_PMU_CLK0_TPIUGATEEN_SIZE 0x1 +#define GC_PMU_CLK0_TPIUGATEEN_DEFAULT 0x1 +#define GC_PMU_CLK0_TPIUGATEEN_OFFSET 0xd8 +#define GC_PMU_CLK0_FCLKEN_LSB 0x3 +#define GC_PMU_CLK0_FCLKEN_MASK 0x8 +#define GC_PMU_CLK0_FCLKEN_SIZE 0x1 +#define GC_PMU_CLK0_FCLKEN_DEFAULT 0x1 +#define GC_PMU_CLK0_FCLKEN_OFFSET 0xd8 +#define GC_PMU_CLK0_DAPCLKEN_LSB 0x4 +#define GC_PMU_CLK0_DAPCLKEN_MASK 0x10 +#define GC_PMU_CLK0_DAPCLKEN_SIZE 0x1 +#define GC_PMU_CLK0_DAPCLKEN_DEFAULT 0x1 +#define GC_PMU_CLK0_DAPCLKEN_OFFSET 0xd8 +#define GC_PMU_CLK0_TPIUCLKEN_LSB 0x5 +#define GC_PMU_CLK0_TPIUCLKEN_MASK 0x20 +#define GC_PMU_CLK0_TPIUCLKEN_SIZE 0x1 +#define GC_PMU_CLK0_TPIUCLKEN_DEFAULT 0x0 +#define GC_PMU_CLK0_TPIUCLKEN_OFFSET 0xd8 +#define GC_PMU_CLK0_TRACECLKEN_LSB 0x6 +#define GC_PMU_CLK0_TRACECLKEN_MASK 0x40 +#define GC_PMU_CLK0_TRACECLKEN_SIZE 0x1 +#define GC_PMU_CLK0_TRACECLKEN_DEFAULT 0x0 +#define GC_PMU_CLK0_TRACECLKEN_OFFSET 0xd8 +#define GC_PMU_CLK1_HCLKGATEEN_LSB 0x0 +#define GC_PMU_CLK1_HCLKGATEEN_MASK 0x1 +#define GC_PMU_CLK1_HCLKGATEEN_SIZE 0x1 +#define GC_PMU_CLK1_HCLKGATEEN_DEFAULT 0x1 +#define GC_PMU_CLK1_HCLKGATEEN_OFFSET 0xdc +#define GC_PMU_CLK1_DAPCLKGATEEN_LSB 0x1 +#define GC_PMU_CLK1_DAPCLKGATEEN_MASK 0x2 +#define GC_PMU_CLK1_DAPCLKGATEEN_SIZE 0x1 +#define GC_PMU_CLK1_DAPCLKGATEEN_DEFAULT 0x1 +#define GC_PMU_CLK1_DAPCLKGATEEN_OFFSET 0xdc +#define GC_PMU_CLK1_TPIUGATEEN_LSB 0x2 +#define GC_PMU_CLK1_TPIUGATEEN_MASK 0x4 +#define GC_PMU_CLK1_TPIUGATEEN_SIZE 0x1 +#define GC_PMU_CLK1_TPIUGATEEN_DEFAULT 0x1 +#define GC_PMU_CLK1_TPIUGATEEN_OFFSET 0xdc +#define GC_PMU_CLK1_FCLKEN_LSB 0x3 +#define GC_PMU_CLK1_FCLKEN_MASK 0x8 +#define GC_PMU_CLK1_FCLKEN_SIZE 0x1 +#define GC_PMU_CLK1_FCLKEN_DEFAULT 0x1 +#define GC_PMU_CLK1_FCLKEN_OFFSET 0xdc +#define GC_PMU_CLK1_DAPCLKEN_LSB 0x4 +#define GC_PMU_CLK1_DAPCLKEN_MASK 0x10 +#define GC_PMU_CLK1_DAPCLKEN_SIZE 0x1 +#define GC_PMU_CLK1_DAPCLKEN_DEFAULT 0x1 +#define GC_PMU_CLK1_DAPCLKEN_OFFSET 0xdc +#define GC_PMU_CLK1_TPIUCLKEN_LSB 0x5 +#define GC_PMU_CLK1_TPIUCLKEN_MASK 0x20 +#define GC_PMU_CLK1_TPIUCLKEN_SIZE 0x1 +#define GC_PMU_CLK1_TPIUCLKEN_DEFAULT 0x0 +#define GC_PMU_CLK1_TPIUCLKEN_OFFSET 0xdc +#define GC_PMU_CLK1_TRACECLKEN_LSB 0x6 +#define GC_PMU_CLK1_TRACECLKEN_MASK 0x40 +#define GC_PMU_CLK1_TRACECLKEN_SIZE 0x1 +#define GC_PMU_CLK1_TRACECLKEN_DEFAULT 0x0 +#define GC_PMU_CLK1_TRACECLKEN_OFFSET 0xdc +#define GC_PMU_RST0_DXO0_LSB 0x0 +#define GC_PMU_RST0_DXO0_MASK 0x1 +#define GC_PMU_RST0_DXO0_SIZE 0x1 +#define GC_PMU_RST0_DXO0_DEFAULT 0x0 +#define GC_PMU_RST0_DXO0_OFFSET 0xe0 +#define GC_PMU_RST0_DSPI0_LSB 0x1 +#define GC_PMU_RST0_DSPI0_MASK 0x2 +#define GC_PMU_RST0_DSPI0_SIZE 0x1 +#define GC_PMU_RST0_DSPI0_DEFAULT 0x0 +#define GC_PMU_RST0_DSPI0_OFFSET 0xe0 +#define GC_PMU_RST0_DAES0_LSB 0x2 +#define GC_PMU_RST0_DAES0_MASK 0x4 +#define GC_PMU_RST0_DAES0_SIZE 0x1 +#define GC_PMU_RST0_DAES0_DEFAULT 0x0 +#define GC_PMU_RST0_DAES0_OFFSET 0xe0 +#define GC_PMU_RST0_PERI0_LSB 0x3 +#define GC_PMU_RST0_PERI0_MASK 0x8 +#define GC_PMU_RST0_PERI0_SIZE 0x1 +#define GC_PMU_RST0_PERI0_DEFAULT 0x0 +#define GC_PMU_RST0_PERI0_OFFSET 0xe0 +#define GC_PMU_RST0_DI2CS0_LSB 0x4 +#define GC_PMU_RST0_DI2CS0_MASK 0x10 +#define GC_PMU_RST0_DI2CS0_SIZE 0x1 +#define GC_PMU_RST0_DI2CS0_DEFAULT 0x0 +#define GC_PMU_RST0_DI2CS0_OFFSET 0xe0 +#define GC_PMU_RST0_DUART0_LSB 0x5 +#define GC_PMU_RST0_DUART0_MASK 0x20 +#define GC_PMU_RST0_DUART0_SIZE 0x1 +#define GC_PMU_RST0_DUART0_DEFAULT 0x0 +#define GC_PMU_RST0_DUART0_OFFSET 0xe0 +#define GC_PMU_RST0_DI2C1_LSB 0x6 +#define GC_PMU_RST0_DI2C1_MASK 0x40 +#define GC_PMU_RST0_DI2C1_SIZE 0x1 +#define GC_PMU_RST0_DI2C1_DEFAULT 0x0 +#define GC_PMU_RST0_DI2C1_OFFSET 0xe0 +#define GC_PMU_RST0_DAES1_LSB 0x7 +#define GC_PMU_RST0_DAES1_MASK 0x80 +#define GC_PMU_RST0_DAES1_SIZE 0x1 +#define GC_PMU_RST0_DAES1_DEFAULT 0x0 +#define GC_PMU_RST0_DAES1_OFFSET 0xe0 +#define GC_PMU_RST0_DTIMELS0_LSB 0x8 +#define GC_PMU_RST0_DTIMELS0_MASK 0x100 +#define GC_PMU_RST0_DTIMELS0_SIZE 0x1 +#define GC_PMU_RST0_DTIMELS0_DEFAULT 0x0 +#define GC_PMU_RST0_DTIMELS0_OFFSET 0xe0 +#define GC_PMU_RST0_DTEMP0_LSB 0x9 +#define GC_PMU_RST0_DTEMP0_MASK 0x200 +#define GC_PMU_RST0_DTEMP0_SIZE 0x1 +#define GC_PMU_RST0_DTEMP0_DEFAULT 0x0 +#define GC_PMU_RST0_DTEMP0_OFFSET 0xe0 +#define GC_PMU_RST0_DRTC0_LSB 0xa +#define GC_PMU_RST0_DRTC0_MASK 0x400 +#define GC_PMU_RST0_DRTC0_SIZE 0x1 +#define GC_PMU_RST0_DRTC0_DEFAULT 0x0 +#define GC_PMU_RST0_DRTC0_OFFSET 0xe0 +#define GC_PMU_RST0_DRBOX0_LSB 0xb +#define GC_PMU_RST0_DRBOX0_MASK 0x800 +#define GC_PMU_RST0_DRBOX0_SIZE 0x1 +#define GC_PMU_RST0_DRBOX0_DEFAULT 0x0 +#define GC_PMU_RST0_DRBOX0_OFFSET 0xe0 +#define GC_PMU_RST0_DUART1_LSB 0xc +#define GC_PMU_RST0_DUART1_MASK 0x1000 +#define GC_PMU_RST0_DUART1_SIZE 0x1 +#define GC_PMU_RST0_DUART1_DEFAULT 0x0 +#define GC_PMU_RST0_DUART1_OFFSET 0xe0 +#define GC_PMU_RST0_DWATCHDOG0_LSB 0xd +#define GC_PMU_RST0_DWATCHDOG0_MASK 0x2000 +#define GC_PMU_RST0_DWATCHDOG0_SIZE 0x1 +#define GC_PMU_RST0_DWATCHDOG0_DEFAULT 0x0 +#define GC_PMU_RST0_DWATCHDOG0_OFFSET 0xe0 +#define GC_PMU_RST0_DUART2_LSB 0xe +#define GC_PMU_RST0_DUART2_MASK 0x4000 +#define GC_PMU_RST0_DUART2_SIZE 0x1 +#define GC_PMU_RST0_DUART2_DEFAULT 0x0 +#define GC_PMU_RST0_DUART2_OFFSET 0xe0 +#define GC_PMU_RST0_DPMU_LSB 0xf +#define GC_PMU_RST0_DPMU_MASK 0x8000 +#define GC_PMU_RST0_DPMU_SIZE 0x1 +#define GC_PMU_RST0_DPMU_DEFAULT 0x0 +#define GC_PMU_RST0_DPMU_OFFSET 0xe0 +#define GC_PMU_RST0_DMAU_LSB 0x10 +#define GC_PMU_RST0_DMAU_MASK 0x10000 +#define GC_PMU_RST0_DMAU_SIZE 0x1 +#define GC_PMU_RST0_DMAU_DEFAULT 0x0 +#define GC_PMU_RST0_DMAU_OFFSET 0xe0 +#define GC_PMU_RST0_DI2C0_LSB 0x11 +#define GC_PMU_RST0_DI2C0_MASK 0x20000 +#define GC_PMU_RST0_DI2C0_SIZE 0x1 +#define GC_PMU_RST0_DI2C0_DEFAULT 0x0 +#define GC_PMU_RST0_DI2C0_OFFSET 0xe0 +#define GC_PMU_RST0_DGLOBALSEC0_LSB 0x12 +#define GC_PMU_RST0_DGLOBALSEC0_MASK 0x40000 +#define GC_PMU_RST0_DGLOBALSEC0_SIZE 0x1 +#define GC_PMU_RST0_DGLOBALSEC0_DEFAULT 0x0 +#define GC_PMU_RST0_DGLOBALSEC0_OFFSET 0xe0 +#define GC_PMU_RST0_DSWDP0_LSB 0x13 +#define GC_PMU_RST0_DSWDP0_MASK 0x80000 +#define GC_PMU_RST0_DSWDP0_SIZE 0x1 +#define GC_PMU_RST0_DSWDP0_DEFAULT 0x0 +#define GC_PMU_RST0_DSWDP0_OFFSET 0xe0 +#define GC_PMU_RST0_DPAU_LSB 0x14 +#define GC_PMU_RST0_DPAU_MASK 0x100000 +#define GC_PMU_RST0_DPAU_SIZE 0x1 +#define GC_PMU_RST0_DPAU_DEFAULT 0x0 +#define GC_PMU_RST0_DPAU_OFFSET 0xe0 +#define GC_PMU_RST0_DCAMO0_LSB 0x15 +#define GC_PMU_RST0_DCAMO0_MASK 0x200000 +#define GC_PMU_RST0_DCAMO0_SIZE 0x1 +#define GC_PMU_RST0_DCAMO0_DEFAULT 0x0 +#define GC_PMU_RST0_DCAMO0_OFFSET 0xe0 +#define GC_PMU_RST0_DTRNG0_LSB 0x16 +#define GC_PMU_RST0_DTRNG0_MASK 0x400000 +#define GC_PMU_RST0_DTRNG0_SIZE 0x1 +#define GC_PMU_RST0_DTRNG0_DEFAULT 0x0 +#define GC_PMU_RST0_DTRNG0_OFFSET 0xe0 +#define GC_PMU_RST0_PERI_MATRIX_LSB 0x17 +#define GC_PMU_RST0_PERI_MATRIX_MASK 0x800000 +#define GC_PMU_RST0_PERI_MATRIX_SIZE 0x1 +#define GC_PMU_RST0_PERI_MATRIX_DEFAULT 0x0 +#define GC_PMU_RST0_PERI_MATRIX_OFFSET 0xe0 +#define GC_PMU_RST0_PERI1_LSB 0x18 +#define GC_PMU_RST0_PERI1_MASK 0x1000000 +#define GC_PMU_RST0_PERI1_SIZE 0x1 +#define GC_PMU_RST0_PERI1_DEFAULT 0x0 +#define GC_PMU_RST0_PERI1_OFFSET 0xe0 +#define GC_PMU_RST0_DGPIO1_LSB 0x19 +#define GC_PMU_RST0_DGPIO1_MASK 0x2000000 +#define GC_PMU_RST0_DGPIO1_SIZE 0x1 +#define GC_PMU_RST0_DGPIO1_DEFAULT 0x0 +#define GC_PMU_RST0_DGPIO1_OFFSET 0xe0 +#define GC_PMU_RST0_DTIMEHS0_LSB 0x1a +#define GC_PMU_RST0_DTIMEHS0_MASK 0x4000000 +#define GC_PMU_RST0_DTIMEHS0_SIZE 0x1 +#define GC_PMU_RST0_DTIMEHS0_DEFAULT 0x0 +#define GC_PMU_RST0_DTIMEHS0_OFFSET 0xe0 +#define GC_PMU_RST0_DSPS0_LSB 0x1b +#define GC_PMU_RST0_DSPS0_MASK 0x8000000 +#define GC_PMU_RST0_DSPS0_SIZE 0x1 +#define GC_PMU_RST0_DSPS0_DEFAULT 0x0 +#define GC_PMU_RST0_DSPS0_OFFSET 0xe0 +#define GC_PMU_RST0_DUSB0_LSB 0x1c +#define GC_PMU_RST0_DUSB0_MASK 0x10000000 +#define GC_PMU_RST0_DUSB0_SIZE 0x1 +#define GC_PMU_RST0_DUSB0_DEFAULT 0x0 +#define GC_PMU_RST0_DUSB0_OFFSET 0xe0 +#define GC_PMU_RST0_DPINMUX_LSB 0x1d +#define GC_PMU_RST0_DPINMUX_MASK 0x20000000 +#define GC_PMU_RST0_DPINMUX_SIZE 0x1 +#define GC_PMU_RST0_DPINMUX_DEFAULT 0x0 +#define GC_PMU_RST0_DPINMUX_OFFSET 0xe0 +#define GC_PMU_RST0_DTIMEHS1_LSB 0x1e +#define GC_PMU_RST0_DTIMEHS1_MASK 0x40000000 +#define GC_PMU_RST0_DTIMEHS1_SIZE 0x1 +#define GC_PMU_RST0_DTIMEHS1_DEFAULT 0x0 +#define GC_PMU_RST0_DTIMEHS1_OFFSET 0xe0 +#define GC_PMU_RST0_DSHA0_LSB 0x1f +#define GC_PMU_RST0_DSHA0_MASK 0x80000000 +#define GC_PMU_RST0_DSHA0_SIZE 0x1 +#define GC_PMU_RST0_DSHA0_DEFAULT 0x0 +#define GC_PMU_RST0_DSHA0_OFFSET 0xe0 +#define GC_PMU_RST1_DFLASH0_LSB 0x0 +#define GC_PMU_RST1_DFLASH0_MASK 0x1 +#define GC_PMU_RST1_DFLASH0_SIZE 0x1 +#define GC_PMU_RST1_DFLASH0_DEFAULT 0x0 +#define GC_PMU_RST1_DFLASH0_OFFSET 0xe4 +#define GC_PMU_RST1_DGPIO0_LSB 0x1 +#define GC_PMU_RST1_DGPIO0_MASK 0x2 +#define GC_PMU_RST1_DGPIO0_SIZE 0x1 +#define GC_PMU_RST1_DGPIO0_DEFAULT 0x0 +#define GC_PMU_RST1_DGPIO0_OFFSET 0xe4 +#define GC_PMU_RST1_DUSB0_USB_PHY_CLK_LSB 0x2 +#define GC_PMU_RST1_DUSB0_USB_PHY_CLK_MASK 0x4 +#define GC_PMU_RST1_DUSB0_USB_PHY_CLK_SIZE 0x1 +#define GC_PMU_RST1_DUSB0_USB_PHY_CLK_DEFAULT 0x0 +#define GC_PMU_RST1_DUSB0_USB_PHY_CLK_OFFSET 0xe4 +#define GC_PMU_FUSE_CTRL_WRITE_LSB 0x0 +#define GC_PMU_FUSE_CTRL_WRITE_MASK 0x1 +#define GC_PMU_FUSE_CTRL_WRITE_SIZE 0x1 +#define GC_PMU_FUSE_CTRL_WRITE_DEFAULT 0x0 +#define GC_PMU_FUSE_CTRL_WRITE_OFFSET 0x10c +#define GC_PMU_FUSE_WR_ID_PKG_LSB 0x0 +#define GC_PMU_FUSE_WR_ID_PKG_MASK 0x7 +#define GC_PMU_FUSE_WR_ID_PKG_SIZE 0x3 +#define GC_PMU_FUSE_WR_ID_PKG_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_ID_PKG_OFFSET 0x118 +#define GC_PMU_FUSE_WR_ID_BIN_LSB 0x3 +#define GC_PMU_FUSE_WR_ID_BIN_MASK 0x38 +#define GC_PMU_FUSE_WR_ID_BIN_SIZE 0x3 +#define GC_PMU_FUSE_WR_ID_BIN_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_ID_BIN_OFFSET 0x118 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_LSB 0x0 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_MASK 0xfffffff +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_SIZE 0x1c +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_TRIM_OFFSET 0x11c +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_LSB 0x1c +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_MASK 0x10000000 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_SIZE 0x1 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RC_OSC_26MHZ_EN_OFFSET 0x11c +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_LSB 0x0 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_MASK 0xff +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_SIZE 0x8 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_TRIM_OFFSET 0x120 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_LSB 0x8 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_MASK 0x100 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_SIZE 0x1 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_RC_OSC_32KHZ_EN_OFFSET 0x120 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_LSB 0x0 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_MASK 0xf +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_SIZE 0x4 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_TRIM_OFFSET 0x124 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_LSB 0x4 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_MASK 0x10 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_SIZE 0x1 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_XTL_OSC_26MHZ_EN_OFFSET 0x124 +#define GC_PMU_FUSE_WR_LOCK_TESTMODE_LSB 0x0 +#define GC_PMU_FUSE_WR_LOCK_TESTMODE_MASK 0x1 +#define GC_PMU_FUSE_WR_LOCK_TESTMODE_SIZE 0x1 +#define GC_PMU_FUSE_WR_LOCK_TESTMODE_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_LOCK_TESTMODE_OFFSET 0x128 +#define GC_PMU_FUSE_WR_LOCK_DAP_LSB 0x1 +#define GC_PMU_FUSE_WR_LOCK_DAP_MASK 0x2 +#define GC_PMU_FUSE_WR_LOCK_DAP_SIZE 0x1 +#define GC_PMU_FUSE_WR_LOCK_DAP_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_LOCK_DAP_OFFSET 0x128 +#define GC_PMU_FUSE_WR_LOCK_FUSE_LSB 0x2 +#define GC_PMU_FUSE_WR_LOCK_FUSE_MASK 0x4 +#define GC_PMU_FUSE_WR_LOCK_FUSE_SIZE 0x1 +#define GC_PMU_FUSE_WR_LOCK_FUSE_DEFAULT 0x0 +#define GC_PMU_FUSE_WR_LOCK_FUSE_OFFSET 0x128 +#define GC_PMU_FUSE_RD_ID_PKG_LSB 0x0 +#define GC_PMU_FUSE_RD_ID_PKG_MASK 0x7 +#define GC_PMU_FUSE_RD_ID_PKG_SIZE 0x3 +#define GC_PMU_FUSE_RD_ID_PKG_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_ID_PKG_OFFSET 0x148 +#define GC_PMU_FUSE_RD_ID_BIN_LSB 0x3 +#define GC_PMU_FUSE_RD_ID_BIN_MASK 0x38 +#define GC_PMU_FUSE_RD_ID_BIN_SIZE 0x3 +#define GC_PMU_FUSE_RD_ID_BIN_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_ID_BIN_OFFSET 0x148 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_LSB 0x0 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_MASK 0xfffffff +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_SIZE 0x1c +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_TRIM_OFFSET 0x14c +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_LSB 0x1c +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_MASK 0x10000000 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_SIZE 0x1 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RC_OSC_26MHZ_EN_OFFSET 0x14c +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_LSB 0x0 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_MASK 0xff +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_SIZE 0x8 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_TRIM_OFFSET 0x150 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_LSB 0x8 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_MASK 0x100 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_SIZE 0x1 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_RC_OSC_32KHZ_EN_OFFSET 0x150 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_LSB 0x0 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_MASK 0xf +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_SIZE 0x4 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_TRIM_OFFSET 0x154 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_LSB 0x4 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_MASK 0x10 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_SIZE 0x1 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_XTL_OSC_26MHZ_EN_OFFSET 0x154 +#define GC_PMU_FUSE_RD_LOCK_TESTMODE_LSB 0x0 +#define GC_PMU_FUSE_RD_LOCK_TESTMODE_MASK 0x1 +#define GC_PMU_FUSE_RD_LOCK_TESTMODE_SIZE 0x1 +#define GC_PMU_FUSE_RD_LOCK_TESTMODE_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_LOCK_TESTMODE_OFFSET 0x158 +#define GC_PMU_FUSE_RD_LOCK_DAP_LSB 0x1 +#define GC_PMU_FUSE_RD_LOCK_DAP_MASK 0x2 +#define GC_PMU_FUSE_RD_LOCK_DAP_SIZE 0x1 +#define GC_PMU_FUSE_RD_LOCK_DAP_DEFAULT 0x1 +#define GC_PMU_FUSE_RD_LOCK_DAP_OFFSET 0x158 +#define GC_PMU_FUSE_RD_LOCK_FUSE_LSB 0x2 +#define GC_PMU_FUSE_RD_LOCK_FUSE_MASK 0x4 +#define GC_PMU_FUSE_RD_LOCK_FUSE_SIZE 0x1 +#define GC_PMU_FUSE_RD_LOCK_FUSE_DEFAULT 0x0 +#define GC_PMU_FUSE_RD_LOCK_FUSE_OFFSET 0x158 +#define GC_PMU_FUSE_TIMING_WRITE_LSB 0x0 +#define GC_PMU_FUSE_TIMING_WRITE_MASK 0xffff +#define GC_PMU_FUSE_TIMING_WRITE_SIZE 0x10 +#define GC_PMU_FUSE_TIMING_WRITE_DEFAULT 0x7d +#define GC_PMU_FUSE_TIMING_WRITE_OFFSET 0x170 +#define GC_PMU_FUSE_TIMING_READ_LSB 0x10 +#define GC_PMU_FUSE_TIMING_READ_MASK 0xffff0000 +#define GC_PMU_FUSE_TIMING_READ_SIZE 0x10 +#define GC_PMU_FUSE_TIMING_READ_DEFAULT 0x8 +#define GC_PMU_FUSE_TIMING_READ_OFFSET 0x170 +#define GC_PMU_FUSE_OVRD_CSB_LSB 0x0 +#define GC_PMU_FUSE_OVRD_CSB_MASK 0x1 +#define GC_PMU_FUSE_OVRD_CSB_SIZE 0x1 +#define GC_PMU_FUSE_OVRD_CSB_DEFAULT 0x1 +#define GC_PMU_FUSE_OVRD_CSB_OFFSET 0x178 +#define GC_PMU_FUSE_OVRD_PGM_LSB 0x1 +#define GC_PMU_FUSE_OVRD_PGM_MASK 0x2 +#define GC_PMU_FUSE_OVRD_PGM_SIZE 0x1 +#define GC_PMU_FUSE_OVRD_PGM_DEFAULT 0x0 +#define GC_PMU_FUSE_OVRD_PGM_OFFSET 0x178 +#define GC_PMU_FUSE_OVRD_SCK_LSB 0x2 +#define GC_PMU_FUSE_OVRD_SCK_MASK 0x4 +#define GC_PMU_FUSE_OVRD_SCK_SIZE 0x1 +#define GC_PMU_FUSE_OVRD_SCK_DEFAULT 0x0 +#define GC_PMU_FUSE_OVRD_SCK_OFFSET 0x178 +#define GC_PMU_FUSE_DBG_STATE_LSB 0x0 +#define GC_PMU_FUSE_DBG_STATE_MASK 0xf +#define GC_PMU_FUSE_DBG_STATE_SIZE 0x4 +#define GC_PMU_FUSE_DBG_STATE_DEFAULT 0x0 +#define GC_PMU_FUSE_DBG_STATE_OFFSET 0x17c +#define GC_PMU_FUSE_DBG_IDLE_LSB 0x4 +#define GC_PMU_FUSE_DBG_IDLE_MASK 0x10 +#define GC_PMU_FUSE_DBG_IDLE_SIZE 0x1 +#define GC_PMU_FUSE_DBG_IDLE_DEFAULT 0x0 +#define GC_PMU_FUSE_DBG_IDLE_OFFSET 0x17c +#define GC_PMU_ICTRL_SLEEP_LSB 0x0 +#define GC_PMU_ICTRL_SLEEP_MASK 0x1 +#define GC_PMU_ICTRL_SLEEP_SIZE 0x1 +#define GC_PMU_ICTRL_SLEEP_DEFAULT 0x0 +#define GC_PMU_ICTRL_SLEEP_OFFSET 0x180 +#define GC_PMU_ISTAT_SLEEP_LSB 0x0 +#define GC_PMU_ISTAT_SLEEP_MASK 0x1 +#define GC_PMU_ISTAT_SLEEP_SIZE 0x1 +#define GC_PMU_ISTAT_SLEEP_DEFAULT 0x0 +#define GC_PMU_ISTAT_SLEEP_OFFSET 0x184 +#define GC_PMU_ISTAT_HIBER_LSB 0x1 +#define GC_PMU_ISTAT_HIBER_MASK 0x2 +#define GC_PMU_ISTAT_HIBER_SIZE 0x1 +#define GC_PMU_ISTAT_HIBER_DEFAULT 0x0 +#define GC_PMU_ISTAT_HIBER_OFFSET 0x184 +#define GC_PMU_ISTAT_PWRDN_LSB 0x2 +#define GC_PMU_ISTAT_PWRDN_MASK 0x4 +#define GC_PMU_ISTAT_PWRDN_SIZE 0x1 +#define GC_PMU_ISTAT_PWRDN_DEFAULT 0x0 +#define GC_PMU_ISTAT_PWRDN_OFFSET 0x184 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_LSB 0x0 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_MASK 0x1 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_SIZE 0x1 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_DEFAULT 0x1 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_OFFSET 0x1008 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_LSB 0x1 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_MASK 0x2 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_SIZE 0x1 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_DEFAULT 0x1 +#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_OFFSET 0x1008 +#define GC_PMU_HW_CONTROLS_LNA_PDB_LSB 0x0 +#define GC_PMU_HW_CONTROLS_LNA_PDB_MASK 0x1 +#define GC_PMU_HW_CONTROLS_LNA_PDB_SIZE 0x1 +#define GC_PMU_HW_CONTROLS_LNA_PDB_DEFAULT 0x0 +#define GC_PMU_HW_CONTROLS_LNA_PDB_OFFSET 0x101c +#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_LSB 0x1 +#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_MASK 0x2 +#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_SIZE 0x1 +#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_DEFAULT 0x0 +#define GC_PMU_HW_CONTROLS_LNA_PKDET_PDB_OFFSET 0x101c +#define GC_PMU_HW_CONTROLS_AUXADC_PDB_LSB 0x2 +#define GC_PMU_HW_CONTROLS_AUXADC_PDB_MASK 0x4 +#define GC_PMU_HW_CONTROLS_AUXADC_PDB_SIZE 0x1 +#define GC_PMU_HW_CONTROLS_AUXADC_PDB_DEFAULT 0x0 +#define GC_PMU_HW_CONTROLS_AUXADC_PDB_OFFSET 0x101c +#define GC_PMU_HW_CONTROLS_PA_PDB_LSB 0x3 +#define GC_PMU_HW_CONTROLS_PA_PDB_MASK 0x8 +#define GC_PMU_HW_CONTROLS_PA_PDB_SIZE 0x1 +#define GC_PMU_HW_CONTROLS_PA_PDB_DEFAULT 0x0 +#define GC_PMU_HW_CONTROLS_PA_PDB_OFFSET 0x101c +#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_LSB 0x4 +#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_MASK 0x10 +#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_SIZE 0x1 +#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_DEFAULT 0x0 +#define GC_PMU_HW_CONTROLS_PA_PDB_EXT_OFFSET 0x101c +#define GC_PMU_ANTEST_TRNG_VLDO_EN_LSB 0x0 +#define GC_PMU_ANTEST_TRNG_VLDO_EN_MASK 0x1 +#define GC_PMU_ANTEST_TRNG_VLDO_EN_SIZE 0x1 +#define GC_PMU_ANTEST_TRNG_VLDO_EN_DEFAULT 0x0 +#define GC_PMU_ANTEST_TRNG_VLDO_EN_OFFSET 0x1024 +#define GC_PMU_ANTEST_TEMP_DIFF_EN_LSB 0x0 +#define GC_PMU_ANTEST_TEMP_DIFF_EN_MASK 0x1 +#define GC_PMU_ANTEST_TEMP_DIFF_EN_SIZE 0x1 +#define GC_PMU_ANTEST_TEMP_DIFF_EN_DEFAULT 0x0 +#define GC_PMU_ANTEST_TEMP_DIFF_EN_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_CM_EN_LSB 0x1 +#define GC_PMU_ANTEST_TEMP_CM_EN_MASK 0x2 +#define GC_PMU_ANTEST_TEMP_CM_EN_SIZE 0x1 +#define GC_PMU_ANTEST_TEMP_CM_EN_DEFAULT 0x0 +#define GC_PMU_ANTEST_TEMP_CM_EN_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_REF_EN_LSB 0x2 +#define GC_PMU_ANTEST_TEMP_REF_EN_MASK 0x4 +#define GC_PMU_ANTEST_TEMP_REF_EN_SIZE 0x1 +#define GC_PMU_ANTEST_TEMP_REF_EN_DEFAULT 0x0 +#define GC_PMU_ANTEST_TEMP_REF_EN_OFFSET 0x1028 +#define GC_PMU_ANTEST_TEMP_VPTAT_EN_LSB 0x3 +#define GC_PMU_ANTEST_TEMP_VPTAT_EN_MASK 0x8 +#define GC_PMU_ANTEST_TEMP_VPTAT_EN_SIZE 0x1 +#define GC_PMU_ANTEST_TEMP_VPTAT_EN_DEFAULT 0x0 +#define GC_PMU_ANTEST_TEMP_VPTAT_EN_OFFSET 0x1028 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_LSB 0x0 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_MASK 0xf +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_SIZE 0x4 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_DEFAULT 0x0 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_OFFSET 0x2000 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_SUB_CTRL_LSB 0x4 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_SUB_CTRL_MASK 0xf0 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_SUB_CTRL_SIZE 0x4 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_SUB_CTRL_DEFAULT 0x0 +#define GC_PMU_TESTBUS_CTRL_TEST_MUX_SUB_CTRL_OFFSET 0x2000 +#define GC_PMU_CHIP_ID_JTAG_STANDARD_LSB 0x0 +#define GC_PMU_CHIP_ID_JTAG_STANDARD_MASK 0x1 +#define GC_PMU_CHIP_ID_JTAG_STANDARD_SIZE 0x1 +#define GC_PMU_CHIP_ID_JTAG_STANDARD_DEFAULT 0x1 +#define GC_PMU_CHIP_ID_JTAG_STANDARD_OFFSET 0x1fff8 +#define GC_PMU_CHIP_ID_MFG_ID_LSB 0x1 +#define GC_PMU_CHIP_ID_MFG_ID_MASK 0xffe +#define GC_PMU_CHIP_ID_MFG_ID_SIZE 0xb +#define GC_PMU_CHIP_ID_MFG_ID_DEFAULT 0x4a6 +#define GC_PMU_CHIP_ID_MFG_ID_OFFSET 0x1fff8 +#define GC_PMU_CHIP_ID_PART_NUM_LSB 0xc +#define GC_PMU_CHIP_ID_PART_NUM_MASK 0xffff000 +#define GC_PMU_CHIP_ID_PART_NUM_SIZE 0x10 +#define GC_PMU_CHIP_ID_PART_NUM_DEFAULT 0x4856 +#define GC_PMU_CHIP_ID_PART_NUM_OFFSET 0x1fff8 +#define GC_PMU_CHIP_ID_REVISION_LSB 0x1c +#define GC_PMU_CHIP_ID_REVISION_MASK 0xf0000000 +#define GC_PMU_CHIP_ID_REVISION_SIZE 0x4 +#define GC_PMU_CHIP_ID_REVISION_DEFAULT 0x1 +#define GC_PMU_CHIP_ID_REVISION_OFFSET 0x1fff8 +#define GC_PMU_VERSION_CHANGE_LSB 0x0 +#define GC_PMU_VERSION_CHANGE_MASK 0xffffff +#define GC_PMU_VERSION_CHANGE_SIZE 0x18 +#define GC_PMU_VERSION_CHANGE_DEFAULT 0xc244 +#define GC_PMU_VERSION_CHANGE_OFFSET 0x1fffc +#define GC_PMU_VERSION_REVISION_LSB 0x18 +#define GC_PMU_VERSION_REVISION_MASK 0xff000000 +#define GC_PMU_VERSION_REVISION_SIZE 0x8 +#define GC_PMU_VERSION_REVISION_DEFAULT 0x11 +#define GC_PMU_VERSION_REVISION_OFFSET 0x1fffc +#define GC_RBOX_VERSION_CHANGE_LSB 0x0 +#define GC_RBOX_VERSION_CHANGE_MASK 0xffffff +#define GC_RBOX_VERSION_CHANGE_SIZE 0x18 +#define GC_RBOX_VERSION_CHANGE_DEFAULT 0xc16f +#define GC_RBOX_VERSION_CHANGE_OFFSET 0x18 +#define GC_RBOX_VERSION_REVISION_LSB 0x18 +#define GC_RBOX_VERSION_REVISION_MASK 0xff000000 +#define GC_RBOX_VERSION_REVISION_SIZE 0x8 +#define GC_RBOX_VERSION_REVISION_DEFAULT 0x6 +#define GC_RBOX_VERSION_REVISION_OFFSET 0x18 +#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_LSB 0x0 +#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_MASK 0xf +#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_SIZE 0x4 +#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_DEFAULT 0x1 +#define GC_RTC_CTRL_X_RTC_MUX_CTRL_3P3_OFFSET 0x0 +#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_LSB 0x4 +#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_MASK 0xff0 +#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_SIZE 0x8 +#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_DEFAULT 0xf0 +#define GC_RTC_CTRL_X_RTC_RC_CTRL_3P3_OFFSET 0x0 +#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_LSB 0xc +#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_MASK 0x1000 +#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_SIZE 0x1 +#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_DEFAULT 0x0 +#define GC_RTC_CTRL_X_RTC_XTL_INSTALLED_3P3_OFFSET 0x0 +#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_LSB 0xd +#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_MASK 0x6000 +#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_SIZE 0x2 +#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_DEFAULT 0x1 +#define GC_RTC_CTRL_X_RTC_XTL_ITRIM_3P3_OFFSET 0x0 +#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_LSB 0xf +#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_MASK 0x78000 +#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_SIZE 0x4 +#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_DEFAULT 0x4 +#define GC_RTC_CTRL_X_RTC_XTL_CTRIM_3P3_OFFSET 0x0 +#define GC_RTC_SETHOLD_EN_LSB 0x0 +#define GC_RTC_SETHOLD_EN_MASK 0x1 +#define GC_RTC_SETHOLD_EN_SIZE 0x1 +#define GC_RTC_SETHOLD_EN_DEFAULT 0x0 +#define GC_RTC_SETHOLD_EN_OFFSET 0x8 +#define GC_RTC_CLRHOLD_EN_LSB 0x0 +#define GC_RTC_CLRHOLD_EN_MASK 0x1 +#define GC_RTC_CLRHOLD_EN_SIZE 0x1 +#define GC_RTC_CLRHOLD_EN_DEFAULT 0x0 +#define GC_RTC_CLRHOLD_EN_OFFSET 0xc +#define GC_SHA_CFG_EN_EN_BIG_ENDIAN_LSB 0x0 +#define GC_SHA_CFG_EN_EN_BIG_ENDIAN_MASK 0x1 +#define GC_SHA_CFG_EN_EN_BIG_ENDIAN_SIZE 0x1 +#define GC_SHA_CFG_EN_EN_BIG_ENDIAN_DEFAULT 0x1 +#define GC_SHA_CFG_EN_EN_BIG_ENDIAN_OFFSET 0x8 +#define GC_SHA_CFG_EN_EN_SHA1_LSB 0x1 +#define GC_SHA_CFG_EN_EN_SHA1_MASK 0x2 +#define GC_SHA_CFG_EN_EN_SHA1_SIZE 0x1 +#define GC_SHA_CFG_EN_EN_SHA1_DEFAULT 0x0 +#define GC_SHA_CFG_EN_EN_SHA1_OFFSET 0x8 +#define GC_SHA_CFG_EN_EN_STEP_LSB 0x2 +#define GC_SHA_CFG_EN_EN_STEP_MASK 0x4 +#define GC_SHA_CFG_EN_EN_STEP_SIZE 0x1 +#define GC_SHA_CFG_EN_EN_STEP_DEFAULT 0x0 +#define GC_SHA_CFG_EN_EN_STEP_OFFSET 0x8 +#define GC_SHA_CFG_EN_EN_BUS_ERROR_LSB 0x3 +#define GC_SHA_CFG_EN_EN_BUS_ERROR_MASK 0x8 +#define GC_SHA_CFG_EN_EN_BUS_ERROR_SIZE 0x1 +#define GC_SHA_CFG_EN_EN_BUS_ERROR_DEFAULT 0x0 +#define GC_SHA_CFG_EN_EN_BUS_ERROR_OFFSET 0x8 +#define GC_SHA_CFG_EN_RESERVED0_LSB 0x4 +#define GC_SHA_CFG_EN_RESERVED0_MASK 0xfff0 +#define GC_SHA_CFG_EN_RESERVED0_SIZE 0xc +#define GC_SHA_CFG_EN_RESERVED0_DEFAULT 0x0 +#define GC_SHA_CFG_EN_RESERVED0_OFFSET 0x8 +#define GC_SHA_CFG_EN_INT_EN_SHA_DONE_LSB 0x10 +#define GC_SHA_CFG_EN_INT_EN_SHA_DONE_MASK 0x10000 +#define GC_SHA_CFG_EN_INT_EN_SHA_DONE_SIZE 0x1 +#define GC_SHA_CFG_EN_INT_EN_SHA_DONE_DEFAULT 0x0 +#define GC_SHA_CFG_EN_INT_EN_SHA_DONE_OFFSET 0x8 +#define GC_SHA_CFG_EN_INT_MASK_SHA_DONE_LSB 0x11 +#define GC_SHA_CFG_EN_INT_MASK_SHA_DONE_MASK 0x20000 +#define GC_SHA_CFG_EN_INT_MASK_SHA_DONE_SIZE 0x1 +#define GC_SHA_CFG_EN_INT_MASK_SHA_DONE_DEFAULT 0x0 +#define GC_SHA_CFG_EN_INT_MASK_SHA_DONE_OFFSET 0x8 +#define GC_SHA_CFG_EN_RESERVED1_LSB 0x12 +#define GC_SHA_CFG_EN_RESERVED1_MASK 0xfffc0000 +#define GC_SHA_CFG_EN_RESERVED1_SIZE 0xe +#define GC_SHA_CFG_EN_RESERVED1_DEFAULT 0x0 +#define GC_SHA_CFG_EN_RESERVED1_OFFSET 0x8 +#define GC_SHA_TRIG_TRIG_GO_LSB 0x0 +#define GC_SHA_TRIG_TRIG_GO_MASK 0x1 +#define GC_SHA_TRIG_TRIG_GO_SIZE 0x1 +#define GC_SHA_TRIG_TRIG_GO_DEFAULT 0x0 +#define GC_SHA_TRIG_TRIG_GO_OFFSET 0xc +#define GC_SHA_TRIG_TRIG_RESETN_LSB 0x1 +#define GC_SHA_TRIG_TRIG_RESETN_MASK 0x2 +#define GC_SHA_TRIG_TRIG_RESETN_SIZE 0x1 +#define GC_SHA_TRIG_TRIG_RESETN_DEFAULT 0x1 +#define GC_SHA_TRIG_TRIG_RESETN_OFFSET 0xc +#define GC_SHA_TRIG_TRIG_STEP_LSB 0x2 +#define GC_SHA_TRIG_TRIG_STEP_MASK 0x4 +#define GC_SHA_TRIG_TRIG_STEP_SIZE 0x1 +#define GC_SHA_TRIG_TRIG_STEP_DEFAULT 0x0 +#define GC_SHA_TRIG_TRIG_STEP_OFFSET 0xc +#define GC_SPI_CTRL_CPOL_LSB 0x0 +#define GC_SPI_CTRL_CPOL_MASK 0x1 +#define GC_SPI_CTRL_CPOL_SIZE 0x1 +#define GC_SPI_CTRL_CPOL_DEFAULT 0x0 +#define GC_SPI_CTRL_CPOL_OFFSET 0x0 +#define GC_SPI_CTRL_CPHA_LSB 0x1 +#define GC_SPI_CTRL_CPHA_MASK 0x2 +#define GC_SPI_CTRL_CPHA_SIZE 0x1 +#define GC_SPI_CTRL_CPHA_DEFAULT 0x0 +#define GC_SPI_CTRL_CPHA_OFFSET 0x0 +#define GC_SPI_CTRL_CSBSU_LSB 0x2 +#define GC_SPI_CTRL_CSBSU_MASK 0x3c +#define GC_SPI_CTRL_CSBSU_SIZE 0x4 +#define GC_SPI_CTRL_CSBSU_DEFAULT 0x0 +#define GC_SPI_CTRL_CSBSU_OFFSET 0x0 +#define GC_SPI_CTRL_CSBHLD_LSB 0x6 +#define GC_SPI_CTRL_CSBHLD_MASK 0x3c0 +#define GC_SPI_CTRL_CSBHLD_SIZE 0x4 +#define GC_SPI_CTRL_CSBHLD_DEFAULT 0x0 +#define GC_SPI_CTRL_CSBHLD_OFFSET 0x0 +#define GC_SPI_CTRL_IDIV_LSB 0xa +#define GC_SPI_CTRL_IDIV_MASK 0x3ffc00 +#define GC_SPI_CTRL_IDIV_SIZE 0xc +#define GC_SPI_CTRL_IDIV_DEFAULT 0x2 +#define GC_SPI_CTRL_IDIV_OFFSET 0x0 +#define GC_SPI_CTRL_CSBPOL_LSB 0x16 +#define GC_SPI_CTRL_CSBPOL_MASK 0x400000 +#define GC_SPI_CTRL_CSBPOL_SIZE 0x1 +#define GC_SPI_CTRL_CSBPOL_DEFAULT 0x0 +#define GC_SPI_CTRL_CSBPOL_OFFSET 0x0 +#define GC_SPI_CTRL_TXBITOR_LSB 0x17 +#define GC_SPI_CTRL_TXBITOR_MASK 0x800000 +#define GC_SPI_CTRL_TXBITOR_SIZE 0x1 +#define GC_SPI_CTRL_TXBITOR_DEFAULT 0x1 +#define GC_SPI_CTRL_TXBITOR_OFFSET 0x0 +#define GC_SPI_CTRL_TXBYTOR_LSB 0x18 +#define GC_SPI_CTRL_TXBYTOR_MASK 0x1000000 +#define GC_SPI_CTRL_TXBYTOR_SIZE 0x1 +#define GC_SPI_CTRL_TXBYTOR_DEFAULT 0x0 +#define GC_SPI_CTRL_TXBYTOR_OFFSET 0x0 +#define GC_SPI_CTRL_RXBITOR_LSB 0x19 +#define GC_SPI_CTRL_RXBITOR_MASK 0x2000000 +#define GC_SPI_CTRL_RXBITOR_SIZE 0x1 +#define GC_SPI_CTRL_RXBITOR_DEFAULT 0x1 +#define GC_SPI_CTRL_RXBITOR_OFFSET 0x0 +#define GC_SPI_CTRL_RXBYTOR_LSB 0x1a +#define GC_SPI_CTRL_RXBYTOR_MASK 0x4000000 +#define GC_SPI_CTRL_RXBYTOR_SIZE 0x1 +#define GC_SPI_CTRL_RXBYTOR_DEFAULT 0x0 +#define GC_SPI_CTRL_RXBYTOR_OFFSET 0x0 +#define GC_SPI_XACT_START_LSB 0x0 +#define GC_SPI_XACT_START_MASK 0x1 +#define GC_SPI_XACT_START_SIZE 0x1 +#define GC_SPI_XACT_START_DEFAULT 0x0 +#define GC_SPI_XACT_START_OFFSET 0x4 +#define GC_SPI_XACT_BCNT_LSB 0x1 +#define GC_SPI_XACT_BCNT_MASK 0xe +#define GC_SPI_XACT_BCNT_SIZE 0x3 +#define GC_SPI_XACT_BCNT_DEFAULT 0x7 +#define GC_SPI_XACT_BCNT_OFFSET 0x4 +#define GC_SPI_XACT_SIZE_LSB 0x4 +#define GC_SPI_XACT_SIZE_MASK 0x7f0 +#define GC_SPI_XACT_SIZE_SIZE 0x7 +#define GC_SPI_XACT_SIZE_DEFAULT 0x0 +#define GC_SPI_XACT_SIZE_OFFSET 0x4 +#define GC_SPI_XACT_RDY_POLL_LSB 0xb +#define GC_SPI_XACT_RDY_POLL_MASK 0x800 +#define GC_SPI_XACT_RDY_POLL_SIZE 0x1 +#define GC_SPI_XACT_RDY_POLL_DEFAULT 0x0 +#define GC_SPI_XACT_RDY_POLL_OFFSET 0x4 +#define GC_SPI_XACT_RDY_POLL_DLY_LSB 0xc +#define GC_SPI_XACT_RDY_POLL_DLY_MASK 0x1f000 +#define GC_SPI_XACT_RDY_POLL_DLY_SIZE 0x5 +#define GC_SPI_XACT_RDY_POLL_DLY_DEFAULT 0x0 +#define GC_SPI_XACT_RDY_POLL_DLY_OFFSET 0x4 +#define GC_SPI_ICTRL_TXDONE_LSB 0x0 +#define GC_SPI_ICTRL_TXDONE_MASK 0x1 +#define GC_SPI_ICTRL_TXDONE_SIZE 0x1 +#define GC_SPI_ICTRL_TXDONE_DEFAULT 0x0 +#define GC_SPI_ICTRL_TXDONE_OFFSET 0x8 +#define GC_SPI_ISTATE_TXDONE_LSB 0x0 +#define GC_SPI_ISTATE_TXDONE_MASK 0x1 +#define GC_SPI_ISTATE_TXDONE_SIZE 0x1 +#define GC_SPI_ISTATE_TXDONE_DEFAULT 0x0 +#define GC_SPI_ISTATE_TXDONE_OFFSET 0xc +#define GC_SPI_ISTATE_CLR_TXDONE_LSB 0x0 +#define GC_SPI_ISTATE_CLR_TXDONE_MASK 0x1 +#define GC_SPI_ISTATE_CLR_TXDONE_SIZE 0x1 +#define GC_SPI_ISTATE_CLR_TXDONE_DEFAULT 0x0 +#define GC_SPI_ISTATE_CLR_TXDONE_OFFSET 0x10 +#define GC_SPI_OVRD_SCKEN_LSB 0x0 +#define GC_SPI_OVRD_SCKEN_MASK 0x1 +#define GC_SPI_OVRD_SCKEN_SIZE 0x1 +#define GC_SPI_OVRD_SCKEN_DEFAULT 0x0 +#define GC_SPI_OVRD_SCKEN_OFFSET 0x14 +#define GC_SPI_OVRD_SCKVAL_LSB 0x1 +#define GC_SPI_OVRD_SCKVAL_MASK 0x2 +#define GC_SPI_OVRD_SCKVAL_SIZE 0x1 +#define GC_SPI_OVRD_SCKVAL_DEFAULT 0x0 +#define GC_SPI_OVRD_SCKVAL_OFFSET 0x14 +#define GC_SPI_OVRD_CSBEN_LSB 0x2 +#define GC_SPI_OVRD_CSBEN_MASK 0x4 +#define GC_SPI_OVRD_CSBEN_SIZE 0x1 +#define GC_SPI_OVRD_CSBEN_DEFAULT 0x0 +#define GC_SPI_OVRD_CSBEN_OFFSET 0x14 +#define GC_SPI_OVRD_CSBVAL_LSB 0x3 +#define GC_SPI_OVRD_CSBVAL_MASK 0x8 +#define GC_SPI_OVRD_CSBVAL_SIZE 0x1 +#define GC_SPI_OVRD_CSBVAL_DEFAULT 0x1 +#define GC_SPI_OVRD_CSBVAL_OFFSET 0x14 +#define GC_SPI_OVRD_MOSIEN_LSB 0x4 +#define GC_SPI_OVRD_MOSIEN_MASK 0x10 +#define GC_SPI_OVRD_MOSIEN_SIZE 0x1 +#define GC_SPI_OVRD_MOSIEN_DEFAULT 0x0 +#define GC_SPI_OVRD_MOSIEN_OFFSET 0x14 +#define GC_SPI_OVRD_MOSIVAL_LSB 0x5 +#define GC_SPI_OVRD_MOSIVAL_MASK 0x20 +#define GC_SPI_OVRD_MOSIVAL_SIZE 0x1 +#define GC_SPI_OVRD_MOSIVAL_DEFAULT 0x0 +#define GC_SPI_OVRD_MOSIVAL_OFFSET 0x14 +#define GC_SPI_VAL_MISO_LSB 0x0 +#define GC_SPI_VAL_MISO_MASK 0x1 +#define GC_SPI_VAL_MISO_SIZE 0x1 +#define GC_SPI_VAL_MISO_DEFAULT 0x0 +#define GC_SPI_VAL_MISO_OFFSET 0x18 +#define GC_SPI_VAL_MOSI_LSB 0x1 +#define GC_SPI_VAL_MOSI_MASK 0x2 +#define GC_SPI_VAL_MOSI_SIZE 0x1 +#define GC_SPI_VAL_MOSI_DEFAULT 0x0 +#define GC_SPI_VAL_MOSI_OFFSET 0x18 +#define GC_SPI_VAL_CSB_LSB 0x2 +#define GC_SPI_VAL_CSB_MASK 0x4 +#define GC_SPI_VAL_CSB_SIZE 0x1 +#define GC_SPI_VAL_CSB_DEFAULT 0x0 +#define GC_SPI_VAL_CSB_OFFSET 0x18 +#define GC_SPI_VAL_SCK_LSB 0x3 +#define GC_SPI_VAL_SCK_MASK 0x8 +#define GC_SPI_VAL_SCK_SIZE 0x1 +#define GC_SPI_VAL_SCK_DEFAULT 0x0 +#define GC_SPI_VAL_SCK_OFFSET 0x18 +#define GC_SPI_ITOP_TXDONE_LSB 0x0 +#define GC_SPI_ITOP_TXDONE_MASK 0x1 +#define GC_SPI_ITOP_TXDONE_SIZE 0x1 +#define GC_SPI_ITOP_TXDONE_DEFAULT 0x0 +#define GC_SPI_ITOP_TXDONE_OFFSET 0xf04 +#define GC_SPS_CTRL_MODE_LSB 0x0 +#define GC_SPS_CTRL_MODE_MASK 0x3 +#define GC_SPS_CTRL_MODE_SIZE 0x2 +#define GC_SPS_CTRL_MODE_DEFAULT 0x1 +#define GC_SPS_CTRL_MODE_OFFSET 0x0 +#define GC_SPS_CTRL_CPHA_LSB 0x2 +#define GC_SPS_CTRL_CPHA_MASK 0x4 +#define GC_SPS_CTRL_CPHA_SIZE 0x1 +#define GC_SPS_CTRL_CPHA_DEFAULT 0x0 +#define GC_SPS_CTRL_CPHA_OFFSET 0x0 +#define GC_SPS_CTRL_CPOL_LSB 0x3 +#define GC_SPS_CTRL_CPOL_MASK 0x8 +#define GC_SPS_CTRL_CPOL_SIZE 0x1 +#define GC_SPS_CTRL_CPOL_DEFAULT 0x0 +#define GC_SPS_CTRL_CPOL_OFFSET 0x0 +#define GC_SPS_CTRL_IDLE_LVL_LSB 0x4 +#define GC_SPS_CTRL_IDLE_LVL_MASK 0x10 +#define GC_SPS_CTRL_IDLE_LVL_SIZE 0x1 +#define GC_SPS_CTRL_IDLE_LVL_DEFAULT 0x0 +#define GC_SPS_CTRL_IDLE_LVL_OFFSET 0x0 +#define GC_SPS_CTRL_TXBITOR_LSB 0x5 +#define GC_SPS_CTRL_TXBITOR_MASK 0x20 +#define GC_SPS_CTRL_TXBITOR_SIZE 0x1 +#define GC_SPS_CTRL_TXBITOR_DEFAULT 0x0 +#define GC_SPS_CTRL_TXBITOR_OFFSET 0x0 +#define GC_SPS_CTRL_RXBITOR_LSB 0x6 +#define GC_SPS_CTRL_RXBITOR_MASK 0x40 +#define GC_SPS_CTRL_RXBITOR_SIZE 0x1 +#define GC_SPS_CTRL_RXBITOR_DEFAULT 0x0 +#define GC_SPS_CTRL_RXBITOR_OFFSET 0x0 +#define GC_SPS_CTRL_ROM_ADDR_SIZE_LSB 0x7 +#define GC_SPS_CTRL_ROM_ADDR_SIZE_MASK 0x180 +#define GC_SPS_CTRL_ROM_ADDR_SIZE_SIZE 0x2 +#define GC_SPS_CTRL_ROM_ADDR_SIZE_DEFAULT 0x3 +#define GC_SPS_CTRL_ROM_ADDR_SIZE_OFFSET 0x0 +#define GC_SPS_STATUS01_STATUS0L_LSB 0x0 +#define GC_SPS_STATUS01_STATUS0L_MASK 0xff +#define GC_SPS_STATUS01_STATUS0L_SIZE 0x8 +#define GC_SPS_STATUS01_STATUS0L_DEFAULT 0x0 +#define GC_SPS_STATUS01_STATUS0L_OFFSET 0x8 +#define GC_SPS_STATUS01_STATUS0H_LSB 0x8 +#define GC_SPS_STATUS01_STATUS0H_MASK 0xff00 +#define GC_SPS_STATUS01_STATUS0H_SIZE 0x8 +#define GC_SPS_STATUS01_STATUS0H_DEFAULT 0x0 +#define GC_SPS_STATUS01_STATUS0H_OFFSET 0x8 +#define GC_SPS_STATUS01_STATUS1_LSB 0x10 +#define GC_SPS_STATUS01_STATUS1_MASK 0xffff0000 +#define GC_SPS_STATUS01_STATUS1_SIZE 0x10 +#define GC_SPS_STATUS01_STATUS1_DEFAULT 0x0 +#define GC_SPS_STATUS01_STATUS1_OFFSET 0x8 +#define GC_SPS_STATUS23_STATUS2_LSB 0x0 +#define GC_SPS_STATUS23_STATUS2_MASK 0xffff +#define GC_SPS_STATUS23_STATUS2_SIZE 0x10 +#define GC_SPS_STATUS23_STATUS2_DEFAULT 0x0 +#define GC_SPS_STATUS23_STATUS2_OFFSET 0xc +#define GC_SPS_STATUS23_STATUS3_LSB 0x10 +#define GC_SPS_STATUS23_STATUS3_MASK 0xffff0000 +#define GC_SPS_STATUS23_STATUS3_SIZE 0x10 +#define GC_SPS_STATUS23_STATUS3_DEFAULT 0x0 +#define GC_SPS_STATUS23_STATUS3_OFFSET 0xc +#define GC_SPS_STATUS45_STATUS4_LSB 0x0 +#define GC_SPS_STATUS45_STATUS4_MASK 0xffff +#define GC_SPS_STATUS45_STATUS4_SIZE 0x10 +#define GC_SPS_STATUS45_STATUS4_DEFAULT 0x0 +#define GC_SPS_STATUS45_STATUS4_OFFSET 0x10 +#define GC_SPS_STATUS45_STATUS5_LSB 0x10 +#define GC_SPS_STATUS45_STATUS5_MASK 0xffff0000 +#define GC_SPS_STATUS45_STATUS5_SIZE 0x10 +#define GC_SPS_STATUS45_STATUS5_DEFAULT 0x0 +#define GC_SPS_STATUS45_STATUS5_OFFSET 0x10 +#define GC_SPS_STATUS67_STATUS6_LSB 0x0 +#define GC_SPS_STATUS67_STATUS6_MASK 0xffff +#define GC_SPS_STATUS67_STATUS6_SIZE 0x10 +#define GC_SPS_STATUS67_STATUS6_DEFAULT 0x0 +#define GC_SPS_STATUS67_STATUS6_OFFSET 0x14 +#define GC_SPS_STATUS67_STATUS7_LSB 0x10 +#define GC_SPS_STATUS67_STATUS7_MASK 0xffff0000 +#define GC_SPS_STATUS67_STATUS7_SIZE 0x10 +#define GC_SPS_STATUS67_STATUS7_DEFAULT 0x0 +#define GC_SPS_STATUS67_STATUS7_OFFSET 0x14 +#define GC_SPS_CTRL01_CTRL0_LSB 0x0 +#define GC_SPS_CTRL01_CTRL0_MASK 0xffff +#define GC_SPS_CTRL01_CTRL0_SIZE 0x10 +#define GC_SPS_CTRL01_CTRL0_DEFAULT 0x0 +#define GC_SPS_CTRL01_CTRL0_OFFSET 0x18 +#define GC_SPS_CTRL01_CTRL1_LSB 0x10 +#define GC_SPS_CTRL01_CTRL1_MASK 0xffff0000 +#define GC_SPS_CTRL01_CTRL1_SIZE 0x10 +#define GC_SPS_CTRL01_CTRL1_DEFAULT 0x0 +#define GC_SPS_CTRL01_CTRL1_OFFSET 0x18 +#define GC_SPS_CTRL23_CTRL2_LSB 0x0 +#define GC_SPS_CTRL23_CTRL2_MASK 0xffff +#define GC_SPS_CTRL23_CTRL2_SIZE 0x10 +#define GC_SPS_CTRL23_CTRL2_DEFAULT 0x0 +#define GC_SPS_CTRL23_CTRL2_OFFSET 0x1c +#define GC_SPS_CTRL23_CTRL3_LSB 0x10 +#define GC_SPS_CTRL23_CTRL3_MASK 0xffff0000 +#define GC_SPS_CTRL23_CTRL3_SIZE 0x10 +#define GC_SPS_CTRL23_CTRL3_DEFAULT 0x0 +#define GC_SPS_CTRL23_CTRL3_OFFSET 0x1c +#define GC_SPS_CTRL45_CTRL4_LSB 0x0 +#define GC_SPS_CTRL45_CTRL4_MASK 0xffff +#define GC_SPS_CTRL45_CTRL4_SIZE 0x10 +#define GC_SPS_CTRL45_CTRL4_DEFAULT 0x0 +#define GC_SPS_CTRL45_CTRL4_OFFSET 0x20 +#define GC_SPS_CTRL45_CTRL5_LSB 0x10 +#define GC_SPS_CTRL45_CTRL5_MASK 0xffff0000 +#define GC_SPS_CTRL45_CTRL5_SIZE 0x10 +#define GC_SPS_CTRL45_CTRL5_DEFAULT 0x0 +#define GC_SPS_CTRL45_CTRL5_OFFSET 0x20 +#define GC_SPS_CTRL67_CTRL6_LSB 0x0 +#define GC_SPS_CTRL67_CTRL6_MASK 0xffff +#define GC_SPS_CTRL67_CTRL6_SIZE 0x10 +#define GC_SPS_CTRL67_CTRL6_DEFAULT 0x0 +#define GC_SPS_CTRL67_CTRL6_OFFSET 0x24 +#define GC_SPS_CTRL67_CTRL7_LSB 0x10 +#define GC_SPS_CTRL67_CTRL7_MASK 0xffff0000 +#define GC_SPS_CTRL67_CTRL7_SIZE 0x10 +#define GC_SPS_CTRL67_CTRL7_DEFAULT 0x0 +#define GC_SPS_CTRL67_CTRL7_OFFSET 0x24 +#define GC_SPS_FIFO_CTRL_TXFIFO_RST_LSB 0x0 +#define GC_SPS_FIFO_CTRL_TXFIFO_RST_MASK 0x1 +#define GC_SPS_FIFO_CTRL_TXFIFO_RST_SIZE 0x1 +#define GC_SPS_FIFO_CTRL_TXFIFO_RST_DEFAULT 0x0 +#define GC_SPS_FIFO_CTRL_TXFIFO_RST_OFFSET 0x28 +#define GC_SPS_FIFO_CTRL_TXFIFO_EN_LSB 0x1 +#define GC_SPS_FIFO_CTRL_TXFIFO_EN_MASK 0x2 +#define GC_SPS_FIFO_CTRL_TXFIFO_EN_SIZE 0x1 +#define GC_SPS_FIFO_CTRL_TXFIFO_EN_DEFAULT 0x0 +#define GC_SPS_FIFO_CTRL_TXFIFO_EN_OFFSET 0x28 +#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_LSB 0x2 +#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_MASK 0x4 +#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_SIZE 0x1 +#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_DEFAULT 0x0 +#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_OFFSET 0x28 +#define GC_SPS_FIFO_CTRL_RXFIFO_RST_LSB 0x3 +#define GC_SPS_FIFO_CTRL_RXFIFO_RST_MASK 0x8 +#define GC_SPS_FIFO_CTRL_RXFIFO_RST_SIZE 0x1 +#define GC_SPS_FIFO_CTRL_RXFIFO_RST_DEFAULT 0x0 +#define GC_SPS_FIFO_CTRL_RXFIFO_RST_OFFSET 0x28 +#define GC_SPS_FIFO_CTRL_RXFIFO_EN_LSB 0x4 +#define GC_SPS_FIFO_CTRL_RXFIFO_EN_MASK 0x10 +#define GC_SPS_FIFO_CTRL_RXFIFO_EN_SIZE 0x1 +#define GC_SPS_FIFO_CTRL_RXFIFO_EN_DEFAULT 0x0 +#define GC_SPS_FIFO_CTRL_RXFIFO_EN_OFFSET 0x28 +#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_LSB 0x5 +#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_MASK 0x20 +#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_SIZE 0x1 +#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_DEFAULT 0x0 +#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_OFFSET 0x28 +#define GC_SPS_ROM_REGION0_CTRL_READ_EN_LSB 0x0 +#define GC_SPS_ROM_REGION0_CTRL_READ_EN_MASK 0x1 +#define GC_SPS_ROM_REGION0_CTRL_READ_EN_SIZE 0x1 +#define GC_SPS_ROM_REGION0_CTRL_READ_EN_DEFAULT 0x0 +#define GC_SPS_ROM_REGION0_CTRL_READ_EN_OFFSET 0x4c +#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_LSB 0x1 +#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_MASK 0x2 +#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_SIZE 0x1 +#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_DEFAULT 0x0 +#define GC_SPS_ROM_REGION0_CTRL_WRITE_EN_OFFSET 0x4c +#define GC_SPS_ROM_REGION0_CTRL_WRAP_LSB 0x2 +#define GC_SPS_ROM_REGION0_CTRL_WRAP_MASK 0x4 +#define GC_SPS_ROM_REGION0_CTRL_WRAP_SIZE 0x1 +#define GC_SPS_ROM_REGION0_CTRL_WRAP_DEFAULT 0x0 +#define GC_SPS_ROM_REGION0_CTRL_WRAP_OFFSET 0x4c +#define GC_SPS_ROM_REGION1_CTRL_READ_EN_LSB 0x0 +#define GC_SPS_ROM_REGION1_CTRL_READ_EN_MASK 0x1 +#define GC_SPS_ROM_REGION1_CTRL_READ_EN_SIZE 0x1 +#define GC_SPS_ROM_REGION1_CTRL_READ_EN_DEFAULT 0x0 +#define GC_SPS_ROM_REGION1_CTRL_READ_EN_OFFSET 0x60 +#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_LSB 0x1 +#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_MASK 0x2 +#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_SIZE 0x1 +#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_DEFAULT 0x0 +#define GC_SPS_ROM_REGION1_CTRL_WRITE_EN_OFFSET 0x60 +#define GC_SPS_ROM_REGION1_CTRL_WRAP_LSB 0x2 +#define GC_SPS_ROM_REGION1_CTRL_WRAP_MASK 0x4 +#define GC_SPS_ROM_REGION1_CTRL_WRAP_SIZE 0x1 +#define GC_SPS_ROM_REGION1_CTRL_WRAP_DEFAULT 0x0 +#define GC_SPS_ROM_REGION1_CTRL_WRAP_OFFSET 0x60 +#define GC_SPS_ROM_REGION2_CTRL_READ_EN_LSB 0x0 +#define GC_SPS_ROM_REGION2_CTRL_READ_EN_MASK 0x1 +#define GC_SPS_ROM_REGION2_CTRL_READ_EN_SIZE 0x1 +#define GC_SPS_ROM_REGION2_CTRL_READ_EN_DEFAULT 0x0 +#define GC_SPS_ROM_REGION2_CTRL_READ_EN_OFFSET 0x74 +#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_LSB 0x1 +#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_MASK 0x2 +#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_SIZE 0x1 +#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_DEFAULT 0x0 +#define GC_SPS_ROM_REGION2_CTRL_WRITE_EN_OFFSET 0x74 +#define GC_SPS_ROM_REGION2_CTRL_WRAP_LSB 0x2 +#define GC_SPS_ROM_REGION2_CTRL_WRAP_MASK 0x4 +#define GC_SPS_ROM_REGION2_CTRL_WRAP_SIZE 0x1 +#define GC_SPS_ROM_REGION2_CTRL_WRAP_DEFAULT 0x0 +#define GC_SPS_ROM_REGION2_CTRL_WRAP_OFFSET 0x74 +#define GC_SPS_ROM_REGION3_CTRL_READ_EN_LSB 0x0 +#define GC_SPS_ROM_REGION3_CTRL_READ_EN_MASK 0x1 +#define GC_SPS_ROM_REGION3_CTRL_READ_EN_SIZE 0x1 +#define GC_SPS_ROM_REGION3_CTRL_READ_EN_DEFAULT 0x0 +#define GC_SPS_ROM_REGION3_CTRL_READ_EN_OFFSET 0x88 +#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_LSB 0x1 +#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_MASK 0x2 +#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_SIZE 0x1 +#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_DEFAULT 0x0 +#define GC_SPS_ROM_REGION3_CTRL_WRITE_EN_OFFSET 0x88 +#define GC_SPS_ROM_REGION3_CTRL_WRAP_LSB 0x2 +#define GC_SPS_ROM_REGION3_CTRL_WRAP_MASK 0x4 +#define GC_SPS_ROM_REGION3_CTRL_WRAP_SIZE 0x1 +#define GC_SPS_ROM_REGION3_CTRL_WRAP_DEFAULT 0x0 +#define GC_SPS_ROM_REGION3_CTRL_WRAP_OFFSET 0x88 +#define GC_SPS_OVRD_MISOEN_LSB 0x0 +#define GC_SPS_OVRD_MISOEN_MASK 0x1 +#define GC_SPS_OVRD_MISOEN_SIZE 0x1 +#define GC_SPS_OVRD_MISOEN_DEFAULT 0x0 +#define GC_SPS_OVRD_MISOEN_OFFSET 0xb4 +#define GC_SPS_OVRD_MISOVAL_LSB 0x1 +#define GC_SPS_OVRD_MISOVAL_MASK 0x2 +#define GC_SPS_OVRD_MISOVAL_SIZE 0x1 +#define GC_SPS_OVRD_MISOVAL_DEFAULT 0x0 +#define GC_SPS_OVRD_MISOVAL_OFFSET 0xb4 +#define GC_SPS_VAL_MISO_LSB 0x0 +#define GC_SPS_VAL_MISO_MASK 0x1 +#define GC_SPS_VAL_MISO_SIZE 0x1 +#define GC_SPS_VAL_MISO_DEFAULT 0x0 +#define GC_SPS_VAL_MISO_OFFSET 0xb8 +#define GC_SPS_VAL_MOSI_LSB 0x1 +#define GC_SPS_VAL_MOSI_MASK 0x2 +#define GC_SPS_VAL_MOSI_SIZE 0x1 +#define GC_SPS_VAL_MOSI_DEFAULT 0x0 +#define GC_SPS_VAL_MOSI_OFFSET 0xb8 +#define GC_SPS_VAL_CSB_LSB 0x2 +#define GC_SPS_VAL_CSB_MASK 0x4 +#define GC_SPS_VAL_CSB_SIZE 0x1 +#define GC_SPS_VAL_CSB_DEFAULT 0x0 +#define GC_SPS_VAL_CSB_OFFSET 0xb8 +#define GC_SPS_VAL_SCK_LSB 0x3 +#define GC_SPS_VAL_SCK_MASK 0x8 +#define GC_SPS_VAL_SCK_SIZE 0x1 +#define GC_SPS_VAL_SCK_DEFAULT 0x0 +#define GC_SPS_VAL_SCK_OFFSET 0xb8 +#define GC_SPS_ICTRL_CTLWR0_LSB 0x0 +#define GC_SPS_ICTRL_CTLWR0_MASK 0x1 +#define GC_SPS_ICTRL_CTLWR0_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR0_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR0_OFFSET 0xbc +#define GC_SPS_ICTRL_CTLWR1_LSB 0x1 +#define GC_SPS_ICTRL_CTLWR1_MASK 0x2 +#define GC_SPS_ICTRL_CTLWR1_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR1_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR1_OFFSET 0xbc +#define GC_SPS_ICTRL_CTLWR2_LSB 0x2 +#define GC_SPS_ICTRL_CTLWR2_MASK 0x4 +#define GC_SPS_ICTRL_CTLWR2_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR2_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR2_OFFSET 0xbc +#define GC_SPS_ICTRL_CTLWR3_LSB 0x3 +#define GC_SPS_ICTRL_CTLWR3_MASK 0x8 +#define GC_SPS_ICTRL_CTLWR3_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR3_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR3_OFFSET 0xbc +#define GC_SPS_ICTRL_CTLWR4_LSB 0x4 +#define GC_SPS_ICTRL_CTLWR4_MASK 0x10 +#define GC_SPS_ICTRL_CTLWR4_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR4_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR4_OFFSET 0xbc +#define GC_SPS_ICTRL_CTLWR5_LSB 0x5 +#define GC_SPS_ICTRL_CTLWR5_MASK 0x20 +#define GC_SPS_ICTRL_CTLWR5_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR5_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR5_OFFSET 0xbc +#define GC_SPS_ICTRL_CTLWR6_LSB 0x6 +#define GC_SPS_ICTRL_CTLWR6_MASK 0x40 +#define GC_SPS_ICTRL_CTLWR6_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR6_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR6_OFFSET 0xbc +#define GC_SPS_ICTRL_CTLWR7_LSB 0x7 +#define GC_SPS_ICTRL_CTLWR7_MASK 0x80 +#define GC_SPS_ICTRL_CTLWR7_SIZE 0x1 +#define GC_SPS_ICTRL_CTLWR7_DEFAULT 0x0 +#define GC_SPS_ICTRL_CTLWR7_OFFSET 0xbc +#define GC_SPS_ICTRL_CS_ASSERT_LSB 0x8 +#define GC_SPS_ICTRL_CS_ASSERT_MASK 0x100 +#define GC_SPS_ICTRL_CS_ASSERT_SIZE 0x1 +#define GC_SPS_ICTRL_CS_ASSERT_DEFAULT 0x0 +#define GC_SPS_ICTRL_CS_ASSERT_OFFSET 0xbc +#define GC_SPS_ICTRL_CS_DEASSERT_LSB 0x9 +#define GC_SPS_ICTRL_CS_DEASSERT_MASK 0x200 +#define GC_SPS_ICTRL_CS_DEASSERT_SIZE 0x1 +#define GC_SPS_ICTRL_CS_DEASSERT_DEFAULT 0x0 +#define GC_SPS_ICTRL_CS_DEASSERT_OFFSET 0xbc +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_LSB 0xa +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_MASK 0x400 +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_SIZE 0x1 +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_OFFSET 0xbc +#define GC_SPS_ICTRL_TXFIFO_EMPTY_LSB 0xb +#define GC_SPS_ICTRL_TXFIFO_EMPTY_MASK 0x800 +#define GC_SPS_ICTRL_TXFIFO_EMPTY_SIZE 0x1 +#define GC_SPS_ICTRL_TXFIFO_EMPTY_DEFAULT 0x0 +#define GC_SPS_ICTRL_TXFIFO_EMPTY_OFFSET 0xbc +#define GC_SPS_ICTRL_TXFIFO_FULL_LSB 0xc +#define GC_SPS_ICTRL_TXFIFO_FULL_MASK 0x1000 +#define GC_SPS_ICTRL_TXFIFO_FULL_SIZE 0x1 +#define GC_SPS_ICTRL_TXFIFO_FULL_DEFAULT 0x0 +#define GC_SPS_ICTRL_TXFIFO_FULL_OFFSET 0xbc +#define GC_SPS_ICTRL_TXFIFO_LVL_LSB 0xd +#define GC_SPS_ICTRL_TXFIFO_LVL_MASK 0x2000 +#define GC_SPS_ICTRL_TXFIFO_LVL_SIZE 0x1 +#define GC_SPS_ICTRL_TXFIFO_LVL_DEFAULT 0x0 +#define GC_SPS_ICTRL_TXFIFO_LVL_OFFSET 0xbc +#define GC_SPS_ICTRL_RXFIFO_LVL_LSB 0xe +#define GC_SPS_ICTRL_RXFIFO_LVL_MASK 0x4000 +#define GC_SPS_ICTRL_RXFIFO_LVL_SIZE 0x1 +#define GC_SPS_ICTRL_RXFIFO_LVL_DEFAULT 0x0 +#define GC_SPS_ICTRL_RXFIFO_LVL_OFFSET 0xbc +#define GC_SPS_ICTRL_ROM_CMD_START_LSB 0xf +#define GC_SPS_ICTRL_ROM_CMD_START_MASK 0x8000 +#define GC_SPS_ICTRL_ROM_CMD_START_SIZE 0x1 +#define GC_SPS_ICTRL_ROM_CMD_START_DEFAULT 0x0 +#define GC_SPS_ICTRL_ROM_CMD_START_OFFSET 0xbc +#define GC_SPS_ICTRL_ROM_CMD_END_LSB 0x10 +#define GC_SPS_ICTRL_ROM_CMD_END_MASK 0x10000 +#define GC_SPS_ICTRL_ROM_CMD_END_SIZE 0x1 +#define GC_SPS_ICTRL_ROM_CMD_END_DEFAULT 0x0 +#define GC_SPS_ICTRL_ROM_CMD_END_OFFSET 0xbc +#define GC_SPS_ICTRL_REGION0_BUF_LVL_LSB 0x11 +#define GC_SPS_ICTRL_REGION0_BUF_LVL_MASK 0x20000 +#define GC_SPS_ICTRL_REGION0_BUF_LVL_SIZE 0x1 +#define GC_SPS_ICTRL_REGION0_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ICTRL_REGION0_BUF_LVL_OFFSET 0xbc +#define GC_SPS_ICTRL_REGION1_BUF_LVL_LSB 0x12 +#define GC_SPS_ICTRL_REGION1_BUF_LVL_MASK 0x40000 +#define GC_SPS_ICTRL_REGION1_BUF_LVL_SIZE 0x1 +#define GC_SPS_ICTRL_REGION1_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ICTRL_REGION1_BUF_LVL_OFFSET 0xbc +#define GC_SPS_ICTRL_REGION2_BUF_LVL_LSB 0x13 +#define GC_SPS_ICTRL_REGION2_BUF_LVL_MASK 0x80000 +#define GC_SPS_ICTRL_REGION2_BUF_LVL_SIZE 0x1 +#define GC_SPS_ICTRL_REGION2_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ICTRL_REGION2_BUF_LVL_OFFSET 0xbc +#define GC_SPS_ICTRL_REGION3_BUF_LVL_LSB 0x14 +#define GC_SPS_ICTRL_REGION3_BUF_LVL_MASK 0x100000 +#define GC_SPS_ICTRL_REGION3_BUF_LVL_SIZE 0x1 +#define GC_SPS_ICTRL_REGION3_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ICTRL_REGION3_BUF_LVL_OFFSET 0xbc +#define GC_SPS_ISTATE_CTLWR0_LSB 0x0 +#define GC_SPS_ISTATE_CTLWR0_MASK 0x1 +#define GC_SPS_ISTATE_CTLWR0_SIZE 0x1 +#define GC_SPS_ISTATE_CTLWR0_DEFAULT 0x0 +#define GC_SPS_ISTATE_CTLWR0_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR1_LSB 0x1 +#define GC_SPS_ISTATE_CTLWR1_MASK 0x2 +#define GC_SPS_ISTATE_CTLWR1_SIZE 0x1 +#define GC_SPS_ISTATE_CTLWR1_DEFAULT 0x0 +#define GC_SPS_ISTATE_CTLWR1_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR2_LSB 0x2 +#define GC_SPS_ISTATE_CTLWR2_MASK 0x4 +#define GC_SPS_ISTATE_CTLWR2_SIZE 0x1 +#define GC_SPS_ISTATE_CTLWR2_DEFAULT 0x0 +#define GC_SPS_ISTATE_CTLWR2_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR3_LSB 0x3 +#define GC_SPS_ISTATE_CTLWR3_MASK 0x8 +#define GC_SPS_ISTATE_CTLWR3_SIZE 0x1 +#define GC_SPS_ISTATE_CTLWR3_DEFAULT 0x0 +#define GC_SPS_ISTATE_CTLWR3_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR4_LSB 0x4 +#define GC_SPS_ISTATE_CTLWR4_MASK 0x10 +#define GC_SPS_ISTATE_CTLWR4_SIZE 0x1 +#define GC_SPS_ISTATE_CTLWR4_DEFAULT 0x0 +#define GC_SPS_ISTATE_CTLWR4_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR5_LSB 0x5 +#define GC_SPS_ISTATE_CTLWR5_MASK 0x20 +#define GC_SPS_ISTATE_CTLWR5_SIZE 0x1 +#define GC_SPS_ISTATE_CTLWR5_DEFAULT 0x0 +#define GC_SPS_ISTATE_CTLWR5_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR6_LSB 0x6 +#define GC_SPS_ISTATE_CTLWR6_MASK 0x40 +#define GC_SPS_ISTATE_CTLWR6_SIZE 0x1 +#define GC_SPS_ISTATE_CTLWR6_DEFAULT 0x0 +#define GC_SPS_ISTATE_CTLWR6_OFFSET 0xc0 +#define GC_SPS_ISTATE_CTLWR7_LSB 0x7 +#define GC_SPS_ISTATE_CTLWR7_MASK 0x80 +#define GC_SPS_ISTATE_CTLWR7_SIZE 0x1 +#define GC_SPS_ISTATE_CTLWR7_DEFAULT 0x0 +#define GC_SPS_ISTATE_CTLWR7_OFFSET 0xc0 +#define GC_SPS_ISTATE_CS_ASSERT_LSB 0x8 +#define GC_SPS_ISTATE_CS_ASSERT_MASK 0x100 +#define GC_SPS_ISTATE_CS_ASSERT_SIZE 0x1 +#define GC_SPS_ISTATE_CS_ASSERT_DEFAULT 0x0 +#define GC_SPS_ISTATE_CS_ASSERT_OFFSET 0xc0 +#define GC_SPS_ISTATE_CS_DEASSERT_LSB 0x9 +#define GC_SPS_ISTATE_CS_DEASSERT_MASK 0x200 +#define GC_SPS_ISTATE_CS_DEASSERT_SIZE 0x1 +#define GC_SPS_ISTATE_CS_DEASSERT_DEFAULT 0x0 +#define GC_SPS_ISTATE_CS_DEASSERT_OFFSET 0xc0 +#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_LSB 0xa +#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_MASK 0x400 +#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_SIZE 0x1 +#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_OFFSET 0xc0 +#define GC_SPS_ISTATE_TXFIFO_EMPTY_LSB 0xb +#define GC_SPS_ISTATE_TXFIFO_EMPTY_MASK 0x800 +#define GC_SPS_ISTATE_TXFIFO_EMPTY_SIZE 0x1 +#define GC_SPS_ISTATE_TXFIFO_EMPTY_DEFAULT 0x0 +#define GC_SPS_ISTATE_TXFIFO_EMPTY_OFFSET 0xc0 +#define GC_SPS_ISTATE_TXFIFO_FULL_LSB 0xc +#define GC_SPS_ISTATE_TXFIFO_FULL_MASK 0x1000 +#define GC_SPS_ISTATE_TXFIFO_FULL_SIZE 0x1 +#define GC_SPS_ISTATE_TXFIFO_FULL_DEFAULT 0x0 +#define GC_SPS_ISTATE_TXFIFO_FULL_OFFSET 0xc0 +#define GC_SPS_ISTATE_TXFIFO_LVL_LSB 0xd +#define GC_SPS_ISTATE_TXFIFO_LVL_MASK 0x2000 +#define GC_SPS_ISTATE_TXFIFO_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_TXFIFO_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_TXFIFO_LVL_OFFSET 0xc0 +#define GC_SPS_ISTATE_RXFIFO_LVL_LSB 0xe +#define GC_SPS_ISTATE_RXFIFO_LVL_MASK 0x4000 +#define GC_SPS_ISTATE_RXFIFO_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_RXFIFO_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_RXFIFO_LVL_OFFSET 0xc0 +#define GC_SPS_ISTATE_ROM_CMD_START_LSB 0xf +#define GC_SPS_ISTATE_ROM_CMD_START_MASK 0x8000 +#define GC_SPS_ISTATE_ROM_CMD_START_SIZE 0x1 +#define GC_SPS_ISTATE_ROM_CMD_START_DEFAULT 0x0 +#define GC_SPS_ISTATE_ROM_CMD_START_OFFSET 0xc0 +#define GC_SPS_ISTATE_ROM_CMD_END_LSB 0x10 +#define GC_SPS_ISTATE_ROM_CMD_END_MASK 0x10000 +#define GC_SPS_ISTATE_ROM_CMD_END_SIZE 0x1 +#define GC_SPS_ISTATE_ROM_CMD_END_DEFAULT 0x0 +#define GC_SPS_ISTATE_ROM_CMD_END_OFFSET 0xc0 +#define GC_SPS_ISTATE_REGION0_BUF_LVL_LSB 0x11 +#define GC_SPS_ISTATE_REGION0_BUF_LVL_MASK 0x20000 +#define GC_SPS_ISTATE_REGION0_BUF_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_REGION0_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_REGION0_BUF_LVL_OFFSET 0xc0 +#define GC_SPS_ISTATE_REGION1_BUF_LVL_LSB 0x12 +#define GC_SPS_ISTATE_REGION1_BUF_LVL_MASK 0x40000 +#define GC_SPS_ISTATE_REGION1_BUF_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_REGION1_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_REGION1_BUF_LVL_OFFSET 0xc0 +#define GC_SPS_ISTATE_REGION2_BUF_LVL_LSB 0x13 +#define GC_SPS_ISTATE_REGION2_BUF_LVL_MASK 0x80000 +#define GC_SPS_ISTATE_REGION2_BUF_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_REGION2_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_REGION2_BUF_LVL_OFFSET 0xc0 +#define GC_SPS_ISTATE_REGION3_BUF_LVL_LSB 0x14 +#define GC_SPS_ISTATE_REGION3_BUF_LVL_MASK 0x100000 +#define GC_SPS_ISTATE_REGION3_BUF_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_REGION3_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_REGION3_BUF_LVL_OFFSET 0xc0 +#define GC_SPS_ISTATE_CLR_CTLWR0_LSB 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR0_MASK 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR0_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR0_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR0_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR1_LSB 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR1_MASK 0x2 +#define GC_SPS_ISTATE_CLR_CTLWR1_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR1_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR1_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR2_LSB 0x2 +#define GC_SPS_ISTATE_CLR_CTLWR2_MASK 0x4 +#define GC_SPS_ISTATE_CLR_CTLWR2_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR2_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR2_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR3_LSB 0x3 +#define GC_SPS_ISTATE_CLR_CTLWR3_MASK 0x8 +#define GC_SPS_ISTATE_CLR_CTLWR3_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR3_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR3_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR4_LSB 0x4 +#define GC_SPS_ISTATE_CLR_CTLWR4_MASK 0x10 +#define GC_SPS_ISTATE_CLR_CTLWR4_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR4_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR4_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR5_LSB 0x5 +#define GC_SPS_ISTATE_CLR_CTLWR5_MASK 0x20 +#define GC_SPS_ISTATE_CLR_CTLWR5_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR5_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR5_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR6_LSB 0x6 +#define GC_SPS_ISTATE_CLR_CTLWR6_MASK 0x40 +#define GC_SPS_ISTATE_CLR_CTLWR6_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR6_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR6_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CTLWR7_LSB 0x7 +#define GC_SPS_ISTATE_CLR_CTLWR7_MASK 0x80 +#define GC_SPS_ISTATE_CLR_CTLWR7_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CTLWR7_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CTLWR7_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CS_ASSERT_LSB 0x8 +#define GC_SPS_ISTATE_CLR_CS_ASSERT_MASK 0x100 +#define GC_SPS_ISTATE_CLR_CS_ASSERT_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CS_ASSERT_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CS_ASSERT_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_CS_DEASSERT_LSB 0x9 +#define GC_SPS_ISTATE_CLR_CS_DEASSERT_MASK 0x200 +#define GC_SPS_ISTATE_CLR_CS_DEASSERT_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_CS_DEASSERT_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_CS_DEASSERT_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_LSB 0xa +#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_MASK 0x400 +#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_ROM_CMD_START_LSB 0xb +#define GC_SPS_ISTATE_CLR_ROM_CMD_START_MASK 0x800 +#define GC_SPS_ISTATE_CLR_ROM_CMD_START_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_ROM_CMD_START_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_ROM_CMD_START_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_ROM_CMD_END_LSB 0xc +#define GC_SPS_ISTATE_CLR_ROM_CMD_END_MASK 0x1000 +#define GC_SPS_ISTATE_CLR_ROM_CMD_END_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_ROM_CMD_END_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_ROM_CMD_END_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_LSB 0xd +#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_MASK 0x2000 +#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_REGION0_BUF_LVL_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_LSB 0xe +#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_MASK 0x4000 +#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_REGION1_BUF_LVL_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_LSB 0xf +#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_MASK 0x8000 +#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_REGION2_BUF_LVL_OFFSET 0xc4 +#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_LSB 0x10 +#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_MASK 0x10000 +#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_SIZE 0x1 +#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ISTATE_CLR_REGION3_BUF_LVL_OFFSET 0xc4 +#define GC_SPS_ITOP_CTRLINT0_LSB 0x0 +#define GC_SPS_ITOP_CTRLINT0_MASK 0x1 +#define GC_SPS_ITOP_CTRLINT0_SIZE 0x1 +#define GC_SPS_ITOP_CTRLINT0_DEFAULT 0x0 +#define GC_SPS_ITOP_CTRLINT0_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT1_LSB 0x1 +#define GC_SPS_ITOP_CTRLINT1_MASK 0x2 +#define GC_SPS_ITOP_CTRLINT1_SIZE 0x1 +#define GC_SPS_ITOP_CTRLINT1_DEFAULT 0x0 +#define GC_SPS_ITOP_CTRLINT1_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT2_LSB 0x2 +#define GC_SPS_ITOP_CTRLINT2_MASK 0x4 +#define GC_SPS_ITOP_CTRLINT2_SIZE 0x1 +#define GC_SPS_ITOP_CTRLINT2_DEFAULT 0x0 +#define GC_SPS_ITOP_CTRLINT2_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT3_LSB 0x3 +#define GC_SPS_ITOP_CTRLINT3_MASK 0x8 +#define GC_SPS_ITOP_CTRLINT3_SIZE 0x1 +#define GC_SPS_ITOP_CTRLINT3_DEFAULT 0x0 +#define GC_SPS_ITOP_CTRLINT3_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT4_LSB 0x4 +#define GC_SPS_ITOP_CTRLINT4_MASK 0x10 +#define GC_SPS_ITOP_CTRLINT4_SIZE 0x1 +#define GC_SPS_ITOP_CTRLINT4_DEFAULT 0x0 +#define GC_SPS_ITOP_CTRLINT4_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT5_LSB 0x5 +#define GC_SPS_ITOP_CTRLINT5_MASK 0x20 +#define GC_SPS_ITOP_CTRLINT5_SIZE 0x1 +#define GC_SPS_ITOP_CTRLINT5_DEFAULT 0x0 +#define GC_SPS_ITOP_CTRLINT5_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT6_LSB 0x6 +#define GC_SPS_ITOP_CTRLINT6_MASK 0x40 +#define GC_SPS_ITOP_CTRLINT6_SIZE 0x1 +#define GC_SPS_ITOP_CTRLINT6_DEFAULT 0x0 +#define GC_SPS_ITOP_CTRLINT6_OFFSET 0xf04 +#define GC_SPS_ITOP_CTRLINT7_LSB 0x7 +#define GC_SPS_ITOP_CTRLINT7_MASK 0x80 +#define GC_SPS_ITOP_CTRLINT7_SIZE 0x1 +#define GC_SPS_ITOP_CTRLINT7_DEFAULT 0x0 +#define GC_SPS_ITOP_CTRLINT7_OFFSET 0xf04 +#define GC_SPS_ITOP_CS_ASSERT_LSB 0x8 +#define GC_SPS_ITOP_CS_ASSERT_MASK 0x100 +#define GC_SPS_ITOP_CS_ASSERT_SIZE 0x1 +#define GC_SPS_ITOP_CS_ASSERT_DEFAULT 0x0 +#define GC_SPS_ITOP_CS_ASSERT_OFFSET 0xf04 +#define GC_SPS_ITOP_CS_DEASSERT_LSB 0x9 +#define GC_SPS_ITOP_CS_DEASSERT_MASK 0x200 +#define GC_SPS_ITOP_CS_DEASSERT_SIZE 0x1 +#define GC_SPS_ITOP_CS_DEASSERT_DEFAULT 0x0 +#define GC_SPS_ITOP_CS_DEASSERT_OFFSET 0xf04 +#define GC_SPS_ITOP_RXFIFO_OVERFLOW_LSB 0xa +#define GC_SPS_ITOP_RXFIFO_OVERFLOW_MASK 0x400 +#define GC_SPS_ITOP_RXFIFO_OVERFLOW_SIZE 0x1 +#define GC_SPS_ITOP_RXFIFO_OVERFLOW_DEFAULT 0x0 +#define GC_SPS_ITOP_RXFIFO_OVERFLOW_OFFSET 0xf04 +#define GC_SPS_ITOP_TXFIFO_EMPTY_LSB 0xb +#define GC_SPS_ITOP_TXFIFO_EMPTY_MASK 0x800 +#define GC_SPS_ITOP_TXFIFO_EMPTY_SIZE 0x1 +#define GC_SPS_ITOP_TXFIFO_EMPTY_DEFAULT 0x0 +#define GC_SPS_ITOP_TXFIFO_EMPTY_OFFSET 0xf04 +#define GC_SPS_ITOP_TXFIFO_FULL_LSB 0xc +#define GC_SPS_ITOP_TXFIFO_FULL_MASK 0x1000 +#define GC_SPS_ITOP_TXFIFO_FULL_SIZE 0x1 +#define GC_SPS_ITOP_TXFIFO_FULL_DEFAULT 0x0 +#define GC_SPS_ITOP_TXFIFO_FULL_OFFSET 0xf04 +#define GC_SPS_ITOP_TXFIFO_LVL_LSB 0xd +#define GC_SPS_ITOP_TXFIFO_LVL_MASK 0x2000 +#define GC_SPS_ITOP_TXFIFO_LVL_SIZE 0x1 +#define GC_SPS_ITOP_TXFIFO_LVL_DEFAULT 0x0 +#define GC_SPS_ITOP_TXFIFO_LVL_OFFSET 0xf04 +#define GC_SPS_ITOP_RXFIFO_LVL_LSB 0xe +#define GC_SPS_ITOP_RXFIFO_LVL_MASK 0x4000 +#define GC_SPS_ITOP_RXFIFO_LVL_SIZE 0x1 +#define GC_SPS_ITOP_RXFIFO_LVL_DEFAULT 0x0 +#define GC_SPS_ITOP_RXFIFO_LVL_OFFSET 0xf04 +#define GC_SPS_ITOP_ROM_CMD_START_LSB 0xf +#define GC_SPS_ITOP_ROM_CMD_START_MASK 0x8000 +#define GC_SPS_ITOP_ROM_CMD_START_SIZE 0x1 +#define GC_SPS_ITOP_ROM_CMD_START_DEFAULT 0x0 +#define GC_SPS_ITOP_ROM_CMD_START_OFFSET 0xf04 +#define GC_SPS_ITOP_ROM_CMD_END_LSB 0x10 +#define GC_SPS_ITOP_ROM_CMD_END_MASK 0x10000 +#define GC_SPS_ITOP_ROM_CMD_END_SIZE 0x1 +#define GC_SPS_ITOP_ROM_CMD_END_DEFAULT 0x0 +#define GC_SPS_ITOP_ROM_CMD_END_OFFSET 0xf04 +#define GC_SPS_ITOP_REGION0_BUF_LVL_LSB 0x11 +#define GC_SPS_ITOP_REGION0_BUF_LVL_MASK 0x20000 +#define GC_SPS_ITOP_REGION0_BUF_LVL_SIZE 0x1 +#define GC_SPS_ITOP_REGION0_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ITOP_REGION0_BUF_LVL_OFFSET 0xf04 +#define GC_SPS_ITOP_REGION1_BUF_LVL_LSB 0x12 +#define GC_SPS_ITOP_REGION1_BUF_LVL_MASK 0x40000 +#define GC_SPS_ITOP_REGION1_BUF_LVL_SIZE 0x1 +#define GC_SPS_ITOP_REGION1_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ITOP_REGION1_BUF_LVL_OFFSET 0xf04 +#define GC_SPS_ITOP_REGION2_BUF_LVL_LSB 0x13 +#define GC_SPS_ITOP_REGION2_BUF_LVL_MASK 0x80000 +#define GC_SPS_ITOP_REGION2_BUF_LVL_SIZE 0x1 +#define GC_SPS_ITOP_REGION2_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ITOP_REGION2_BUF_LVL_OFFSET 0xf04 +#define GC_SPS_ITOP_REGION3_BUF_LVL_LSB 0x14 +#define GC_SPS_ITOP_REGION3_BUF_LVL_MASK 0x100000 +#define GC_SPS_ITOP_REGION3_BUF_LVL_SIZE 0x1 +#define GC_SPS_ITOP_REGION3_BUF_LVL_DEFAULT 0x0 +#define GC_SPS_ITOP_REGION3_BUF_LVL_OFFSET 0xf04 +#define GC_TEMP_VERSION_CHANGE_LSB 0x0 +#define GC_TEMP_VERSION_CHANGE_MASK 0xffffff +#define GC_TEMP_VERSION_CHANGE_SIZE 0x18 +#define GC_TEMP_VERSION_CHANGE_DEFAULT 0xc178 +#define GC_TEMP_VERSION_CHANGE_OFFSET 0x0 +#define GC_TEMP_VERSION_REVISION_LSB 0x18 +#define GC_TEMP_VERSION_REVISION_MASK 0xff000000 +#define GC_TEMP_VERSION_REVISION_SIZE 0x8 +#define GC_TEMP_VERSION_REVISION_DEFAULT 0xd +#define GC_TEMP_VERSION_REVISION_OFFSET 0x0 +#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_LSB 0x0 +#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_MASK 0x1 +#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_SIZE 0x1 +#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_OFFSET 0x4 +#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_LSB 0x1 +#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_MASK 0x2 +#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_SIZE 0x1 +#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_ENABLE_MIN_TEMP_OFFSET 0x4 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_LSB 0x2 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_MASK 0x4 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_SIZE 0x1 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_OFFSET 0x4 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_LSB 0x3 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_MASK 0x8 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_SIZE 0x1 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_ENABLE_MAX_TEMP_DIFF_OFFSET 0x4 +#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_LSB 0x4 +#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_MASK 0x10 +#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_SIZE 0x1 +#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_OFFSET 0x4 +#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_LSB 0x0 +#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_MASK 0x1 +#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_SIZE 0x1 +#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_OFFSET 0x8 +#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_LSB 0x1 +#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_MASK 0x2 +#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_SIZE 0x1 +#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_STATE_MIN_TEMP_OFFSET 0x8 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_LSB 0x2 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_MASK 0x4 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_SIZE 0x1 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_OFFSET 0x8 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_LSB 0x3 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_MASK 0x8 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_SIZE 0x1 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_STATE_MAX_TEMP_DIFF_OFFSET 0x8 +#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_LSB 0x4 +#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_MASK 0x10 +#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_SIZE 0x1 +#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_OFFSET 0x8 +#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_LSB 0x0 +#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_MASK 0x1 +#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_SIZE 0x1 +#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_OFFSET 0xc +#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_LSB 0x1 +#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_MASK 0x2 +#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_SIZE 0x1 +#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_TEST_MIN_TEMP_OFFSET 0xc +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_LSB 0x2 +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_MASK 0x4 +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_SIZE 0x1 +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_OFFSET 0xc +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_LSB 0x3 +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_MASK 0x8 +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_SIZE 0x1 +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_TEST_MAX_TEMP_DIFF_OFFSET 0xc +#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_LSB 0x4 +#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_MASK 0x10 +#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_SIZE 0x1 +#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_DEFAULT 0x0 +#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_OFFSET 0xc +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_LSB 0x0 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_MASK 0x7 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_SIZE 0x3 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_DEFAULT 0x5 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_OFFSET 0x14 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P906V 0x3 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_1P120V 0x6 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P763V 0x1 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P691V 0x0 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_1P192V 0x7 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P977V 0x4 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_1P049V 0x5 +#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P834V 0x2 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_LSB 0x4 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_MASK 0x70 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_SIZE 0x3 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_DEFAULT 0x3 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_OFFSET 0x14 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P429V 0x2 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P477V 0x3 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P382V 0x1 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P572V 0x5 +#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P524V 0x4 +#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_LSB 0x0 +#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_MASK 0x1 +#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_SIZE 0x1 +#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_DEFAULT 0x0 +#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_LSB 0x1 +#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_MASK 0x2 +#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_SIZE 0x1 +#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_DEFAULT 0x0 +#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_LSB 0x2 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_MASK 0x4 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_SIZE 0x1 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_DEFAULT 0x1 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_LSB 0x3 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_MASK 0x8 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_SIZE 0x1 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_DEFAULT 0x0 +#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_LSB 0x4 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_MASK 0x70 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_SIZE 0x3 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_DEFAULT 0x6 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N5 0x5 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N4 0x4 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N3 0x3 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N2 0x2 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N1 0x1 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N0 0x0 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_VPTAT_CORE 0x6 +#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ANALOG_TEST_BUS 0x7 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_LSB 0x7 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_MASK 0x780 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_SIZE 0x4 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_DEFAULT 0x0 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_LSB 0xb +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_MASK 0x7800 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_SIZE 0x4 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_DEFAULT 0x1 +#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_LSB 0xf +#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_MASK 0x8000 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_SIZE 0x1 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_DEFAULT 0x1 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_LSB 0x10 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_MASK 0x10000 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_SIZE 0x1 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_DEFAULT 0x1 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_OFFSET 0x18 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_LSB 0x11 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_MASK 0x20000 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_SIZE 0x1 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_DEFAULT 0x1 +#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_OFFSET 0x18 +#define GC_TEMP_ADC_OPERATION_RESET_B_LSB 0x0 +#define GC_TEMP_ADC_OPERATION_RESET_B_MASK 0x1 +#define GC_TEMP_ADC_OPERATION_RESET_B_SIZE 0x1 +#define GC_TEMP_ADC_OPERATION_RESET_B_DEFAULT 0x0 +#define GC_TEMP_ADC_OPERATION_RESET_B_OFFSET 0x28 +#define GC_TEMP_ADC_OPERATION_ENABLE_LSB 0x1 +#define GC_TEMP_ADC_OPERATION_ENABLE_MASK 0x2 +#define GC_TEMP_ADC_OPERATION_ENABLE_SIZE 0x1 +#define GC_TEMP_ADC_OPERATION_ENABLE_DEFAULT 0x0 +#define GC_TEMP_ADC_OPERATION_ENABLE_OFFSET 0x28 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_LSB 0x0 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_MASK 0x3 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_SIZE 0x2 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_DEFAULT 0x0 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_OFFSET 0x40 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_ADC_SUM2 0x1 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_ADC_IOUT 0x0 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_ADC_SUM8 0x3 +#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_ADC_SUM4 0x2 +#define GC_TEMP_ABS_LIMIT_MIN_LSB 0x0 +#define GC_TEMP_ABS_LIMIT_MIN_MASK 0xfff +#define GC_TEMP_ABS_LIMIT_MIN_SIZE 0xc +#define GC_TEMP_ABS_LIMIT_MIN_DEFAULT 0x0 +#define GC_TEMP_ABS_LIMIT_MIN_OFFSET 0x44 +#define GC_TEMP_ABS_LIMIT_MAX_LSB 0xc +#define GC_TEMP_ABS_LIMIT_MAX_MASK 0xfff000 +#define GC_TEMP_ABS_LIMIT_MAX_SIZE 0xc +#define GC_TEMP_ABS_LIMIT_MAX_DEFAULT 0x0 +#define GC_TEMP_ABS_LIMIT_MAX_OFFSET 0x44 +#define GC_TEMP_DIFF_PARAM_MAX_LSB 0x0 +#define GC_TEMP_DIFF_PARAM_MAX_MASK 0xfff +#define GC_TEMP_DIFF_PARAM_MAX_SIZE 0xc +#define GC_TEMP_DIFF_PARAM_MAX_DEFAULT 0x0 +#define GC_TEMP_DIFF_PARAM_MAX_OFFSET 0x48 +#define GC_TEMP_DIFF_PARAM_PERIOD_LSB 0xc +#define GC_TEMP_DIFF_PARAM_PERIOD_MASK 0xfffff000 +#define GC_TEMP_DIFF_PARAM_PERIOD_SIZE 0x14 +#define GC_TEMP_DIFF_PARAM_PERIOD_DEFAULT 0x0 +#define GC_TEMP_DIFF_PARAM_PERIOD_OFFSET 0x48 +#define GC_TEMP_METRIC_DIFF_LSB 0x0 +#define GC_TEMP_METRIC_DIFF_MASK 0xfff +#define GC_TEMP_METRIC_DIFF_SIZE 0xc +#define GC_TEMP_METRIC_DIFF_DEFAULT 0x0 +#define GC_TEMP_METRIC_DIFF_OFFSET 0x4c +#define GC_TEMP_METRIC_CTR_LSB 0xc +#define GC_TEMP_METRIC_CTR_MASK 0xfffff000 +#define GC_TEMP_METRIC_CTR_SIZE 0x14 +#define GC_TEMP_METRIC_CTR_DEFAULT 0x0 +#define GC_TEMP_METRIC_CTR_OFFSET 0x4c +#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_LSB 0x0 +#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_MASK 0x1 +#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_SIZE 0x1 +#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_OFFSET 0x8 +#define GC_TIMEHS_TIMER1CONTROL_SIZE_LSB 0x1 +#define GC_TIMEHS_TIMER1CONTROL_SIZE_MASK 0x2 +#define GC_TIMEHS_TIMER1CONTROL_SIZE_SIZE 0x1 +#define GC_TIMEHS_TIMER1CONTROL_SIZE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1CONTROL_SIZE_OFFSET 0x8 +#define GC_TIMEHS_TIMER1CONTROL_PRE_LSB 0x2 +#define GC_TIMEHS_TIMER1CONTROL_PRE_MASK 0xc +#define GC_TIMEHS_TIMER1CONTROL_PRE_SIZE 0x2 +#define GC_TIMEHS_TIMER1CONTROL_PRE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1CONTROL_PRE_OFFSET 0x8 +#define GC_TIMEHS_TIMER1CONTROL_RESERVED_LSB 0x4 +#define GC_TIMEHS_TIMER1CONTROL_RESERVED_MASK 0x10 +#define GC_TIMEHS_TIMER1CONTROL_RESERVED_SIZE 0x1 +#define GC_TIMEHS_TIMER1CONTROL_RESERVED_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1CONTROL_RESERVED_OFFSET 0x8 +#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_LSB 0x5 +#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_MASK 0x20 +#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_SIZE 0x1 +#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_DEFAULT 0x1 +#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_OFFSET 0x8 +#define GC_TIMEHS_TIMER1CONTROL_MODE_LSB 0x6 +#define GC_TIMEHS_TIMER1CONTROL_MODE_MASK 0x40 +#define GC_TIMEHS_TIMER1CONTROL_MODE_SIZE 0x1 +#define GC_TIMEHS_TIMER1CONTROL_MODE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1CONTROL_MODE_OFFSET 0x8 +#define GC_TIMEHS_TIMER1CONTROL_ENABLE_LSB 0x7 +#define GC_TIMEHS_TIMER1CONTROL_ENABLE_MASK 0x80 +#define GC_TIMEHS_TIMER1CONTROL_ENABLE_SIZE 0x1 +#define GC_TIMEHS_TIMER1CONTROL_ENABLE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER1CONTROL_ENABLE_OFFSET 0x8 +#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_LSB 0x0 +#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_MASK 0x1 +#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_SIZE 0x1 +#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_OFFSET 0x28 +#define GC_TIMEHS_TIMER2CONTROL_SIZE_LSB 0x1 +#define GC_TIMEHS_TIMER2CONTROL_SIZE_MASK 0x2 +#define GC_TIMEHS_TIMER2CONTROL_SIZE_SIZE 0x1 +#define GC_TIMEHS_TIMER2CONTROL_SIZE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2CONTROL_SIZE_OFFSET 0x28 +#define GC_TIMEHS_TIMER2CONTROL_PRE_LSB 0x2 +#define GC_TIMEHS_TIMER2CONTROL_PRE_MASK 0xc +#define GC_TIMEHS_TIMER2CONTROL_PRE_SIZE 0x2 +#define GC_TIMEHS_TIMER2CONTROL_PRE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2CONTROL_PRE_OFFSET 0x28 +#define GC_TIMEHS_TIMER2CONTROL_RESERVED_LSB 0x4 +#define GC_TIMEHS_TIMER2CONTROL_RESERVED_MASK 0x10 +#define GC_TIMEHS_TIMER2CONTROL_RESERVED_SIZE 0x1 +#define GC_TIMEHS_TIMER2CONTROL_RESERVED_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2CONTROL_RESERVED_OFFSET 0x28 +#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_LSB 0x5 +#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_MASK 0x20 +#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_SIZE 0x1 +#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_DEFAULT 0x1 +#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_OFFSET 0x28 +#define GC_TIMEHS_TIMER2CONTROL_MODE_LSB 0x6 +#define GC_TIMEHS_TIMER2CONTROL_MODE_MASK 0x40 +#define GC_TIMEHS_TIMER2CONTROL_MODE_SIZE 0x1 +#define GC_TIMEHS_TIMER2CONTROL_MODE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2CONTROL_MODE_OFFSET 0x28 +#define GC_TIMEHS_TIMER2CONTROL_ENABLE_LSB 0x7 +#define GC_TIMEHS_TIMER2CONTROL_ENABLE_MASK 0x80 +#define GC_TIMEHS_TIMER2CONTROL_ENABLE_SIZE 0x1 +#define GC_TIMEHS_TIMER2CONTROL_ENABLE_DEFAULT 0x0 +#define GC_TIMEHS_TIMER2CONTROL_ENABLE_OFFSET 0x28 +#define GC_TIMEHS_TIMERITOP_TIMINT1_LSB 0x0 +#define GC_TIMEHS_TIMERITOP_TIMINT1_MASK 0x1 +#define GC_TIMEHS_TIMERITOP_TIMINT1_SIZE 0x1 +#define GC_TIMEHS_TIMERITOP_TIMINT1_DEFAULT 0x0 +#define GC_TIMEHS_TIMERITOP_TIMINT1_OFFSET 0xf04 +#define GC_TIMEHS_TIMERITOP_TIMINT2_LSB 0x1 +#define GC_TIMEHS_TIMERITOP_TIMINT2_MASK 0x2 +#define GC_TIMEHS_TIMERITOP_TIMINT2_SIZE 0x1 +#define GC_TIMEHS_TIMERITOP_TIMINT2_DEFAULT 0x0 +#define GC_TIMEHS_TIMERITOP_TIMINT2_OFFSET 0xf04 +#define GC_TIMELS_TIMER0_CONTROL_ENABLE_LSB 0x0 +#define GC_TIMELS_TIMER0_CONTROL_ENABLE_MASK 0x1 +#define GC_TIMELS_TIMER0_CONTROL_ENABLE_SIZE 0x1 +#define GC_TIMELS_TIMER0_CONTROL_ENABLE_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_CONTROL_ENABLE_OFFSET 0x0 +#define GC_TIMELS_TIMER0_CONTROL_RELOAD_LSB 0x1 +#define GC_TIMELS_TIMER0_CONTROL_RELOAD_MASK 0x2 +#define GC_TIMELS_TIMER0_CONTROL_RELOAD_SIZE 0x1 +#define GC_TIMELS_TIMER0_CONTROL_RELOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_CONTROL_RELOAD_OFFSET 0x0 +#define GC_TIMELS_TIMER0_CONTROL_WRAP_LSB 0x2 +#define GC_TIMELS_TIMER0_CONTROL_WRAP_MASK 0x4 +#define GC_TIMELS_TIMER0_CONTROL_WRAP_SIZE 0x1 +#define GC_TIMELS_TIMER0_CONTROL_WRAP_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_CONTROL_WRAP_OFFSET 0x0 +#define GC_TIMELS_TIMER0_CONTROL_TEST_LSB 0x3 +#define GC_TIMELS_TIMER0_CONTROL_TEST_MASK 0x8 +#define GC_TIMELS_TIMER0_CONTROL_TEST_SIZE 0x1 +#define GC_TIMELS_TIMER0_CONTROL_TEST_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_CONTROL_TEST_OFFSET 0x0 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_LSB 0x0 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_MASK 0x1 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_SIZE 0x1 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_OFFSET 0x4 +#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_LSB 0x1 +#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_MASK 0x2 +#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_SIZE 0x1 +#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_OFFSET 0x4 +#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_LSB 0x2 +#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_MASK 0x4 +#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_SIZE 0x1 +#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_OFFSET 0x4 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_LSB 0x3 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_MASK 0x8 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_SIZE 0x1 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_OFFSET 0x4 +#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_LSB 0x4 +#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_MASK 0x10 +#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_SIZE 0x1 +#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_OFFSET 0x4 +#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_LSB 0x5 +#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_MASK 0x20 +#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_SIZE 0x1 +#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_OFFSET 0x4 +#define GC_TIMELS_TIMER0_STATUS_WRAPPED_LSB 0x6 +#define GC_TIMELS_TIMER0_STATUS_WRAPPED_MASK 0x40 +#define GC_TIMELS_TIMER0_STATUS_WRAPPED_SIZE 0x1 +#define GC_TIMELS_TIMER0_STATUS_WRAPPED_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_STATUS_WRAPPED_OFFSET 0x4 +#define GC_TIMELS_TIMER0_SETHOLD_EN_LSB 0x0 +#define GC_TIMELS_TIMER0_SETHOLD_EN_MASK 0x1 +#define GC_TIMELS_TIMER0_SETHOLD_EN_SIZE 0x1 +#define GC_TIMELS_TIMER0_SETHOLD_EN_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_SETHOLD_EN_OFFSET 0x28 +#define GC_TIMELS_TIMER0_CLRHOLD_EN_LSB 0x0 +#define GC_TIMELS_TIMER0_CLRHOLD_EN_MASK 0x1 +#define GC_TIMELS_TIMER0_CLRHOLD_EN_SIZE 0x1 +#define GC_TIMELS_TIMER0_CLRHOLD_EN_DEFAULT 0x0 +#define GC_TIMELS_TIMER0_CLRHOLD_EN_OFFSET 0x2c +#define GC_TIMELS_TIMER1_CONTROL_ENABLE_LSB 0x0 +#define GC_TIMELS_TIMER1_CONTROL_ENABLE_MASK 0x1 +#define GC_TIMELS_TIMER1_CONTROL_ENABLE_SIZE 0x1 +#define GC_TIMELS_TIMER1_CONTROL_ENABLE_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_CONTROL_ENABLE_OFFSET 0x40 +#define GC_TIMELS_TIMER1_CONTROL_RELOAD_LSB 0x1 +#define GC_TIMELS_TIMER1_CONTROL_RELOAD_MASK 0x2 +#define GC_TIMELS_TIMER1_CONTROL_RELOAD_SIZE 0x1 +#define GC_TIMELS_TIMER1_CONTROL_RELOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_CONTROL_RELOAD_OFFSET 0x40 +#define GC_TIMELS_TIMER1_CONTROL_WRAP_LSB 0x2 +#define GC_TIMELS_TIMER1_CONTROL_WRAP_MASK 0x4 +#define GC_TIMELS_TIMER1_CONTROL_WRAP_SIZE 0x1 +#define GC_TIMELS_TIMER1_CONTROL_WRAP_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_CONTROL_WRAP_OFFSET 0x40 +#define GC_TIMELS_TIMER1_CONTROL_TEST_LSB 0x3 +#define GC_TIMELS_TIMER1_CONTROL_TEST_MASK 0x8 +#define GC_TIMELS_TIMER1_CONTROL_TEST_SIZE 0x1 +#define GC_TIMELS_TIMER1_CONTROL_TEST_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_CONTROL_TEST_OFFSET 0x40 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_LSB 0x0 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_MASK 0x1 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_SIZE 0x1 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_OFFSET 0x44 +#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_LSB 0x1 +#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_MASK 0x2 +#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_SIZE 0x1 +#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_OFFSET 0x44 +#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_LSB 0x2 +#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_MASK 0x4 +#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_SIZE 0x1 +#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_OFFSET 0x44 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_LSB 0x3 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_MASK 0x8 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_SIZE 0x1 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_OFFSET 0x44 +#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_LSB 0x4 +#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_MASK 0x10 +#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_SIZE 0x1 +#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_OFFSET 0x44 +#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_LSB 0x5 +#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_MASK 0x20 +#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_SIZE 0x1 +#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_OFFSET 0x44 +#define GC_TIMELS_TIMER1_STATUS_WRAPPED_LSB 0x6 +#define GC_TIMELS_TIMER1_STATUS_WRAPPED_MASK 0x40 +#define GC_TIMELS_TIMER1_STATUS_WRAPPED_SIZE 0x1 +#define GC_TIMELS_TIMER1_STATUS_WRAPPED_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_STATUS_WRAPPED_OFFSET 0x44 +#define GC_TIMELS_TIMER1_SETHOLD_EN_LSB 0x0 +#define GC_TIMELS_TIMER1_SETHOLD_EN_MASK 0x1 +#define GC_TIMELS_TIMER1_SETHOLD_EN_SIZE 0x1 +#define GC_TIMELS_TIMER1_SETHOLD_EN_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_SETHOLD_EN_OFFSET 0x68 +#define GC_TIMELS_TIMER1_CLRHOLD_EN_LSB 0x0 +#define GC_TIMELS_TIMER1_CLRHOLD_EN_MASK 0x1 +#define GC_TIMELS_TIMER1_CLRHOLD_EN_SIZE 0x1 +#define GC_TIMELS_TIMER1_CLRHOLD_EN_DEFAULT 0x0 +#define GC_TIMELS_TIMER1_CLRHOLD_EN_OFFSET 0x6c +#define GC_TIMELS_ITOP_TIMINT0_LSB 0x0 +#define GC_TIMELS_ITOP_TIMINT0_MASK 0x1 +#define GC_TIMELS_ITOP_TIMINT0_SIZE 0x1 +#define GC_TIMELS_ITOP_TIMINT0_DEFAULT 0x0 +#define GC_TIMELS_ITOP_TIMINT0_OFFSET 0xf04 +#define GC_TIMELS_ITOP_TIMINT1_LSB 0x1 +#define GC_TIMELS_ITOP_TIMINT1_MASK 0x2 +#define GC_TIMELS_ITOP_TIMINT1_SIZE 0x1 +#define GC_TIMELS_ITOP_TIMINT1_DEFAULT 0x0 +#define GC_TIMELS_ITOP_TIMINT1_OFFSET 0xf04 +#define GC_TRNG_VERSION_CHANGE_LSB 0x0 +#define GC_TRNG_VERSION_CHANGE_MASK 0xffffff +#define GC_TRNG_VERSION_CHANGE_SIZE 0x18 +#define GC_TRNG_VERSION_CHANGE_DEFAULT 0xc241 +#define GC_TRNG_VERSION_CHANGE_OFFSET 0x0 +#define GC_TRNG_VERSION_REVISION_LSB 0x18 +#define GC_TRNG_VERSION_REVISION_MASK 0xff000000 +#define GC_TRNG_VERSION_REVISION_SIZE 0x8 +#define GC_TRNG_VERSION_REVISION_DEFAULT 0x7 +#define GC_TRNG_VERSION_REVISION_OFFSET 0x0 +#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_LSB 0x0 +#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_MASK 0x1 +#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_SIZE 0x1 +#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_DEFAULT 0x0 +#define GC_TRNG_INT_ENABLE_INTR_TIMEOUT_OFFSET 0x4 +#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_LSB 0x1 +#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_MASK 0x2 +#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_SIZE 0x1 +#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_DEFAULT 0x0 +#define GC_TRNG_INT_ENABLE_INTR_CALC_DONE_OFFSET 0x4 +#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_LSB 0x2 +#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_MASK 0x4 +#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_SIZE 0x1 +#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_DEFAULT 0x0 +#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_OFFSET 0x4 +#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_LSB 0x3 +#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_MASK 0x8 +#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_SIZE 0x1 +#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_DEFAULT 0x0 +#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_OFFSET 0x4 +#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_LSB 0x4 +#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_MASK 0x10 +#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_SIZE 0x1 +#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_DEFAULT 0x0 +#define GC_TRNG_INT_ENABLE_INTR_STAT_40_60_OFFSET 0x4 +#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_LSB 0x5 +#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_MASK 0x20 +#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_SIZE 0x1 +#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_DEFAULT 0x0 +#define GC_TRNG_INT_ENABLE_INTR_STAT_30_70_OFFSET 0x4 +#define GC_TRNG_INT_STATE_INTR_TIMEOUT_LSB 0x0 +#define GC_TRNG_INT_STATE_INTR_TIMEOUT_MASK 0x1 +#define GC_TRNG_INT_STATE_INTR_TIMEOUT_SIZE 0x1 +#define GC_TRNG_INT_STATE_INTR_TIMEOUT_DEFAULT 0x0 +#define GC_TRNG_INT_STATE_INTR_TIMEOUT_OFFSET 0x8 +#define GC_TRNG_INT_STATE_INTR_CALC_DONE_LSB 0x1 +#define GC_TRNG_INT_STATE_INTR_CALC_DONE_MASK 0x2 +#define GC_TRNG_INT_STATE_INTR_CALC_DONE_SIZE 0x1 +#define GC_TRNG_INT_STATE_INTR_CALC_DONE_DEFAULT 0x0 +#define GC_TRNG_INT_STATE_INTR_CALC_DONE_OFFSET 0x8 +#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_LSB 0x2 +#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_MASK 0x4 +#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_SIZE 0x1 +#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_DEFAULT 0x0 +#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_OFFSET 0x8 +#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_LSB 0x3 +#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_MASK 0x8 +#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_SIZE 0x1 +#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_DEFAULT 0x0 +#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_OFFSET 0x8 +#define GC_TRNG_INT_STATE_INTR_STAT_40_60_LSB 0x4 +#define GC_TRNG_INT_STATE_INTR_STAT_40_60_MASK 0x10 +#define GC_TRNG_INT_STATE_INTR_STAT_40_60_SIZE 0x1 +#define GC_TRNG_INT_STATE_INTR_STAT_40_60_DEFAULT 0x0 +#define GC_TRNG_INT_STATE_INTR_STAT_40_60_OFFSET 0x8 +#define GC_TRNG_INT_STATE_INTR_STAT_30_70_LSB 0x5 +#define GC_TRNG_INT_STATE_INTR_STAT_30_70_MASK 0x20 +#define GC_TRNG_INT_STATE_INTR_STAT_30_70_SIZE 0x1 +#define GC_TRNG_INT_STATE_INTR_STAT_30_70_DEFAULT 0x0 +#define GC_TRNG_INT_STATE_INTR_STAT_30_70_OFFSET 0x8 +#define GC_TRNG_INT_TEST_INTR_TIMEOUT_LSB 0x0 +#define GC_TRNG_INT_TEST_INTR_TIMEOUT_MASK 0x1 +#define GC_TRNG_INT_TEST_INTR_TIMEOUT_SIZE 0x1 +#define GC_TRNG_INT_TEST_INTR_TIMEOUT_DEFAULT 0x0 +#define GC_TRNG_INT_TEST_INTR_TIMEOUT_OFFSET 0xc +#define GC_TRNG_INT_TEST_INTR_CALC_DONE_LSB 0x1 +#define GC_TRNG_INT_TEST_INTR_CALC_DONE_MASK 0x2 +#define GC_TRNG_INT_TEST_INTR_CALC_DONE_SIZE 0x1 +#define GC_TRNG_INT_TEST_INTR_CALC_DONE_DEFAULT 0x0 +#define GC_TRNG_INT_TEST_INTR_CALC_DONE_OFFSET 0xc +#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_LSB 0x2 +#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_MASK 0x4 +#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_SIZE 0x1 +#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_DEFAULT 0x0 +#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_OFFSET 0xc +#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_LSB 0x3 +#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_MASK 0x8 +#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_SIZE 0x1 +#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_DEFAULT 0x0 +#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_OFFSET 0xc +#define GC_TRNG_INT_TEST_INTR_STAT_40_60_LSB 0x4 +#define GC_TRNG_INT_TEST_INTR_STAT_40_60_MASK 0x10 +#define GC_TRNG_INT_TEST_INTR_STAT_40_60_SIZE 0x1 +#define GC_TRNG_INT_TEST_INTR_STAT_40_60_DEFAULT 0x0 +#define GC_TRNG_INT_TEST_INTR_STAT_40_60_OFFSET 0xc +#define GC_TRNG_INT_TEST_INTR_STAT_30_70_LSB 0x5 +#define GC_TRNG_INT_TEST_INTR_STAT_30_70_MASK 0x20 +#define GC_TRNG_INT_TEST_INTR_STAT_30_70_SIZE 0x1 +#define GC_TRNG_INT_TEST_INTR_STAT_30_70_DEFAULT 0x0 +#define GC_TRNG_INT_TEST_INTR_STAT_30_70_OFFSET 0xc +#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_LSB 0x0 +#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_MASK 0xf +#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_SIZE 0x4 +#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_DEFAULT 0x0 +#define GC_TRNG_SLICE_MAX_LIMIT_LOWER_OFFSET 0x28 +#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_LSB 0x4 +#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_MASK 0xf0 +#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_SIZE 0x4 +#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_DEFAULT 0xf +#define GC_TRNG_SLICE_MAX_LIMIT_UPPER_OFFSET 0x28 +#define GC_TRNG_FSM_STATE_FSM_IDLE_LSB 0x0 +#define GC_TRNG_FSM_STATE_FSM_IDLE_MASK 0x1 +#define GC_TRNG_FSM_STATE_FSM_IDLE_SIZE 0x1 +#define GC_TRNG_FSM_STATE_FSM_IDLE_DEFAULT 0x1 +#define GC_TRNG_FSM_STATE_FSM_IDLE_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_FSM_WAIT_LSB 0x1 +#define GC_TRNG_FSM_STATE_FSM_WAIT_MASK 0x2 +#define GC_TRNG_FSM_STATE_FSM_WAIT_SIZE 0x1 +#define GC_TRNG_FSM_STATE_FSM_WAIT_DEFAULT 0x0 +#define GC_TRNG_FSM_STATE_FSM_WAIT_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_LSB 0x2 +#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_MASK 0x4 +#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_SIZE 0x1 +#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_DEFAULT 0x0 +#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_FSM_CAPTURE_LSB 0x3 +#define GC_TRNG_FSM_STATE_FSM_CAPTURE_MASK 0x8 +#define GC_TRNG_FSM_STATE_FSM_CAPTURE_SIZE 0x1 +#define GC_TRNG_FSM_STATE_FSM_CAPTURE_DEFAULT 0x0 +#define GC_TRNG_FSM_STATE_FSM_CAPTURE_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_LSB 0x4 +#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_MASK 0x10 +#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_SIZE 0x1 +#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_DEFAULT 0x0 +#define GC_TRNG_FSM_STATE_FSM_STAT_CALC_OFFSET 0x38 +#define GC_TRNG_FSM_STATE_FSM_FULL_LSB 0x5 +#define GC_TRNG_FSM_STATE_FSM_FULL_MASK 0x20 +#define GC_TRNG_FSM_STATE_FSM_FULL_SIZE 0x1 +#define GC_TRNG_FSM_STATE_FSM_FULL_DEFAULT 0x0 +#define GC_TRNG_FSM_STATE_FSM_FULL_OFFSET 0x38 +#define GC_TRNG_SLICE_RANGE_LOWER_LSB 0x0 +#define GC_TRNG_SLICE_RANGE_LOWER_MASK 0xf +#define GC_TRNG_SLICE_RANGE_LOWER_SIZE 0x4 +#define GC_TRNG_SLICE_RANGE_LOWER_DEFAULT 0x0 +#define GC_TRNG_SLICE_RANGE_LOWER_OFFSET 0x40 +#define GC_TRNG_SLICE_RANGE_UPPER_LSB 0x4 +#define GC_TRNG_SLICE_RANGE_UPPER_MASK 0xf0 +#define GC_TRNG_SLICE_RANGE_UPPER_SIZE 0x4 +#define GC_TRNG_SLICE_RANGE_UPPER_DEFAULT 0xf +#define GC_TRNG_SLICE_RANGE_UPPER_OFFSET 0x40 +#define GC_UART_CTRL_TX_LSB 0x0 +#define GC_UART_CTRL_TX_MASK 0x1 +#define GC_UART_CTRL_TX_SIZE 0x1 +#define GC_UART_CTRL_TX_DEFAULT 0x0 +#define GC_UART_CTRL_TX_OFFSET 0xc +#define GC_UART_CTRL_RX_LSB 0x1 +#define GC_UART_CTRL_RX_MASK 0x2 +#define GC_UART_CTRL_RX_SIZE 0x1 +#define GC_UART_CTRL_RX_DEFAULT 0x0 +#define GC_UART_CTRL_RX_OFFSET 0xc +#define GC_UART_CTRL_CTS_LSB 0x2 +#define GC_UART_CTRL_CTS_MASK 0x4 +#define GC_UART_CTRL_CTS_SIZE 0x1 +#define GC_UART_CTRL_CTS_DEFAULT 0x0 +#define GC_UART_CTRL_CTS_OFFSET 0xc +#define GC_UART_CTRL_RTS_LSB 0x3 +#define GC_UART_CTRL_RTS_MASK 0x8 +#define GC_UART_CTRL_RTS_SIZE 0x1 +#define GC_UART_CTRL_RTS_DEFAULT 0x0 +#define GC_UART_CTRL_RTS_OFFSET 0xc +#define GC_UART_CTRL_SLPBK_LSB 0x4 +#define GC_UART_CTRL_SLPBK_MASK 0x10 +#define GC_UART_CTRL_SLPBK_SIZE 0x1 +#define GC_UART_CTRL_SLPBK_DEFAULT 0x0 +#define GC_UART_CTRL_SLPBK_OFFSET 0xc +#define GC_UART_CTRL_LLPBK_LSB 0x5 +#define GC_UART_CTRL_LLPBK_MASK 0x20 +#define GC_UART_CTRL_LLPBK_SIZE 0x1 +#define GC_UART_CTRL_LLPBK_DEFAULT 0x0 +#define GC_UART_CTRL_LLPBK_OFFSET 0xc +#define GC_UART_CTRL_RCOS_LSB 0x6 +#define GC_UART_CTRL_RCOS_MASK 0x40 +#define GC_UART_CTRL_RCOS_SIZE 0x1 +#define GC_UART_CTRL_RCOS_DEFAULT 0x0 +#define GC_UART_CTRL_RCOS_OFFSET 0xc +#define GC_UART_CTRL_NF_LSB 0x7 +#define GC_UART_CTRL_NF_MASK 0x80 +#define GC_UART_CTRL_NF_SIZE 0x1 +#define GC_UART_CTRL_NF_DEFAULT 0x0 +#define GC_UART_CTRL_NF_OFFSET 0xc +#define GC_UART_ICTRL_TX_LSB 0x0 +#define GC_UART_ICTRL_TX_MASK 0x1 +#define GC_UART_ICTRL_TX_SIZE 0x1 +#define GC_UART_ICTRL_TX_DEFAULT 0x0 +#define GC_UART_ICTRL_TX_OFFSET 0x10 +#define GC_UART_ICTRL_RX_LSB 0x1 +#define GC_UART_ICTRL_RX_MASK 0x2 +#define GC_UART_ICTRL_RX_SIZE 0x1 +#define GC_UART_ICTRL_RX_DEFAULT 0x0 +#define GC_UART_ICTRL_RX_OFFSET 0x10 +#define GC_UART_ICTRL_TXO_LSB 0x2 +#define GC_UART_ICTRL_TXO_MASK 0x4 +#define GC_UART_ICTRL_TXO_SIZE 0x1 +#define GC_UART_ICTRL_TXO_DEFAULT 0x0 +#define GC_UART_ICTRL_TXO_OFFSET 0x10 +#define GC_UART_ICTRL_RXO_LSB 0x3 +#define GC_UART_ICTRL_RXO_MASK 0x8 +#define GC_UART_ICTRL_RXO_SIZE 0x1 +#define GC_UART_ICTRL_RXO_DEFAULT 0x0 +#define GC_UART_ICTRL_RXO_OFFSET 0x10 +#define GC_UART_ICTRL_RXF_LSB 0x4 +#define GC_UART_ICTRL_RXF_MASK 0x10 +#define GC_UART_ICTRL_RXF_SIZE 0x1 +#define GC_UART_ICTRL_RXF_DEFAULT 0x0 +#define GC_UART_ICTRL_RXF_OFFSET 0x10 +#define GC_UART_ICTRL_RXB_LSB 0x5 +#define GC_UART_ICTRL_RXB_MASK 0x20 +#define GC_UART_ICTRL_RXB_SIZE 0x1 +#define GC_UART_ICTRL_RXB_DEFAULT 0x0 +#define GC_UART_ICTRL_RXB_OFFSET 0x10 +#define GC_UART_ICTRL_RXBLVL_LSB 0x6 +#define GC_UART_ICTRL_RXBLVL_MASK 0xc0 +#define GC_UART_ICTRL_RXBLVL_SIZE 0x2 +#define GC_UART_ICTRL_RXBLVL_DEFAULT 0x0 +#define GC_UART_ICTRL_RXBLVL_OFFSET 0x10 +#define GC_UART_ICTRL_RXTO_LSB 0x8 +#define GC_UART_ICTRL_RXTO_MASK 0x100 +#define GC_UART_ICTRL_RXTO_SIZE 0x1 +#define GC_UART_ICTRL_RXTO_DEFAULT 0x0 +#define GC_UART_ICTRL_RXTO_OFFSET 0x10 +#define GC_UART_STATE_TX_LSB 0x0 +#define GC_UART_STATE_TX_MASK 0x1 +#define GC_UART_STATE_TX_SIZE 0x1 +#define GC_UART_STATE_TX_DEFAULT 0x0 +#define GC_UART_STATE_TX_OFFSET 0x14 +#define GC_UART_STATE_RX_LSB 0x1 +#define GC_UART_STATE_RX_MASK 0x2 +#define GC_UART_STATE_RX_SIZE 0x1 +#define GC_UART_STATE_RX_DEFAULT 0x0 +#define GC_UART_STATE_RX_OFFSET 0x14 +#define GC_UART_STATE_TXO_LSB 0x2 +#define GC_UART_STATE_TXO_MASK 0x4 +#define GC_UART_STATE_TXO_SIZE 0x1 +#define GC_UART_STATE_TXO_DEFAULT 0x0 +#define GC_UART_STATE_TXO_OFFSET 0x14 +#define GC_UART_STATE_RXO_LSB 0x3 +#define GC_UART_STATE_RXO_MASK 0x8 +#define GC_UART_STATE_RXO_SIZE 0x1 +#define GC_UART_STATE_RXO_DEFAULT 0x0 +#define GC_UART_STATE_RXO_OFFSET 0x14 +#define GC_UART_STATE_TXEMPTY_LSB 0x4 +#define GC_UART_STATE_TXEMPTY_MASK 0x10 +#define GC_UART_STATE_TXEMPTY_SIZE 0x1 +#define GC_UART_STATE_TXEMPTY_DEFAULT 0x1 +#define GC_UART_STATE_TXEMPTY_OFFSET 0x14 +#define GC_UART_STATE_TXIDLE_LSB 0x5 +#define GC_UART_STATE_TXIDLE_MASK 0x20 +#define GC_UART_STATE_TXIDLE_SIZE 0x1 +#define GC_UART_STATE_TXIDLE_DEFAULT 0x0 +#define GC_UART_STATE_TXIDLE_OFFSET 0x14 +#define GC_UART_STATE_RXIDLE_LSB 0x6 +#define GC_UART_STATE_RXIDLE_MASK 0x40 +#define GC_UART_STATE_RXIDLE_SIZE 0x1 +#define GC_UART_STATE_RXIDLE_DEFAULT 0x0 +#define GC_UART_STATE_RXIDLE_OFFSET 0x14 +#define GC_UART_STATE_RXEMPTY_LSB 0x7 +#define GC_UART_STATE_RXEMPTY_MASK 0x80 +#define GC_UART_STATE_RXEMPTY_SIZE 0x1 +#define GC_UART_STATE_RXEMPTY_DEFAULT 0x1 +#define GC_UART_STATE_RXEMPTY_OFFSET 0x14 +#define GC_UART_STATECLR_RES0_LSB 0x0 +#define GC_UART_STATECLR_RES0_MASK 0x1 +#define GC_UART_STATECLR_RES0_SIZE 0x1 +#define GC_UART_STATECLR_RES0_DEFAULT 0x0 +#define GC_UART_STATECLR_RES0_OFFSET 0x18 +#define GC_UART_STATECLR_RES1_LSB 0x1 +#define GC_UART_STATECLR_RES1_MASK 0x2 +#define GC_UART_STATECLR_RES1_SIZE 0x1 +#define GC_UART_STATECLR_RES1_DEFAULT 0x0 +#define GC_UART_STATECLR_RES1_OFFSET 0x18 +#define GC_UART_STATECLR_TXO_LSB 0x2 +#define GC_UART_STATECLR_TXO_MASK 0x4 +#define GC_UART_STATECLR_TXO_SIZE 0x1 +#define GC_UART_STATECLR_TXO_DEFAULT 0x0 +#define GC_UART_STATECLR_TXO_OFFSET 0x18 +#define GC_UART_STATECLR_RXO_LSB 0x3 +#define GC_UART_STATECLR_RXO_MASK 0x8 +#define GC_UART_STATECLR_RXO_SIZE 0x1 +#define GC_UART_STATECLR_RXO_DEFAULT 0x0 +#define GC_UART_STATECLR_RXO_OFFSET 0x18 +#define GC_UART_ISTATE_TX_LSB 0x0 +#define GC_UART_ISTATE_TX_MASK 0x1 +#define GC_UART_ISTATE_TX_SIZE 0x1 +#define GC_UART_ISTATE_TX_DEFAULT 0x0 +#define GC_UART_ISTATE_TX_OFFSET 0x1c +#define GC_UART_ISTATE_RX_LSB 0x1 +#define GC_UART_ISTATE_RX_MASK 0x2 +#define GC_UART_ISTATE_RX_SIZE 0x1 +#define GC_UART_ISTATE_RX_DEFAULT 0x0 +#define GC_UART_ISTATE_RX_OFFSET 0x1c +#define GC_UART_ISTATE_TXO_LSB 0x2 +#define GC_UART_ISTATE_TXO_MASK 0x4 +#define GC_UART_ISTATE_TXO_SIZE 0x1 +#define GC_UART_ISTATE_TXO_DEFAULT 0x0 +#define GC_UART_ISTATE_TXO_OFFSET 0x1c +#define GC_UART_ISTATE_RXO_LSB 0x3 +#define GC_UART_ISTATE_RXO_MASK 0x8 +#define GC_UART_ISTATE_RXO_SIZE 0x1 +#define GC_UART_ISTATE_RXO_DEFAULT 0x0 +#define GC_UART_ISTATE_RXO_OFFSET 0x1c +#define GC_UART_ISTATE_RXF_LSB 0x4 +#define GC_UART_ISTATE_RXF_MASK 0x10 +#define GC_UART_ISTATE_RXF_SIZE 0x1 +#define GC_UART_ISTATE_RXF_DEFAULT 0x0 +#define GC_UART_ISTATE_RXF_OFFSET 0x1c +#define GC_UART_ISTATE_RXB_LSB 0x5 +#define GC_UART_ISTATE_RXB_MASK 0x20 +#define GC_UART_ISTATE_RXB_SIZE 0x1 +#define GC_UART_ISTATE_RXB_DEFAULT 0x0 +#define GC_UART_ISTATE_RXB_OFFSET 0x1c +#define GC_UART_ISTATE_RXTO_LSB 0x6 +#define GC_UART_ISTATE_RXTO_MASK 0x40 +#define GC_UART_ISTATE_RXTO_SIZE 0x1 +#define GC_UART_ISTATE_RXTO_DEFAULT 0x0 +#define GC_UART_ISTATE_RXTO_OFFSET 0x1c +#define GC_UART_ISTATECLR_TX_LSB 0x0 +#define GC_UART_ISTATECLR_TX_MASK 0x1 +#define GC_UART_ISTATECLR_TX_SIZE 0x1 +#define GC_UART_ISTATECLR_TX_DEFAULT 0x0 +#define GC_UART_ISTATECLR_TX_OFFSET 0x20 +#define GC_UART_ISTATECLR_RX_LSB 0x1 +#define GC_UART_ISTATECLR_RX_MASK 0x2 +#define GC_UART_ISTATECLR_RX_SIZE 0x1 +#define GC_UART_ISTATECLR_RX_DEFAULT 0x0 +#define GC_UART_ISTATECLR_RX_OFFSET 0x20 +#define GC_UART_ISTATECLR_TXO_LSB 0x2 +#define GC_UART_ISTATECLR_TXO_MASK 0x4 +#define GC_UART_ISTATECLR_TXO_SIZE 0x1 +#define GC_UART_ISTATECLR_TXO_DEFAULT 0x0 +#define GC_UART_ISTATECLR_TXO_OFFSET 0x20 +#define GC_UART_ISTATECLR_RXO_LSB 0x3 +#define GC_UART_ISTATECLR_RXO_MASK 0x8 +#define GC_UART_ISTATECLR_RXO_SIZE 0x1 +#define GC_UART_ISTATECLR_RXO_DEFAULT 0x0 +#define GC_UART_ISTATECLR_RXO_OFFSET 0x20 +#define GC_UART_ISTATECLR_RXF_LSB 0x4 +#define GC_UART_ISTATECLR_RXF_MASK 0x10 +#define GC_UART_ISTATECLR_RXF_SIZE 0x1 +#define GC_UART_ISTATECLR_RXF_DEFAULT 0x0 +#define GC_UART_ISTATECLR_RXF_OFFSET 0x20 +#define GC_UART_ISTATECLR_RXB_LSB 0x5 +#define GC_UART_ISTATECLR_RXB_MASK 0x20 +#define GC_UART_ISTATECLR_RXB_SIZE 0x1 +#define GC_UART_ISTATECLR_RXB_DEFAULT 0x0 +#define GC_UART_ISTATECLR_RXB_OFFSET 0x20 +#define GC_UART_ISTATECLR_RXTO_LSB 0x6 +#define GC_UART_ISTATECLR_RXTO_MASK 0x40 +#define GC_UART_ISTATECLR_RXTO_SIZE 0x1 +#define GC_UART_ISTATECLR_RXTO_DEFAULT 0x0 +#define GC_UART_ISTATECLR_RXTO_OFFSET 0x20 +#define GC_UART_FIFO_RXRST_LSB 0x0 +#define GC_UART_FIFO_RXRST_MASK 0x1 +#define GC_UART_FIFO_RXRST_SIZE 0x1 +#define GC_UART_FIFO_RXRST_DEFAULT 0x0 +#define GC_UART_FIFO_RXRST_OFFSET 0x24 +#define GC_UART_FIFO_TXRST_LSB 0x1 +#define GC_UART_FIFO_TXRST_MASK 0x2 +#define GC_UART_FIFO_TXRST_SIZE 0x1 +#define GC_UART_FIFO_TXRST_DEFAULT 0x0 +#define GC_UART_FIFO_TXRST_OFFSET 0x24 +#define GC_UART_FIFO_RXILVL_LSB 0x2 +#define GC_UART_FIFO_RXILVL_MASK 0x1c +#define GC_UART_FIFO_RXILVL_SIZE 0x3 +#define GC_UART_FIFO_RXILVL_DEFAULT 0x0 +#define GC_UART_FIFO_RXILVL_OFFSET 0x24 +#define GC_UART_FIFO_TXILVL_LSB 0x5 +#define GC_UART_FIFO_TXILVL_MASK 0x60 +#define GC_UART_FIFO_TXILVL_SIZE 0x2 +#define GC_UART_FIFO_TXILVL_DEFAULT 0x0 +#define GC_UART_FIFO_TXILVL_OFFSET 0x24 +#define GC_UART_RFIFO_TXLVL_LSB 0x0 +#define GC_UART_RFIFO_TXLVL_MASK 0x3f +#define GC_UART_RFIFO_TXLVL_SIZE 0x6 +#define GC_UART_RFIFO_TXLVL_DEFAULT 0x0 +#define GC_UART_RFIFO_TXLVL_OFFSET 0x28 +#define GC_UART_RFIFO_RXLVL_LSB 0x6 +#define GC_UART_RFIFO_RXLVL_MASK 0xfc0 +#define GC_UART_RFIFO_RXLVL_SIZE 0x6 +#define GC_UART_RFIFO_RXLVL_DEFAULT 0x0 +#define GC_UART_RFIFO_RXLVL_OFFSET 0x28 +#define GC_UART_OVRD_TXEN_LSB 0x0 +#define GC_UART_OVRD_TXEN_MASK 0x1 +#define GC_UART_OVRD_TXEN_SIZE 0x1 +#define GC_UART_OVRD_TXEN_DEFAULT 0x0 +#define GC_UART_OVRD_TXEN_OFFSET 0x2c +#define GC_UART_OVRD_TXVAL_LSB 0x1 +#define GC_UART_OVRD_TXVAL_MASK 0x2 +#define GC_UART_OVRD_TXVAL_SIZE 0x1 +#define GC_UART_OVRD_TXVAL_DEFAULT 0x0 +#define GC_UART_OVRD_TXVAL_OFFSET 0x2c +#define GC_UART_OVRD_RTSEN_LSB 0x2 +#define GC_UART_OVRD_RTSEN_MASK 0x4 +#define GC_UART_OVRD_RTSEN_SIZE 0x1 +#define GC_UART_OVRD_RTSEN_DEFAULT 0x0 +#define GC_UART_OVRD_RTSEN_OFFSET 0x2c +#define GC_UART_OVRD_RTSVAL_LSB 0x3 +#define GC_UART_OVRD_RTSVAL_MASK 0x8 +#define GC_UART_OVRD_RTSVAL_SIZE 0x1 +#define GC_UART_OVRD_RTSVAL_DEFAULT 0x0 +#define GC_UART_OVRD_RTSVAL_OFFSET 0x2c +#define GC_UART_VAL_RX_LSB 0x0 +#define GC_UART_VAL_RX_MASK 0xffff +#define GC_UART_VAL_RX_SIZE 0x10 +#define GC_UART_VAL_RX_DEFAULT 0x0 +#define GC_UART_VAL_RX_OFFSET 0x30 +#define GC_UART_VAL_CTS_LSB 0x10 +#define GC_UART_VAL_CTS_MASK 0xffff0000 +#define GC_UART_VAL_CTS_SIZE 0x10 +#define GC_UART_VAL_CTS_DEFAULT 0x0 +#define GC_UART_VAL_CTS_OFFSET 0x30 +#define GC_UART_RXTO_EN_LSB 0x0 +#define GC_UART_RXTO_EN_MASK 0x1 +#define GC_UART_RXTO_EN_SIZE 0x1 +#define GC_UART_RXTO_EN_DEFAULT 0x0 +#define GC_UART_RXTO_EN_OFFSET 0x34 +#define GC_UART_RXTO_VAL_LSB 0x1 +#define GC_UART_RXTO_VAL_MASK 0x1fffffe +#define GC_UART_RXTO_VAL_SIZE 0x18 +#define GC_UART_RXTO_VAL_DEFAULT 0x0 +#define GC_UART_RXTO_VAL_OFFSET 0x34 +#define GC_UART_ITOP_TX_LSB 0x0 +#define GC_UART_ITOP_TX_MASK 0x1 +#define GC_UART_ITOP_TX_SIZE 0x1 +#define GC_UART_ITOP_TX_DEFAULT 0x0 +#define GC_UART_ITOP_TX_OFFSET 0xf04 +#define GC_UART_ITOP_RX_LSB 0x1 +#define GC_UART_ITOP_RX_MASK 0x2 +#define GC_UART_ITOP_RX_SIZE 0x1 +#define GC_UART_ITOP_RX_DEFAULT 0x0 +#define GC_UART_ITOP_RX_OFFSET 0xf04 +#define GC_UART_ITOP_TXO_LSB 0x2 +#define GC_UART_ITOP_TXO_MASK 0x4 +#define GC_UART_ITOP_TXO_SIZE 0x1 +#define GC_UART_ITOP_TXO_DEFAULT 0x0 +#define GC_UART_ITOP_TXO_OFFSET 0xf04 +#define GC_UART_ITOP_RXO_LSB 0x3 +#define GC_UART_ITOP_RXO_MASK 0x8 +#define GC_UART_ITOP_RXO_SIZE 0x1 +#define GC_UART_ITOP_RXO_DEFAULT 0x0 +#define GC_UART_ITOP_RXO_OFFSET 0xf04 +#define GC_UART_ITOP_RXF_LSB 0x4 +#define GC_UART_ITOP_RXF_MASK 0x10 +#define GC_UART_ITOP_RXF_SIZE 0x1 +#define GC_UART_ITOP_RXF_DEFAULT 0x0 +#define GC_UART_ITOP_RXF_OFFSET 0xf04 +#define GC_UART_ITOP_RXB_LSB 0x5 +#define GC_UART_ITOP_RXB_MASK 0x20 +#define GC_UART_ITOP_RXB_SIZE 0x1 +#define GC_UART_ITOP_RXB_DEFAULT 0x0 +#define GC_UART_ITOP_RXB_OFFSET 0xf04 +#define GC_UART_ITOP_RXTO_LSB 0x6 +#define GC_UART_ITOP_RXTO_MASK 0x40 +#define GC_UART_ITOP_RXTO_SIZE 0x1 +#define GC_UART_ITOP_RXTO_DEFAULT 0x0 +#define GC_UART_ITOP_RXTO_OFFSET 0xf04 +#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6 +#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40 +#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1 +#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0 +#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7 +#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80 +#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1 +#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0 +#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10 +#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000 +#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1 +#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0 +#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0 +#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13 +#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000 +#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1 +#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0 +#define GC_USB_GOTGCTL_OTGVER_LSB 0x14 +#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000 +#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1 +#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0 +#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0 +#define GC_USB_GOTGCTL_CURMOD_LSB 0x15 +#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000 +#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1 +#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0 +#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0 +#define GC_USB_GOTGINT_SESENDDET_LSB 0x2 +#define GC_USB_GOTGINT_SESENDDET_MASK 0x4 +#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1 +#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0 +#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4 +#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11 +#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000 +#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1 +#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0 +#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4 +#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12 +#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000 +#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1 +#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0 +#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4 +#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0 +#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1 +#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1 +#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0 +#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8 +#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1 +#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e +#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4 +#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0 +#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8 +#define GC_USB_GAHBCFG_DMAEN_LSB 0x5 +#define GC_USB_GAHBCFG_DMAEN_MASK 0x20 +#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1 +#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0 +#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8 +#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15 +#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000 +#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1 +#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0 +#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8 +#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17 +#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000 +#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1 +#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0 +#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8 +#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0 +#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7 +#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3 +#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc +#define GC_USB_GUSBCFG_PHYIF_LSB 0x3 +#define GC_USB_GUSBCFG_PHYIF_MASK 0x8 +#define GC_USB_GUSBCFG_PHYIF_SIZE 0x1 +#define GC_USB_GUSBCFG_PHYIF_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PHYIF_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB 0x4 +#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_MASK 0x10 +#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_OFFSET 0xc +#define GC_USB_GUSBCFG_FSINTF_LSB 0x5 +#define GC_USB_GUSBCFG_FSINTF_MASK 0x20 +#define GC_USB_GUSBCFG_FSINTF_SIZE 0x1 +#define GC_USB_GUSBCFG_FSINTF_DEFAULT 0x0 +#define GC_USB_GUSBCFG_FSINTF_OFFSET 0xc +#define GC_USB_GUSBCFG_PHYSEL_LSB 0x6 +#define GC_USB_GUSBCFG_PHYSEL_MASK 0x40 +#define GC_USB_GUSBCFG_PHYSEL_SIZE 0x1 +#define GC_USB_GUSBCFG_PHYSEL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PHYSEL_OFFSET 0xc +#define GC_USB_GUSBCFG_DDRSEL_LSB 0x7 +#define GC_USB_GUSBCFG_DDRSEL_MASK 0x80 +#define GC_USB_GUSBCFG_DDRSEL_SIZE 0x1 +#define GC_USB_GUSBCFG_DDRSEL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_DDRSEL_OFFSET 0xc +#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa +#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00 +#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4 +#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0 +#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 0xf +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIFSLS_LSB 0x11 +#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000 +#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 0x12 +#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000 +#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 0x13 +#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000 +#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc +#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 0x16 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc +#define GC_USB_GUSBCFG_IC_USBCAP_LSB 0x1a +#define GC_USB_GUSBCFG_IC_USBCAP_MASK 0x4000000 +#define GC_USB_GUSBCFG_IC_USBCAP_SIZE 0x1 +#define GC_USB_GUSBCFG_IC_USBCAP_DEFAULT 0x0 +#define GC_USB_GUSBCFG_IC_USBCAP_OFFSET 0xc +#define GC_USB_GUSBCFG_TXENDDELAY_LSB 0x1c +#define GC_USB_GUSBCFG_TXENDDELAY_MASK 0x10000000 +#define GC_USB_GUSBCFG_TXENDDELAY_SIZE 0x1 +#define GC_USB_GUSBCFG_TXENDDELAY_DEFAULT 0x0 +#define GC_USB_GUSBCFG_TXENDDELAY_OFFSET 0xc +#define GC_USB_GUSBCFG_CORRUPTTXPKT_LSB 0x1f +#define GC_USB_GUSBCFG_CORRUPTTXPKT_MASK 0x80000000 +#define GC_USB_GUSBCFG_CORRUPTTXPKT_SIZE 0x1 +#define GC_USB_GUSBCFG_CORRUPTTXPKT_DEFAULT 0x0 +#define GC_USB_GUSBCFG_CORRUPTTXPKT_OFFSET 0xc +#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0 +#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1 +#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1 +#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0 +#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10 +#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1 +#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2 +#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1 +#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0 +#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10 +#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4 +#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10 +#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1 +#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0 +#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10 +#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5 +#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20 +#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1 +#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0 +#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10 +#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6 +#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0 +#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5 +#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0 +#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10 +#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e +#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000 +#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1 +#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0 +#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10 +#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f +#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000 +#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1 +#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0 +#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10 +#define GC_USB_GINTSTS_CURMOD_LSB 0x0 +#define GC_USB_GINTSTS_CURMOD_MASK 0x1 +#define GC_USB_GINTSTS_CURMOD_SIZE 0x1 +#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0 +#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14 +#define GC_USB_GINTSTS_MODEMIS_LSB 0x1 +#define GC_USB_GINTSTS_MODEMIS_MASK 0x2 +#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1 +#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0 +#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14 +#define GC_USB_GINTSTS_OTGINT_LSB 0x2 +#define GC_USB_GINTSTS_OTGINT_MASK 0x4 +#define GC_USB_GINTSTS_OTGINT_SIZE 0x1 +#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14 +#define GC_USB_GINTSTS_SOF_LSB 0x3 +#define GC_USB_GINTSTS_SOF_MASK 0x8 +#define GC_USB_GINTSTS_SOF_SIZE 0x1 +#define GC_USB_GINTSTS_SOF_DEFAULT 0x0 +#define GC_USB_GINTSTS_SOF_OFFSET 0x14 +#define GC_USB_GINTSTS_RXFLVL_LSB 0x4 +#define GC_USB_GINTSTS_RXFLVL_MASK 0x10 +#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1 +#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0 +#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14 +#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6 +#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40 +#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1 +#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0 +#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14 +#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7 +#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80 +#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1 +#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0 +#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14 +#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa +#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400 +#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_USBSUSP_LSB 0xb +#define GC_USB_GINTSTS_USBSUSP_MASK 0x800 +#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_USBRST_LSB 0xc +#define GC_USB_GINTSTS_USBRST_MASK 0x1000 +#define GC_USB_GINTSTS_USBRST_SIZE 0x1 +#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0 +#define GC_USB_GINTSTS_USBRST_OFFSET 0x14 +#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd +#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000 +#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1 +#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0 +#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14 +#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe +#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000 +#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1 +#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0 +#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14 +#define GC_USB_GINTSTS_EOPF_LSB 0xf +#define GC_USB_GINTSTS_EOPF_MASK 0x8000 +#define GC_USB_GINTSTS_EOPF_SIZE 0x1 +#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0 +#define GC_USB_GINTSTS_EOPF_OFFSET 0x14 +#define GC_USB_GINTSTS_EPMIS_LSB 0x11 +#define GC_USB_GINTSTS_EPMIS_MASK 0x20000 +#define GC_USB_GINTSTS_EPMIS_SIZE 0x1 +#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0 +#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14 +#define GC_USB_GINTSTS_IEPINT_LSB 0x12 +#define GC_USB_GINTSTS_IEPINT_MASK 0x40000 +#define GC_USB_GINTSTS_IEPINT_SIZE 0x1 +#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14 +#define GC_USB_GINTSTS_OEPINT_LSB 0x13 +#define GC_USB_GINTSTS_OEPINT_MASK 0x80000 +#define GC_USB_GINTSTS_OEPINT_SIZE 0x1 +#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14 +#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14 +#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000 +#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1 +#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0 +#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14 +#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15 +#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000 +#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1 +#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0 +#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14 +#define GC_USB_GINTSTS_FETSUSP_LSB 0x16 +#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000 +#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_RESETDET_LSB 0x17 +#define GC_USB_GINTSTS_RESETDET_MASK 0x800000 +#define GC_USB_GINTSTS_RESETDET_SIZE 0x1 +#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0 +#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14 +#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c +#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000 +#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1 +#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0 +#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14 +#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e +#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000 +#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1 +#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14 +#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f +#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000 +#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1 +#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14 +#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1 +#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2 +#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1 +#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2 +#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4 +#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_SOFMSK_LSB 0x3 +#define GC_USB_GINTMSK_SOFMSK_MASK 0x8 +#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4 +#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10 +#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1 +#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6 +#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40 +#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa +#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400 +#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb +#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800 +#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc +#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000 +#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd +#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000 +#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe +#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf +#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000 +#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11 +#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000 +#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1 +#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12 +#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000 +#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13 +#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000 +#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14 +#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000 +#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1 +#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16 +#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000 +#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17 +#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000 +#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1 +#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d +#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000 +#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e +#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000 +#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f +#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000 +#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18 +#define GC_USB_GRXSTSR_CHNUM_LSB 0x0 +#define GC_USB_GRXSTSR_CHNUM_MASK 0xf +#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4 +#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0 +#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c +#define GC_USB_GRXSTSR_BCNT_LSB 0x4 +#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0 +#define GC_USB_GRXSTSR_BCNT_SIZE 0xb +#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0 +#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c +#define GC_USB_GRXSTSR_DPID_LSB 0xf +#define GC_USB_GRXSTSR_DPID_MASK 0x18000 +#define GC_USB_GRXSTSR_DPID_SIZE 0x2 +#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0 +#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c +#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11 +#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000 +#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4 +#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0 +#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c +#define GC_USB_GRXSTSR_FN_LSB 0x15 +#define GC_USB_GRXSTSR_FN_MASK 0x1e00000 +#define GC_USB_GRXSTSR_FN_SIZE 0x4 +#define GC_USB_GRXSTSR_FN_DEFAULT 0x0 +#define GC_USB_GRXSTSR_FN_OFFSET 0x1c +#define GC_USB_GRXSTSP_CHNUM_LSB 0x0 +#define GC_USB_GRXSTSP_CHNUM_MASK 0xf +#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4 +#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0 +#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20 +#define GC_USB_GRXSTSP_BCNT_LSB 0x4 +#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0 +#define GC_USB_GRXSTSP_BCNT_SIZE 0xb +#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0 +#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20 +#define GC_USB_GRXSTSP_DPID_LSB 0xf +#define GC_USB_GRXSTSP_DPID_MASK 0x18000 +#define GC_USB_GRXSTSP_DPID_SIZE 0x2 +#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0 +#define GC_USB_GRXSTSP_DPID_OFFSET 0x20 +#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11 +#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000 +#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4 +#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0 +#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20 +#define GC_USB_GRXSTSP_FN_LSB 0x15 +#define GC_USB_GRXSTSP_FN_MASK 0x1e00000 +#define GC_USB_GRXSTSP_FN_SIZE 0x4 +#define GC_USB_GRXSTSP_FN_DEFAULT 0x0 +#define GC_USB_GRXSTSP_FN_OFFSET 0x20 +#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0 +#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff +#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb +#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0 +#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28 +#define GC_USB_GGPIO_GPI_LSB 0x0 +#define GC_USB_GGPIO_GPI_MASK 0xffff +#define GC_USB_GGPIO_GPI_SIZE 0x10 +#define GC_USB_GGPIO_GPI_DEFAULT 0x0 +#define GC_USB_GGPIO_GPI_OFFSET 0x38 +#define GC_USB_GGPIO_GPO_LSB 0x10 +#define GC_USB_GGPIO_GPO_MASK 0xffff0000 +#define GC_USB_GGPIO_GPO_SIZE 0x10 +#define GC_USB_GGPIO_GPO_DEFAULT 0x0 +#define GC_USB_GGPIO_GPO_OFFSET 0x38 +#define GC_USB_GUID_GUID_LSB 0x0 +#define GC_USB_GUID_GUID_MASK 0xffffffff +#define GC_USB_GUID_GUID_SIZE 0x20 +#define GC_USB_GUID_GUID_DEFAULT 0x0 +#define GC_USB_GUID_GUID_OFFSET 0x3c +#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0 +#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff +#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20 +#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0 +#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40 +#define GC_USB_GHWCFG1_EPDIR_LSB 0x0 +#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff +#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20 +#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0 +#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44 +#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0 +#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7 +#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3 +#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48 +#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3 +#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18 +#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2 +#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48 +#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5 +#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20 +#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1 +#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48 +#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6 +#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0 +#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2 +#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48 +#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8 +#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300 +#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2 +#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48 +#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa +#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00 +#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4 +#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48 +#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe +#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000 +#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4 +#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48 +#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12 +#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000 +#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48 +#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16 +#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000 +#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2 +#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18 +#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000 +#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2 +#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a +#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000 +#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5 +#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c +#define GC_USB_GHWCFG3_OTGEN_LSB 0x7 +#define GC_USB_GHWCFG3_OTGEN_MASK 0x80 +#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1 +#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c +#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8 +#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100 +#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1 +#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0 +#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c +#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9 +#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200 +#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1 +#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c +#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa +#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400 +#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1 +#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c +#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb +#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800 +#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1 +#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c +#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc +#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000 +#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c +#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd +#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000 +#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1 +#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c +#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe +#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000 +#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c +#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf +#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000 +#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1 +#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c +#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10 +#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000 +#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10 +#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4 +#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10 +#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1 +#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0 +#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50 +#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5 +#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20 +#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1 +#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0 +#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50 +#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6 +#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40 +#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1 +#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0 +#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe +#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50 +#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10 +#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000 +#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14 +#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000 +#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16 +#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000 +#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17 +#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000 +#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18 +#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000 +#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19 +#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000 +#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1 +#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50 +#define GC_USB_GHWCFG4_INEPS_LSB 0x1a +#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000 +#define GC_USB_GHWCFG4_INEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e +#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000 +#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1 +#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50 +#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f +#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000 +#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1 +#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff +#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c +#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c +#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c +#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c +#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c +#define GC_USB_DCFG_DEVSPD_LSB 0x0 +#define GC_USB_DCFG_DEVSPD_MASK 0x3 +#define GC_USB_DCFG_DEVSPD_SIZE 0x2 +#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0 +#define GC_USB_DCFG_DEVSPD_OFFSET 0x800 +#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2 +#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4 +#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1 +#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0 +#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800 +#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3 +#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8 +#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1 +#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0 +#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800 +#define GC_USB_DCFG_DEVADDR_LSB 0x4 +#define GC_USB_DCFG_DEVADDR_MASK 0x7f0 +#define GC_USB_DCFG_DEVADDR_SIZE 0x7 +#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0 +#define GC_USB_DCFG_DEVADDR_OFFSET 0x800 +#define GC_USB_DCFG_PERFRINT_LSB 0xb +#define GC_USB_DCFG_PERFRINT_MASK 0x1800 +#define GC_USB_DCFG_PERFRINT_SIZE 0x2 +#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0 +#define GC_USB_DCFG_PERFRINT_OFFSET 0x800 +#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd +#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000 +#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1 +#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0 +#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800 +#define GC_USB_DCFG_XCVRDLY_LSB 0xe +#define GC_USB_DCFG_XCVRDLY_MASK 0x4000 +#define GC_USB_DCFG_XCVRDLY_SIZE 0x1 +#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0 +#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800 +#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf +#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000 +#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1 +#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0 +#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800 +#define GC_USB_DCFG_DESCDMA_LSB 0x17 +#define GC_USB_DCFG_DESCDMA_MASK 0x800000 +#define GC_USB_DCFG_DESCDMA_SIZE 0x1 +#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0 +#define GC_USB_DCFG_DESCDMA_OFFSET 0x800 +#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18 +#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000 +#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2 +#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0 +#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800 +#define GC_USB_DCFG_RESVALID_LSB 0x1a +#define GC_USB_DCFG_RESVALID_MASK 0xfc000000 +#define GC_USB_DCFG_RESVALID_SIZE 0x6 +#define GC_USB_DCFG_RESVALID_DEFAULT 0x2 +#define GC_USB_DCFG_RESVALID_OFFSET 0x800 +#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0 +#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1 +#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1 +#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0 +#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804 +#define GC_USB_DCTL_SFTDISCON_LSB 0x1 +#define GC_USB_DCTL_SFTDISCON_MASK 0x2 +#define GC_USB_DCTL_SFTDISCON_SIZE 0x1 +#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0 +#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804 +#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2 +#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4 +#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1 +#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0 +#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804 +#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3 +#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8 +#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1 +#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0 +#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804 +#define GC_USB_DCTL_TSTCTL_LSB 0x4 +#define GC_USB_DCTL_TSTCTL_MASK 0x70 +#define GC_USB_DCTL_TSTCTL_SIZE 0x3 +#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0 +#define GC_USB_DCTL_TSTCTL_OFFSET 0x804 +#define GC_USB_DCTL_SGNPINNAK_LSB 0x7 +#define GC_USB_DCTL_SGNPINNAK_MASK 0x80 +#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1 +#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0 +#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804 +#define GC_USB_DCTL_CGNPINNAK_LSB 0x8 +#define GC_USB_DCTL_CGNPINNAK_MASK 0x100 +#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1 +#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0 +#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804 +#define GC_USB_DCTL_SGOUTNAK_LSB 0x9 +#define GC_USB_DCTL_SGOUTNAK_MASK 0x200 +#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1 +#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0 +#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804 +#define GC_USB_DCTL_CGOUTNAK_LSB 0xa +#define GC_USB_DCTL_CGOUTNAK_MASK 0x400 +#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1 +#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0 +#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804 +#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb +#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800 +#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1 +#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0 +#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804 +#define GC_USB_DCTL_GMC_LSB 0xd +#define GC_USB_DCTL_GMC_MASK 0x6000 +#define GC_USB_DCTL_GMC_SIZE 0x2 +#define GC_USB_DCTL_GMC_DEFAULT 0x0 +#define GC_USB_DCTL_GMC_OFFSET 0x804 +#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf +#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000 +#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1 +#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0 +#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804 +#define GC_USB_DCTL_NAKONBBLE_LSB 0x10 +#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000 +#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1 +#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0 +#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804 +#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11 +#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000 +#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1 +#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0 +#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804 +#define GC_USB_DSTS_SUSPSTS_LSB 0x0 +#define GC_USB_DSTS_SUSPSTS_MASK 0x1 +#define GC_USB_DSTS_SUSPSTS_SIZE 0x1 +#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0 +#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808 +#define GC_USB_DSTS_ENUMSPD_LSB 0x1 +#define GC_USB_DSTS_ENUMSPD_MASK 0x6 +#define GC_USB_DSTS_ENUMSPD_SIZE 0x2 +#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0 +#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808 +#define GC_USB_DSTS_ERRTICERR_LSB 0x3 +#define GC_USB_DSTS_ERRTICERR_MASK 0x8 +#define GC_USB_DSTS_ERRTICERR_SIZE 0x1 +#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0 +#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808 +#define GC_USB_DSTS_SOFFN_LSB 0x8 +#define GC_USB_DSTS_SOFFN_MASK 0x3fff00 +#define GC_USB_DSTS_SOFFN_SIZE 0xe +#define GC_USB_DSTS_SOFFN_DEFAULT 0x0 +#define GC_USB_DSTS_SOFFN_OFFSET 0x808 +#define GC_USB_DSTS_DEVLNSTS_LSB 0x16 +#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000 +#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2 +#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0 +#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1 +#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2 +#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2 +#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4 +#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3 +#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8 +#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9 +#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200 +#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd +#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000 +#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1 +#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2 +#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2 +#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4 +#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3 +#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8 +#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc +#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000 +#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd +#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000 +#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe +#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000 +#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814 +#define GC_USB_DAINT_INEPINT0_LSB 0x0 +#define GC_USB_DAINT_INEPINT0_MASK 0x1 +#define GC_USB_DAINT_INEPINT0_SIZE 0x1 +#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT0_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT1_LSB 0x1 +#define GC_USB_DAINT_INEPINT1_MASK 0x2 +#define GC_USB_DAINT_INEPINT1_SIZE 0x1 +#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT1_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT2_LSB 0x2 +#define GC_USB_DAINT_INEPINT2_MASK 0x4 +#define GC_USB_DAINT_INEPINT2_SIZE 0x1 +#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT2_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT3_LSB 0x3 +#define GC_USB_DAINT_INEPINT3_MASK 0x8 +#define GC_USB_DAINT_INEPINT3_SIZE 0x1 +#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT3_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT4_LSB 0x4 +#define GC_USB_DAINT_INEPINT4_MASK 0x10 +#define GC_USB_DAINT_INEPINT4_SIZE 0x1 +#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT4_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT5_LSB 0x5 +#define GC_USB_DAINT_INEPINT5_MASK 0x20 +#define GC_USB_DAINT_INEPINT5_SIZE 0x1 +#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT5_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT6_LSB 0x6 +#define GC_USB_DAINT_INEPINT6_MASK 0x40 +#define GC_USB_DAINT_INEPINT6_SIZE 0x1 +#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT6_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT7_LSB 0x7 +#define GC_USB_DAINT_INEPINT7_MASK 0x80 +#define GC_USB_DAINT_INEPINT7_SIZE 0x1 +#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT7_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT8_LSB 0x8 +#define GC_USB_DAINT_INEPINT8_MASK 0x100 +#define GC_USB_DAINT_INEPINT8_SIZE 0x1 +#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT8_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT9_LSB 0x9 +#define GC_USB_DAINT_INEPINT9_MASK 0x200 +#define GC_USB_DAINT_INEPINT9_SIZE 0x1 +#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT9_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT10_LSB 0xa +#define GC_USB_DAINT_INEPINT10_MASK 0x400 +#define GC_USB_DAINT_INEPINT10_SIZE 0x1 +#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT10_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT11_LSB 0xb +#define GC_USB_DAINT_INEPINT11_MASK 0x800 +#define GC_USB_DAINT_INEPINT11_SIZE 0x1 +#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT11_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT12_LSB 0xc +#define GC_USB_DAINT_INEPINT12_MASK 0x1000 +#define GC_USB_DAINT_INEPINT12_SIZE 0x1 +#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT12_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT13_LSB 0xd +#define GC_USB_DAINT_INEPINT13_MASK 0x2000 +#define GC_USB_DAINT_INEPINT13_SIZE 0x1 +#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT13_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT14_LSB 0xe +#define GC_USB_DAINT_INEPINT14_MASK 0x4000 +#define GC_USB_DAINT_INEPINT14_SIZE 0x1 +#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT14_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT15_LSB 0xf +#define GC_USB_DAINT_INEPINT15_MASK 0x8000 +#define GC_USB_DAINT_INEPINT15_SIZE 0x1 +#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT15_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT0_LSB 0x10 +#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000 +#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT1_LSB 0x11 +#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000 +#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT2_LSB 0x12 +#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000 +#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT3_LSB 0x13 +#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000 +#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT4_LSB 0x14 +#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000 +#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT5_LSB 0x15 +#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000 +#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT6_LSB 0x16 +#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000 +#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT7_LSB 0x17 +#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000 +#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT8_LSB 0x18 +#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000 +#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT9_LSB 0x19 +#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000 +#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a +#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000 +#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b +#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000 +#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c +#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000 +#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d +#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000 +#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e +#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000 +#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f +#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000 +#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818 +#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0 +#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1 +#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1 +#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2 +#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2 +#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4 +#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3 +#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8 +#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4 +#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10 +#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5 +#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20 +#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6 +#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40 +#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7 +#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80 +#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8 +#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100 +#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9 +#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200 +#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa +#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400 +#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb +#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800 +#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc +#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000 +#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd +#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000 +#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe +#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000 +#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf +#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000 +#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10 +#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000 +#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11 +#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000 +#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12 +#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000 +#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13 +#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000 +#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14 +#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000 +#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15 +#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000 +#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16 +#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000 +#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17 +#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000 +#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18 +#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000 +#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19 +#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000 +#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a +#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000 +#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b +#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000 +#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c +#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000 +#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d +#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000 +#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e +#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000 +#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f +#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000 +#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c +#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0 +#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff +#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10 +#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0 +#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff +#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc +#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c +#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0 +#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1 +#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1 +#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2 +#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2 +#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc +#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9 +#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830 +#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb +#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800 +#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2 +#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0 +#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830 +#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10 +#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000 +#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11 +#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000 +#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9 +#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830 +#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b +#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000 +#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1 +#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834 +#define GC_USB_DIEPCTL0_MPS_LSB 0x0 +#define GC_USB_DIEPCTL0_MPS_MASK 0x3 +#define GC_USB_DIEPCTL0_MPS_SIZE 0x2 +#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900 +#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900 +#define GC_USB_DIEPCTL0_STALL_LSB 0x15 +#define GC_USB_DIEPCTL0_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL0_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900 +#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900 +#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900 +#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900 +#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908 +#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908 +#define GC_USB_DIEPINT0_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT0_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908 +#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908 +#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908 +#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908 +#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908 +#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908 +#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908 +#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908 +#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908 +#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908 +#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908 +#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f +#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7 +#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910 +#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000 +#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2 +#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910 +#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c +#define GC_USB_DIEPCTL1_MPS_LSB 0x0 +#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL1_MPS_SIZE 0xb +#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920 +#define GC_USB_DIEPCTL1_DPID_LSB 0x10 +#define GC_USB_DIEPCTL1_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL1_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920 +#define GC_USB_DIEPCTL1_STALL_LSB 0x15 +#define GC_USB_DIEPCTL1_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL1_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920 +#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920 +#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920 +#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928 +#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928 +#define GC_USB_DIEPINT1_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT1_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928 +#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928 +#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928 +#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928 +#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928 +#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928 +#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928 +#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928 +#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928 +#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928 +#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928 +#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930 +#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c +#define GC_USB_DIEPCTL2_MPS_LSB 0x0 +#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL2_MPS_SIZE 0xb +#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940 +#define GC_USB_DIEPCTL2_DPID_LSB 0x10 +#define GC_USB_DIEPCTL2_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL2_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940 +#define GC_USB_DIEPCTL2_STALL_LSB 0x15 +#define GC_USB_DIEPCTL2_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL2_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940 +#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940 +#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940 +#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948 +#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948 +#define GC_USB_DIEPINT2_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT2_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948 +#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948 +#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948 +#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948 +#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948 +#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948 +#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948 +#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948 +#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948 +#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948 +#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948 +#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950 +#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c +#define GC_USB_DIEPCTL3_MPS_LSB 0x0 +#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL3_MPS_SIZE 0xb +#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960 +#define GC_USB_DIEPCTL3_DPID_LSB 0x10 +#define GC_USB_DIEPCTL3_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL3_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960 +#define GC_USB_DIEPCTL3_STALL_LSB 0x15 +#define GC_USB_DIEPCTL3_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL3_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960 +#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960 +#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960 +#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968 +#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968 +#define GC_USB_DIEPINT3_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT3_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968 +#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968 +#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968 +#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968 +#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968 +#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968 +#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968 +#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968 +#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968 +#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968 +#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968 +#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970 +#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c +#define GC_USB_DIEPCTL4_MPS_LSB 0x0 +#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL4_MPS_SIZE 0xb +#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980 +#define GC_USB_DIEPCTL4_DPID_LSB 0x10 +#define GC_USB_DIEPCTL4_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL4_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980 +#define GC_USB_DIEPCTL4_STALL_LSB 0x15 +#define GC_USB_DIEPCTL4_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL4_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980 +#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980 +#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980 +#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988 +#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988 +#define GC_USB_DIEPINT4_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT4_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988 +#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988 +#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988 +#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988 +#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988 +#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988 +#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988 +#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988 +#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988 +#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988 +#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988 +#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990 +#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c +#define GC_USB_DIEPCTL5_MPS_LSB 0x0 +#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL5_MPS_SIZE 0xb +#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_DPID_LSB 0x10 +#define GC_USB_DIEPCTL5_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL5_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_STALL_LSB 0x15 +#define GC_USB_DIEPCTL5_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL5_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0 +#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT5_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8 +#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0 +#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc +#define GC_USB_DIEPCTL6_MPS_LSB 0x0 +#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL6_MPS_SIZE 0xb +#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_DPID_LSB 0x10 +#define GC_USB_DIEPCTL6_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL6_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_STALL_LSB 0x15 +#define GC_USB_DIEPCTL6_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL6_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0 +#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT6_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8 +#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0 +#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc +#define GC_USB_DIEPCTL7_MPS_LSB 0x0 +#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL7_MPS_SIZE 0xb +#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_DPID_LSB 0x10 +#define GC_USB_DIEPCTL7_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL7_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_STALL_LSB 0x15 +#define GC_USB_DIEPCTL7_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL7_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0 +#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT7_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8 +#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0 +#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc +#define GC_USB_DIEPCTL8_MPS_LSB 0x0 +#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL8_MPS_SIZE 0xb +#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_DPID_LSB 0x10 +#define GC_USB_DIEPCTL8_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL8_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_STALL_LSB 0x15 +#define GC_USB_DIEPCTL8_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL8_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00 +#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08 +#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08 +#define GC_USB_DIEPINT8_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT8_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08 +#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08 +#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08 +#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08 +#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10 +#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c +#define GC_USB_DIEPCTL9_MPS_LSB 0x0 +#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL9_MPS_SIZE 0xb +#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_DPID_LSB 0x10 +#define GC_USB_DIEPCTL9_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL9_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_STALL_LSB 0x15 +#define GC_USB_DIEPCTL9_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL9_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20 +#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28 +#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28 +#define GC_USB_DIEPINT9_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT9_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28 +#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28 +#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28 +#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28 +#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30 +#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c +#define GC_USB_DIEPCTL10_MPS_LSB 0x0 +#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL10_MPS_SIZE 0xb +#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_DPID_LSB 0x10 +#define GC_USB_DIEPCTL10_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL10_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_STALL_LSB 0x15 +#define GC_USB_DIEPCTL10_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL10_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40 +#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48 +#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48 +#define GC_USB_DIEPINT10_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT10_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48 +#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48 +#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48 +#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48 +#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50 +#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c +#define GC_USB_DIEPCTL11_MPS_LSB 0x0 +#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL11_MPS_SIZE 0xb +#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_DPID_LSB 0x10 +#define GC_USB_DIEPCTL11_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL11_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_STALL_LSB 0x15 +#define GC_USB_DIEPCTL11_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL11_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60 +#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68 +#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68 +#define GC_USB_DIEPINT11_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT11_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68 +#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68 +#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68 +#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68 +#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70 +#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c +#define GC_USB_DIEPCTL12_MPS_LSB 0x0 +#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL12_MPS_SIZE 0xb +#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_DPID_LSB 0x10 +#define GC_USB_DIEPCTL12_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL12_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_STALL_LSB 0x15 +#define GC_USB_DIEPCTL12_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL12_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80 +#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88 +#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88 +#define GC_USB_DIEPINT12_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT12_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88 +#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88 +#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88 +#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88 +#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90 +#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c +#define GC_USB_DIEPCTL13_MPS_LSB 0x0 +#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL13_MPS_SIZE 0xb +#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_DPID_LSB 0x10 +#define GC_USB_DIEPCTL13_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL13_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_STALL_LSB 0x15 +#define GC_USB_DIEPCTL13_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL13_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0 +#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT13_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8 +#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0 +#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc +#define GC_USB_DIEPCTL14_MPS_LSB 0x0 +#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL14_MPS_SIZE 0xb +#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_DPID_LSB 0x10 +#define GC_USB_DIEPCTL14_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL14_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_STALL_LSB 0x15 +#define GC_USB_DIEPCTL14_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL14_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0 +#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8 +#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8 +#define GC_USB_DIEPINT14_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT14_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8 +#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8 +#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8 +#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8 +#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0 +#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc +#define GC_USB_DIEPCTL15_MPS_LSB 0x0 +#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL15_MPS_SIZE 0xb +#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_DPID_LSB 0x10 +#define GC_USB_DIEPCTL15_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL15_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_STALL_LSB 0x15 +#define GC_USB_DIEPCTL15_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL15_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0 +#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8 +#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8 +#define GC_USB_DIEPINT15_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT15_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8 +#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8 +#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8 +#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8 +#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0 +#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4 +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc +#define GC_USB_DOEPCTL0_MPS_LSB 0x0 +#define GC_USB_DOEPCTL0_MPS_MASK 0x3 +#define GC_USB_DOEPCTL0_MPS_SIZE 0x2 +#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_SNP_LSB 0x14 +#define GC_USB_DOEPCTL0_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL0_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_STALL_LSB 0x15 +#define GC_USB_DOEPCTL0_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL0_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00 +#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08 +#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08 +#define GC_USB_DOEPINT0_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT0_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_SETUP_LSB 0x3 +#define GC_USB_DOEPINT0_SETUP_MASK 0x8 +#define GC_USB_DOEPINT0_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08 +#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08 +#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08 +#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08 +#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08 +#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f +#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7 +#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000 +#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1 +#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d +#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000 +#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2 +#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10 +#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c +#define GC_USB_DOEPCTL1_MPS_LSB 0x0 +#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL1_MPS_SIZE 0xb +#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_DPID_LSB 0x10 +#define GC_USB_DOEPCTL1_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL1_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SNP_LSB 0x14 +#define GC_USB_DOEPCTL1_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL1_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_STALL_LSB 0x15 +#define GC_USB_DOEPCTL1_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL1_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20 +#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28 +#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28 +#define GC_USB_DOEPINT1_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT1_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_SETUP_LSB 0x3 +#define GC_USB_DOEPINT1_SETUP_MASK 0x8 +#define GC_USB_DOEPINT1_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28 +#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28 +#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28 +#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28 +#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28 +#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30 +#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c +#define GC_USB_DOEPCTL2_MPS_LSB 0x0 +#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL2_MPS_SIZE 0xb +#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_DPID_LSB 0x10 +#define GC_USB_DOEPCTL2_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL2_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SNP_LSB 0x14 +#define GC_USB_DOEPCTL2_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL2_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_STALL_LSB 0x15 +#define GC_USB_DOEPCTL2_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL2_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40 +#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48 +#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48 +#define GC_USB_DOEPINT2_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT2_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_SETUP_LSB 0x3 +#define GC_USB_DOEPINT2_SETUP_MASK 0x8 +#define GC_USB_DOEPINT2_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48 +#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48 +#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48 +#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48 +#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48 +#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50 +#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c +#define GC_USB_DOEPCTL3_MPS_LSB 0x0 +#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL3_MPS_SIZE 0xb +#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_DPID_LSB 0x10 +#define GC_USB_DOEPCTL3_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL3_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SNP_LSB 0x14 +#define GC_USB_DOEPCTL3_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL3_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_STALL_LSB 0x15 +#define GC_USB_DOEPCTL3_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL3_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60 +#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68 +#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68 +#define GC_USB_DOEPINT3_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT3_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_SETUP_LSB 0x3 +#define GC_USB_DOEPINT3_SETUP_MASK 0x8 +#define GC_USB_DOEPINT3_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68 +#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68 +#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68 +#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68 +#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68 +#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70 +#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c +#define GC_USB_DOEPCTL4_MPS_LSB 0x0 +#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL4_MPS_SIZE 0xb +#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_DPID_LSB 0x10 +#define GC_USB_DOEPCTL4_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL4_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SNP_LSB 0x14 +#define GC_USB_DOEPCTL4_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL4_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_STALL_LSB 0x15 +#define GC_USB_DOEPCTL4_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL4_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80 +#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88 +#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88 +#define GC_USB_DOEPINT4_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT4_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_SETUP_LSB 0x3 +#define GC_USB_DOEPINT4_SETUP_MASK 0x8 +#define GC_USB_DOEPINT4_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88 +#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88 +#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88 +#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88 +#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88 +#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90 +#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c +#define GC_USB_DOEPCTL5_MPS_LSB 0x0 +#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL5_MPS_SIZE 0xb +#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_DPID_LSB 0x10 +#define GC_USB_DOEPCTL5_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL5_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SNP_LSB 0x14 +#define GC_USB_DOEPCTL5_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL5_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_STALL_LSB 0x15 +#define GC_USB_DOEPCTL5_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL5_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0 +#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8 +#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8 +#define GC_USB_DOEPINT5_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT5_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_SETUP_LSB 0x3 +#define GC_USB_DOEPINT5_SETUP_MASK 0x8 +#define GC_USB_DOEPINT5_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8 +#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8 +#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8 +#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8 +#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8 +#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0 +#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc +#define GC_USB_DOEPCTL6_MPS_LSB 0x0 +#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL6_MPS_SIZE 0xb +#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_DPID_LSB 0x10 +#define GC_USB_DOEPCTL6_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL6_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SNP_LSB 0x14 +#define GC_USB_DOEPCTL6_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL6_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_STALL_LSB 0x15 +#define GC_USB_DOEPCTL6_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL6_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0 +#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT6_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_SETUP_LSB 0x3 +#define GC_USB_DOEPINT6_SETUP_MASK 0x8 +#define GC_USB_DOEPINT6_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8 +#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0 +#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc +#define GC_USB_DOEPCTL7_MPS_LSB 0x0 +#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL7_MPS_SIZE 0xb +#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_DPID_LSB 0x10 +#define GC_USB_DOEPCTL7_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL7_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SNP_LSB 0x14 +#define GC_USB_DOEPCTL7_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL7_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_STALL_LSB 0x15 +#define GC_USB_DOEPCTL7_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL7_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0 +#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT7_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_SETUP_LSB 0x3 +#define GC_USB_DOEPINT7_SETUP_MASK 0x8 +#define GC_USB_DOEPINT7_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8 +#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0 +#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc +#define GC_USB_DOEPCTL8_MPS_LSB 0x0 +#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL8_MPS_SIZE 0xb +#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_DPID_LSB 0x10 +#define GC_USB_DOEPCTL8_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL8_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SNP_LSB 0x14 +#define GC_USB_DOEPCTL8_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL8_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_STALL_LSB 0x15 +#define GC_USB_DOEPCTL8_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL8_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00 +#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08 +#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08 +#define GC_USB_DOEPINT8_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT8_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_SETUP_LSB 0x3 +#define GC_USB_DOEPINT8_SETUP_MASK 0x8 +#define GC_USB_DOEPINT8_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08 +#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08 +#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08 +#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08 +#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08 +#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10 +#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c +#define GC_USB_DOEPCTL9_MPS_LSB 0x0 +#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL9_MPS_SIZE 0xb +#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_DPID_LSB 0x10 +#define GC_USB_DOEPCTL9_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL9_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SNP_LSB 0x14 +#define GC_USB_DOEPCTL9_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL9_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_STALL_LSB 0x15 +#define GC_USB_DOEPCTL9_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL9_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20 +#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28 +#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28 +#define GC_USB_DOEPINT9_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT9_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_SETUP_LSB 0x3 +#define GC_USB_DOEPINT9_SETUP_MASK 0x8 +#define GC_USB_DOEPINT9_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28 +#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28 +#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28 +#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28 +#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28 +#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30 +#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c +#define GC_USB_DOEPCTL10_MPS_LSB 0x0 +#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL10_MPS_SIZE 0xb +#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_DPID_LSB 0x10 +#define GC_USB_DOEPCTL10_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL10_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SNP_LSB 0x14 +#define GC_USB_DOEPCTL10_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL10_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_STALL_LSB 0x15 +#define GC_USB_DOEPCTL10_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL10_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40 +#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48 +#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48 +#define GC_USB_DOEPINT10_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT10_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_SETUP_LSB 0x3 +#define GC_USB_DOEPINT10_SETUP_MASK 0x8 +#define GC_USB_DOEPINT10_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48 +#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48 +#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48 +#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48 +#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48 +#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50 +#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c +#define GC_USB_DOEPCTL11_MPS_LSB 0x0 +#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL11_MPS_SIZE 0xb +#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_DPID_LSB 0x10 +#define GC_USB_DOEPCTL11_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL11_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SNP_LSB 0x14 +#define GC_USB_DOEPCTL11_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL11_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_STALL_LSB 0x15 +#define GC_USB_DOEPCTL11_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL11_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60 +#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68 +#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68 +#define GC_USB_DOEPINT11_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT11_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_SETUP_LSB 0x3 +#define GC_USB_DOEPINT11_SETUP_MASK 0x8 +#define GC_USB_DOEPINT11_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68 +#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68 +#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68 +#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68 +#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68 +#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70 +#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c +#define GC_USB_DOEPCTL12_MPS_LSB 0x0 +#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL12_MPS_SIZE 0xb +#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_DPID_LSB 0x10 +#define GC_USB_DOEPCTL12_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL12_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SNP_LSB 0x14 +#define GC_USB_DOEPCTL12_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL12_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_STALL_LSB 0x15 +#define GC_USB_DOEPCTL12_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL12_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80 +#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88 +#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88 +#define GC_USB_DOEPINT12_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT12_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_SETUP_LSB 0x3 +#define GC_USB_DOEPINT12_SETUP_MASK 0x8 +#define GC_USB_DOEPINT12_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88 +#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88 +#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88 +#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88 +#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88 +#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90 +#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c +#define GC_USB_DOEPCTL13_MPS_LSB 0x0 +#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL13_MPS_SIZE 0xb +#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_DPID_LSB 0x10 +#define GC_USB_DOEPCTL13_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL13_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SNP_LSB 0x14 +#define GC_USB_DOEPCTL13_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL13_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_STALL_LSB 0x15 +#define GC_USB_DOEPCTL13_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL13_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0 +#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8 +#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8 +#define GC_USB_DOEPINT13_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT13_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_SETUP_LSB 0x3 +#define GC_USB_DOEPINT13_SETUP_MASK 0x8 +#define GC_USB_DOEPINT13_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8 +#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8 +#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8 +#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8 +#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8 +#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0 +#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc +#define GC_USB_DOEPCTL14_MPS_LSB 0x0 +#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL14_MPS_SIZE 0xb +#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_DPID_LSB 0x10 +#define GC_USB_DOEPCTL14_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL14_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SNP_LSB 0x14 +#define GC_USB_DOEPCTL14_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL14_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_STALL_LSB 0x15 +#define GC_USB_DOEPCTL14_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL14_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0 +#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT14_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_SETUP_LSB 0x3 +#define GC_USB_DOEPINT14_SETUP_MASK 0x8 +#define GC_USB_DOEPINT14_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8 +#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0 +#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc +#define GC_USB_DOEPCTL15_MPS_LSB 0x0 +#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL15_MPS_SIZE 0xb +#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_DPID_LSB 0x10 +#define GC_USB_DOEPCTL15_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL15_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SNP_LSB 0x14 +#define GC_USB_DOEPCTL15_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL15_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_STALL_LSB 0x15 +#define GC_USB_DOEPCTL15_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL15_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0 +#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8 +#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8 +#define GC_USB_DOEPINT15_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT15_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_SETUP_LSB 0x3 +#define GC_USB_DOEPINT15_SETUP_MASK 0x8 +#define GC_USB_DOEPINT15_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8 +#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8 +#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8 +#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8 +#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8 +#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0 +#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc +#define GC_WATCHDOG_WDOGCONTROL_INTEN_LSB 0x0 +#define GC_WATCHDOG_WDOGCONTROL_INTEN_MASK 0x1 +#define GC_WATCHDOG_WDOGCONTROL_INTEN_SIZE 0x1 +#define GC_WATCHDOG_WDOGCONTROL_INTEN_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGCONTROL_INTEN_OFFSET 0x8 +#define GC_WATCHDOG_WDOGCONTROL_RESEN_LSB 0x1 +#define GC_WATCHDOG_WDOGCONTROL_RESEN_MASK 0x2 +#define GC_WATCHDOG_WDOGCONTROL_RESEN_SIZE 0x1 +#define GC_WATCHDOG_WDOGCONTROL_RESEN_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGCONTROL_RESEN_OFFSET 0x8 +#define GC_WATCHDOG_WDOGITOP_WDOGRES_LSB 0x0 +#define GC_WATCHDOG_WDOGITOP_WDOGRES_MASK 0x1 +#define GC_WATCHDOG_WDOGITOP_WDOGRES_SIZE 0x1 +#define GC_WATCHDOG_WDOGITOP_WDOGRES_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGITOP_WDOGRES_OFFSET 0xf04 +#define GC_WATCHDOG_WDOGITOP_WDOGINT_LSB 0x1 +#define GC_WATCHDOG_WDOGITOP_WDOGINT_MASK 0x2 +#define GC_WATCHDOG_WDOGITOP_WDOGINT_SIZE 0x1 +#define GC_WATCHDOG_WDOGITOP_WDOGINT_DEFAULT 0x0 +#define GC_WATCHDOG_WDOGITOP_WDOGINT_OFFSET 0xf04 +#define GC_XO_OSC_CLKOUT_ADC_EN_LSB 0x0 +#define GC_XO_OSC_CLKOUT_ADC_EN_MASK 0x1 +#define GC_XO_OSC_CLKOUT_ADC_EN_SIZE 0x1 +#define GC_XO_OSC_CLKOUT_ADC_EN_DEFAULT 0x0 +#define GC_XO_OSC_CLKOUT_ADC_EN_OFFSET 0x0 +#define GC_XO_OSC_CLKOUT_PLL_EN_LSB 0x1 +#define GC_XO_OSC_CLKOUT_PLL_EN_MASK 0x2 +#define GC_XO_OSC_CLKOUT_PLL_EN_SIZE 0x1 +#define GC_XO_OSC_CLKOUT_PLL_EN_DEFAULT 0x0 +#define GC_XO_OSC_CLKOUT_PLL_EN_OFFSET 0x0 +#define GC_XO_OSC_CLKOUT_BADC_EN_LSB 0x2 +#define GC_XO_OSC_CLKOUT_BADC_EN_MASK 0x4 +#define GC_XO_OSC_CLKOUT_BADC_EN_SIZE 0x1 +#define GC_XO_OSC_CLKOUT_BADC_EN_DEFAULT 0x0 +#define GC_XO_OSC_CLKOUT_BADC_EN_OFFSET 0x0 +#define GC_XO_OSC_CLKOUT_USB_EN_LSB 0x3 +#define GC_XO_OSC_CLKOUT_USB_EN_MASK 0x8 +#define GC_XO_OSC_CLKOUT_USB_EN_SIZE 0x1 +#define GC_XO_OSC_CLKOUT_USB_EN_DEFAULT 0x0 +#define GC_XO_OSC_CLKOUT_USB_EN_OFFSET 0x0 +#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_LSB 0x0 +#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_MASK 0xf +#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_SIZE 0x4 +#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_DEFAULT 0x6 +#define GC_XO_OSC_ADC_CAL_FREQ2X_CNTL_OFFSET 0x4 +#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_LSB 0x4 +#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_MASK 0x10 +#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_SIZE 0x1 +#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_DEFAULT 0x0 +#define GC_XO_OSC_ADC_CAL_FREQ2X_EN_OFFSET 0x4 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_LSB 0x0 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_MASK 0xf +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_SIZE 0x4 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_DEFAULT 0x6 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_CNTL_OFFSET 0x8 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_LSB 0x4 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_MASK 0x10 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_SIZE 0x1 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_DEFAULT 0x0 +#define GC_XO_OSC_ADC_CAL_FREQ2X_STAT_EN_OFFSET 0x8 +#define GC_XO_OSC_24_48B_SEL_ADC_LSB 0x0 +#define GC_XO_OSC_24_48B_SEL_ADC_MASK 0x1 +#define GC_XO_OSC_24_48B_SEL_ADC_SIZE 0x1 +#define GC_XO_OSC_24_48B_SEL_ADC_DEFAULT 0x0 +#define GC_XO_OSC_24_48B_SEL_ADC_OFFSET 0xc +#define GC_XO_OSC_24_48B_SEL_PLL_LSB 0x1 +#define GC_XO_OSC_24_48B_SEL_PLL_MASK 0x2 +#define GC_XO_OSC_24_48B_SEL_PLL_SIZE 0x1 +#define GC_XO_OSC_24_48B_SEL_PLL_DEFAULT 0x0 +#define GC_XO_OSC_24_48B_SEL_PLL_OFFSET 0xc +#define GC_XO_OSC_TEST_CLK48_ADC_EN_LSB 0x0 +#define GC_XO_OSC_TEST_CLK48_ADC_EN_MASK 0x1 +#define GC_XO_OSC_TEST_CLK48_ADC_EN_SIZE 0x1 +#define GC_XO_OSC_TEST_CLK48_ADC_EN_DEFAULT 0x0 +#define GC_XO_OSC_TEST_CLK48_ADC_EN_OFFSET 0x10 +#define GC_XO_OSC_TEST_CLK48_PLL_EN_LSB 0x1 +#define GC_XO_OSC_TEST_CLK48_PLL_EN_MASK 0x2 +#define GC_XO_OSC_TEST_CLK48_PLL_EN_SIZE 0x1 +#define GC_XO_OSC_TEST_CLK48_PLL_EN_DEFAULT 0x0 +#define GC_XO_OSC_TEST_CLK48_PLL_EN_OFFSET 0x10 +#define GC_XO_OSC_TEST_DIG_EN_LSB 0x2 +#define GC_XO_OSC_TEST_DIG_EN_MASK 0x4 +#define GC_XO_OSC_TEST_DIG_EN_SIZE 0x1 +#define GC_XO_OSC_TEST_DIG_EN_DEFAULT 0x0 +#define GC_XO_OSC_TEST_DIG_EN_OFFSET 0x10 +#define GC_XO_OSC_RC_TRIM_LSB 0x0 +#define GC_XO_OSC_RC_TRIM_MASK 0xfffffff +#define GC_XO_OSC_RC_TRIM_SIZE 0x1c +#define GC_XO_OSC_RC_TRIM_DEFAULT 0x4444444 +#define GC_XO_OSC_RC_TRIM_OFFSET 0x28 +#define GC_XO_OSC_RC_EN_LSB 0x1c +#define GC_XO_OSC_RC_EN_MASK 0x10000000 +#define GC_XO_OSC_RC_EN_SIZE 0x1 +#define GC_XO_OSC_RC_EN_DEFAULT 0x0 +#define GC_XO_OSC_RC_EN_OFFSET 0x28 +#define GC_XO_OSC_RC_STATUS_TRIM_LSB 0x0 +#define GC_XO_OSC_RC_STATUS_TRIM_MASK 0xfffffff +#define GC_XO_OSC_RC_STATUS_TRIM_SIZE 0x1c +#define GC_XO_OSC_RC_STATUS_TRIM_DEFAULT 0x4444444 +#define GC_XO_OSC_RC_STATUS_TRIM_OFFSET 0x2c +#define GC_XO_OSC_RC_STATUS_EN_LSB 0x1c +#define GC_XO_OSC_RC_STATUS_EN_MASK 0x10000000 +#define GC_XO_OSC_RC_STATUS_EN_SIZE 0x1 +#define GC_XO_OSC_RC_STATUS_EN_DEFAULT 0x0 +#define GC_XO_OSC_RC_STATUS_EN_OFFSET 0x2c +#define GC_XO_OSC_XTL_RC_FLTR_TRIM_LSB 0x0 +#define GC_XO_OSC_XTL_RC_FLTR_TRIM_MASK 0xf +#define GC_XO_OSC_XTL_RC_FLTR_TRIM_SIZE 0x4 +#define GC_XO_OSC_XTL_RC_FLTR_TRIM_DEFAULT 0x5 +#define GC_XO_OSC_XTL_RC_FLTR_TRIM_OFFSET 0x3c +#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_LSB 0x4 +#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_MASK 0x10 +#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_SIZE 0x1 +#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_DEFAULT 0x1 +#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_OFFSET 0x3c +#define GC_XO_OSC_XTL_OVRD_TRIM_LSB 0x0 +#define GC_XO_OSC_XTL_OVRD_TRIM_MASK 0xf +#define GC_XO_OSC_XTL_OVRD_TRIM_SIZE 0x4 +#define GC_XO_OSC_XTL_OVRD_TRIM_DEFAULT 0x7 +#define GC_XO_OSC_XTL_OVRD_TRIM_OFFSET 0x40 +#define GC_XO_OSC_XTL_OVRD_ENB_LSB 0x4 +#define GC_XO_OSC_XTL_OVRD_ENB_MASK 0x10 +#define GC_XO_OSC_XTL_OVRD_ENB_SIZE 0x1 +#define GC_XO_OSC_XTL_OVRD_ENB_DEFAULT 0x1 +#define GC_XO_OSC_XTL_OVRD_ENB_OFFSET 0x40 +#define GC_XO_OSC_XTL_TRIM_CODE_LSB 0x0 +#define GC_XO_OSC_XTL_TRIM_CODE_MASK 0xf +#define GC_XO_OSC_XTL_TRIM_CODE_SIZE 0x4 +#define GC_XO_OSC_XTL_TRIM_CODE_DEFAULT 0x0 +#define GC_XO_OSC_XTL_TRIM_CODE_OFFSET 0x48 +#define GC_XO_OSC_XTL_TRIM_EN_LSB 0x4 +#define GC_XO_OSC_XTL_TRIM_EN_MASK 0x10 +#define GC_XO_OSC_XTL_TRIM_EN_SIZE 0x1 +#define GC_XO_OSC_XTL_TRIM_EN_DEFAULT 0x0 +#define GC_XO_OSC_XTL_TRIM_EN_OFFSET 0x48 +#define GC_XO_OSC_XTL_TRIM_STAT_CODE_LSB 0x0 +#define GC_XO_OSC_XTL_TRIM_STAT_CODE_MASK 0xf +#define GC_XO_OSC_XTL_TRIM_STAT_CODE_SIZE 0x4 +#define GC_XO_OSC_XTL_TRIM_STAT_CODE_DEFAULT 0x0 +#define GC_XO_OSC_XTL_TRIM_STAT_CODE_OFFSET 0x4c +#define GC_XO_OSC_XTL_TRIM_STAT_EN_LSB 0x4 +#define GC_XO_OSC_XTL_TRIM_STAT_EN_MASK 0x10 +#define GC_XO_OSC_XTL_TRIM_STAT_EN_SIZE 0x1 +#define GC_XO_OSC_XTL_TRIM_STAT_EN_DEFAULT 0x0 +#define GC_XO_OSC_XTL_TRIM_STAT_EN_OFFSET 0x4c +#define GC_XO_OSC_XTL_FSM_DONE_LSB 0x0 +#define GC_XO_OSC_XTL_FSM_DONE_MASK 0x1 +#define GC_XO_OSC_XTL_FSM_DONE_SIZE 0x1 +#define GC_XO_OSC_XTL_FSM_DONE_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_DONE_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_TRIM_LSB 0x1 +#define GC_XO_OSC_XTL_FSM_TRIM_MASK 0x1e +#define GC_XO_OSC_XTL_FSM_TRIM_SIZE 0x4 +#define GC_XO_OSC_XTL_FSM_TRIM_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_TRIM_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_STATUS_LSB 0x5 +#define GC_XO_OSC_XTL_FSM_STATUS_MASK 0x20 +#define GC_XO_OSC_XTL_FSM_STATUS_SIZE 0x1 +#define GC_XO_OSC_XTL_FSM_STATUS_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_STATUS_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_STATE_LSB 0x6 +#define GC_XO_OSC_XTL_FSM_STATE_MASK 0x3c0 +#define GC_XO_OSC_XTL_FSM_STATE_SIZE 0x4 +#define GC_XO_OSC_XTL_FSM_STATE_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_STATE_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_LSB 0xa +#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_MASK 0x400 +#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_SIZE 0x1 +#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_OFFSET 0x54 +#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_LSB 0x0 +#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_MASK 0xf +#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_SIZE 0x4 +#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_DEFAULT 0x8 +#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_LSB 0x4 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_MASK 0x30 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_SIZE 0x2 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_DEFAULT 0x0 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_LSB 0x6 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_MASK 0xc0 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_SIZE 0x2 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_DEFAULT 0x2 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_LSB 0x8 +#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_MASK 0x700 +#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_SIZE 0x3 +#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_DEFAULT 0x4 +#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_LSB 0xb +#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_MASK 0xf800 +#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_SIZE 0x5 +#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_DEFAULT 0xe +#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_OFFSET 0x58 +#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_LSB 0x10 +#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_MASK 0x1f0000 +#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_SIZE 0x5 +#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_DEFAULT 0xd +#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x58 +#define GC_XO_OSC_SETHOLD_RC_TRIM_LSB 0x0 +#define GC_XO_OSC_SETHOLD_RC_TRIM_MASK 0x1 +#define GC_XO_OSC_SETHOLD_RC_TRIM_SIZE 0x1 +#define GC_XO_OSC_SETHOLD_RC_TRIM_DEFAULT 0x0 +#define GC_XO_OSC_SETHOLD_RC_TRIM_OFFSET 0x5c +#define GC_XO_OSC_SETHOLD_XTL_LSB 0x1 +#define GC_XO_OSC_SETHOLD_XTL_MASK 0x2 +#define GC_XO_OSC_SETHOLD_XTL_SIZE 0x1 +#define GC_XO_OSC_SETHOLD_XTL_DEFAULT 0x0 +#define GC_XO_OSC_SETHOLD_XTL_OFFSET 0x5c +#define GC_XO_OSC_SETHOLD_ANA_LSB 0x2 +#define GC_XO_OSC_SETHOLD_ANA_MASK 0x4 +#define GC_XO_OSC_SETHOLD_ANA_SIZE 0x1 +#define GC_XO_OSC_SETHOLD_ANA_DEFAULT 0x0 +#define GC_XO_OSC_SETHOLD_ANA_OFFSET 0x5c +#define GC_XO_OSC_CLRHOLD_RC_TRIM_LSB 0x0 +#define GC_XO_OSC_CLRHOLD_RC_TRIM_MASK 0x1 +#define GC_XO_OSC_CLRHOLD_RC_TRIM_SIZE 0x1 +#define GC_XO_OSC_CLRHOLD_RC_TRIM_DEFAULT 0x0 +#define GC_XO_OSC_CLRHOLD_RC_TRIM_OFFSET 0x60 +#define GC_XO_OSC_CLRHOLD_XTL_LSB 0x1 +#define GC_XO_OSC_CLRHOLD_XTL_MASK 0x2 +#define GC_XO_OSC_CLRHOLD_XTL_SIZE 0x1 +#define GC_XO_OSC_CLRHOLD_XTL_DEFAULT 0x0 +#define GC_XO_OSC_CLRHOLD_XTL_OFFSET 0x60 +#define GC_XO_OSC_CLRHOLD_ANA_LSB 0x2 +#define GC_XO_OSC_CLRHOLD_ANA_MASK 0x4 +#define GC_XO_OSC_CLRHOLD_ANA_SIZE 0x1 +#define GC_XO_OSC_CLRHOLD_ANA_DEFAULT 0x0 +#define GC_XO_OSC_CLRHOLD_ANA_OFFSET 0x60 +#define GC_M3_ICTR_INTLINESNUM_LSB 0x0 +#define GC_M3_ICTR_INTLINESNUM_MASK 0xf +#define GC_M3_ICTR_INTLINESNUM_SIZE 0x4 +#define GC_M3_ICTR_INTLINESNUM_DEFAULT 0x4 +#define GC_M3_ICTR_INTLINESNUM_OFFSET 0xe004 +#define GC_M3_SYST_CSR_ENABLE_LSB 0x0 +#define GC_M3_SYST_CSR_ENABLE_MASK 0x1 +#define GC_M3_SYST_CSR_ENABLE_SIZE 0x1 +#define GC_M3_SYST_CSR_ENABLE_DEFAULT 0x0 +#define GC_M3_SYST_CSR_ENABLE_OFFSET 0xe010 +#define GC_M3_SYST_CSR_TICKINT_LSB 0x1 +#define GC_M3_SYST_CSR_TICKINT_MASK 0x2 +#define GC_M3_SYST_CSR_TICKINT_SIZE 0x1 +#define GC_M3_SYST_CSR_TICKINT_DEFAULT 0x0 +#define GC_M3_SYST_CSR_TICKINT_OFFSET 0xe010 +#define GC_M3_SYST_CSR_CLKSOURCE_LSB 0x2 +#define GC_M3_SYST_CSR_CLKSOURCE_MASK 0x4 +#define GC_M3_SYST_CSR_CLKSOURCE_SIZE 0x1 +#define GC_M3_SYST_CSR_CLKSOURCE_DEFAULT 0x1 +#define GC_M3_SYST_CSR_CLKSOURCE_OFFSET 0xe010 +#define GC_M3_SYST_CSR_RESERVED_LSB 0x3 +#define GC_M3_SYST_CSR_RESERVED_MASK 0xfff8 +#define GC_M3_SYST_CSR_RESERVED_SIZE 0xd +#define GC_M3_SYST_CSR_RESERVED_DEFAULT 0x0 +#define GC_M3_SYST_CSR_RESERVED_OFFSET 0xe010 +#define GC_M3_SYST_CSR_COUNTFLAG_LSB 0x10 +#define GC_M3_SYST_CSR_COUNTFLAG_MASK 0x10000 +#define GC_M3_SYST_CSR_COUNTFLAG_SIZE 0x1 +#define GC_M3_SYST_CSR_COUNTFLAG_DEFAULT 0x0 +#define GC_M3_SYST_CSR_COUNTFLAG_OFFSET 0xe010 +#define GC_M3_SYST_RVR_RELOAD_LSB 0x0 +#define GC_M3_SYST_RVR_RELOAD_MASK 0xffffff +#define GC_M3_SYST_RVR_RELOAD_SIZE 0x18 +#define GC_M3_SYST_RVR_RELOAD_DEFAULT 0x0 +#define GC_M3_SYST_RVR_RELOAD_OFFSET 0xe014 +#define GC_M3_SYST_CVR_RELOAD_LSB 0x0 +#define GC_M3_SYST_CVR_RELOAD_MASK 0xffffffff +#define GC_M3_SYST_CVR_RELOAD_SIZE 0x20 +#define GC_M3_SYST_CVR_RELOAD_DEFAULT 0x0 +#define GC_M3_SYST_CVR_RELOAD_OFFSET 0xe018 +#define GC_M3_SYST_CALIB_TENMS_LSB 0x0 +#define GC_M3_SYST_CALIB_TENMS_MASK 0xffffff +#define GC_M3_SYST_CALIB_TENMS_SIZE 0x18 +#define GC_M3_SYST_CALIB_TENMS_DEFAULT 0x3f79f +#define GC_M3_SYST_CALIB_TENMS_OFFSET 0xe01c +#define GC_M3_SYST_CALIB_RESERVED_LSB 0x18 +#define GC_M3_SYST_CALIB_RESERVED_MASK 0x3f000000 +#define GC_M3_SYST_CALIB_RESERVED_SIZE 0x6 +#define GC_M3_SYST_CALIB_RESERVED_DEFAULT 0x0 +#define GC_M3_SYST_CALIB_RESERVED_OFFSET 0xe01c +#define GC_M3_SYST_CALIB_SKEW_LSB 0x1e +#define GC_M3_SYST_CALIB_SKEW_MASK 0x40000000 +#define GC_M3_SYST_CALIB_SKEW_SIZE 0x1 +#define GC_M3_SYST_CALIB_SKEW_DEFAULT 0x0 +#define GC_M3_SYST_CALIB_SKEW_OFFSET 0xe01c +#define GC_M3_SYST_CALIB_NOREF_LSB 0x1f +#define GC_M3_SYST_CALIB_NOREF_MASK 0x80000000 +#define GC_M3_SYST_CALIB_NOREF_SIZE 0x1 +#define GC_M3_SYST_CALIB_NOREF_DEFAULT 0x0 +#define GC_M3_SYST_CALIB_NOREF_OFFSET 0xe01c +#define GC_SPI_DATA_SIZE 0x100 +#define GC_SPS_DATA_SIZE 0x800 +#define GC_USB_DFIFO_PP0_SIZE 0x1000 +#define GC_USB_DFIFO_PP1_SIZE 0x1000 +#define GC_USB_DFIFO_PP2_SIZE 0x1000 +#define GC_USB_DFIFO_PP3_SIZE 0x1000 +#define GC_USB_DFIFO_PP4_SIZE 0x1000 +#define GC_USB_DFIFO_PP5_SIZE 0x1000 +#define GC_USB_DFIFO_PP6_SIZE 0x1000 +#define GC_USB_DFIFO_PP7_SIZE 0x1000 +#define GC_USB_DFIFO_PP8_SIZE 0x1000 +#define GC_USB_DFIFO_PP9_SIZE 0x1000 +#define GC_USB_DFIFO_PP10_SIZE 0x1000 +#define GC_USB_DFIFO_PP11_SIZE 0x1000 +#define GC_USB_DFIFO_PP12_SIZE 0x1000 +#define GC_USB_DFIFO_PP13_SIZE 0x1000 +#define GC_USB_DFIFO_PP14_SIZE 0x1000 +#define GC_USB_DFIFO_PP15_SIZE 0x1000 +#define GC_USB_DFIFO_SIZE 0x1000 +#ifdef GC__ENABLE_FLASH_DFT_DEFINITIONS__ +#define GC_FLASH_DFT_REGS_ADDR_WIDTH 4 +#define GC_FLASH_DFT_R_PIN_ADDR 0 +#define GC_FLASH_DFT_R_PIN_WIDTH 7 +#define GC_FLASH_DFT_R_XADR_ADDR 1 +#define GC_FLASH_DFT_R_XADR_WIDTH 10 +#define GC_FLASH_DFT_R_YADR_ADDR 2 +#define GC_FLASH_DFT_R_YADR_WIDTH 6 +#define GC_FLASH_DFT_R_DATA_ADDR 3 +#define GC_FLASH_DFT_R_DATA_WIDTH 32 +#define GC_FLASH_DFT_R_CTRL_ADDR 4 +#define GC_FLASH_DFT_R_CTRL_WIDTH 16 +#define GC_FLASH_DFT_R_GRPSEL_ADDR 5 +#define GC_FLASH_DFT_R_GRPSEL_WIDTH 1 +#define GC_FLASH_DFT_R_OPMODE_ADDR 6 +#define GC_FLASH_DFT_R_OPMODE_WIDTH 5 +#define GC_FLASH_DFT_R_IPSEL_ADDR 7 +#define GC_FLASH_DFT_R_IPSEL_WIDTH 4 +#define GC_FLASH_DFT_R_STATUS_ADDR 8 +#define GC_FLASH_DFT_R_STATUS_WIDTH 2 +#define GC_FLASH_DFT_R_BITSEL_ADDR 9 +#define GC_FLASH_DFT_R_BITSEL_WIDTH 6 +#define GC_FLASH_DFT_R_REPAIR_0_ADDR 10 +#define GC_FLASH_DFT_R_REPAIR_0_WIDTH 8 +#define GC_FLASH_DFT_R_REPAIR_1_ADDR 11 +#define GC_FLASH_DFT_R_REPAIR_1_WIDTH 8 +#define GC_FLASH_DFT_R_SMW_ADDR 12 +#define GC_FLASH_DFT_R_SMW_WIDTH 2 +#define GC_FLASH_DFT_WIDTH_BY_ADDR(addr) \ + (addr == GC_FLASH_DFT_R_PIN_ADDR) ? 7 : \ + (addr == GC_FLASH_DFT_R_XADR_ADDR) ? 10 : \ + (addr == GC_FLASH_DFT_R_YADR_ADDR) ? 6 : \ + (addr == GC_FLASH_DFT_R_DATA_ADDR) ? 32 : \ + (addr == GC_FLASH_DFT_R_CTRL_ADDR) ? 16 : \ + (addr == GC_FLASH_DFT_R_GRPSEL_ADDR) ? 1 : \ + (addr == GC_FLASH_DFT_R_OPMODE_ADDR) ? 5 : \ + (addr == GC_FLASH_DFT_R_IPSEL_ADDR) ? 4 : \ + (addr == GC_FLASH_DFT_R_STATUS_ADDR) ? 2 : \ + (addr == GC_FLASH_DFT_R_BITSEL_ADDR) ? 6 : \ + (addr == GC_FLASH_DFT_R_REPAIR_0_ADDR) ? 8 : \ + (addr == GC_FLASH_DFT_R_REPAIR_1_ADDR) ? 8 : \ + (addr == GC_FLASH_DFT_R_SMW_ADDR) ? 2 : \ + -1 +#endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */ + +#endif /* GC_REGDEFS_H */ +#define GC_CONST_FSH_PE_CONTROL_READ 0x16021765 +#define GC_CONST_FSH_PE_CONTROL_PROGRAM 0x27182818 +#define GC_CONST_FSH_PE_CONTROL_ERASE 0x31415927 +#define GC_CONST_FSH_PE_CONTROL_BULKERASE 0x1d1e2bad +#define GC_CONST_FSH_OVRD_UNLOCK 0x13806488 +#define GC_CONST_FSH_PE_EN 0xb11924e1 diff --git a/chip/g/gc_regdefs.h b/chip/g/cr50_fpga_regdefs.h index cfe8dd8f59..cfe8dd8f59 100644 --- a/chip/g/gc_regdefs.h +++ b/chip/g/cr50_fpga_regdefs.h diff --git a/chip/g/registers.h b/chip/g/registers.h index e549dd091c..36a9f96ac1 100644 --- a/chip/g/registers.h +++ b/chip/g/registers.h @@ -7,9 +7,22 @@ #define __CROS_EC_REGISTERS_H #include "common.h" -#include "gc_regdefs.h" +#if defined(CHIP_VARIANT_CR50_FPGA) +#include "cr50_fpga_regdefs.h" +#define PCLK_FREQ 30000000 +#elif defined(CHIP_VARIANT_CR50_A1) +#include "cr50_a1_regdefs.h" +#define PCLK_FREQ 24000000 +#else +#error "Unsupported CR50 chip variant" +#endif + #include "util.h" +/* Constants for setting baud rate */ +#define DEFAULT_UART_FREQ 1000000 +#define UART_NCO_WIDTH 16 + /* Replace masked bits with val << lsb */ #define REG_WRITE_MLV(reg, mask, lsb, val) reg = ((reg & ~mask) | ((val << lsb) & mask)) diff --git a/chip/g/uart.c b/chip/g/uart.c index dfea855105..8d0e39f868 100644 --- a/chip/g/uart.c +++ b/chip/g/uart.c @@ -124,11 +124,6 @@ void uart_ec_rx_interrupt(void) } DECLARE_IRQ(GC_IRQNUM_UART0_RXINT, uart_ec_rx_interrupt, 1); -/* Constants for setting baud rate */ -#define PCLK_FREQ 30000000 -#define DEFAULT_UART_FREQ 1000000 -#define UART_NCO_WIDTH 16 - void uart_init(void) { long long setting = (16 * (1 << UART_NCO_WIDTH) * |