Ryu: Add support for the SPI over USB bridge

This enables the USB SPI bridge and adds Ryu specific
functions for enabling and disabling the SPI bridge.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j
     Verify that a modified flashrom can read and write
     the AP SPI Flash.

Change-Id: I3ed2503e23c360c0de7a3aedd1d256be7e82df1e
Reviewed-on: https://chromium-review.googlesource.com/260965
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>

3 files changed, 69 insertions, 14 deletions

diff --git a/board/ryu/board.c b/board/ryu/board.c
index 6b35bf06dd..e0b3079fcc 100644
--- a/board/ryu/board.c
+++ b/board/ryu/board.c
@@ -24,10 +24,12 @@
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
+#include "spi.h"
 #include "task.h"
 #include "usb.h"
 #include "usb_pd.h"
 #include "usb_pd_config.h"
+#include "usb_spi.h"
 #include "usb-stm32f3.h"
 #include "usb-stream.h"
 #include "usart-stm32f3.h"
@@ -516,3 +518,50 @@ int board_is_vbus_too_low(enum chg_ramp_vbus_state ramp_state)
 {
 	return adc_read_channel(ADC_VBUS) < VBUS_LOW_THRESHOLD_MV;
 }
+
+/*
+ * Enable and disable SPI for case closed debugging.  This forces the AP into
+ * reset while SPI is enabled, thus preventing contention on the SPI interface.
+ */
+void usb_spi_board_enable(struct usb_spi_config const *config)
+{
+	/* Place AP into reset */
+	gpio_set_level(GPIO_PMIC_WARM_RESET_L, 0);
+
+	/* Configure SPI GPIOs */
+	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_set_flags(GPIO_SPI_FLASH_NSS, GPIO_OUT_HIGH);
+
+	/* Set all four SPI pins to high speed */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xf03c0000;
+
+	/* Enable clocks to SPI2 module */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+
+	/* Reset SPI2 */
+	STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
+	STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
+
+	/* Enable SPI LDO to power the flash chip */
+	gpio_set_level(GPIO_VDDSPI_EN, 1);
+
+	spi_enable(1);
+}
+
+void usb_spi_board_disable(struct usb_spi_config const *config)
+{
+	spi_enable(0);
+
+	/* Disable SPI LDO */
+	gpio_set_level(GPIO_VDDSPI_EN, 0);
+
+	/* Disable clocks to SPI2 module */
+	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
+
+	/* Release SPI GPIOs */
+	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_set_flags(GPIO_SPI_FLASH_NSS, GPIO_INPUT);
+
+	/* Release AP from reset */
+	gpio_set_level(GPIO_PMIC_WARM_RESET_L, 1);
+}
diff --git a/board/ryu/board.h b/board/ryu/board.h
index 7b8c710205..092284e40e 100644
--- a/board/ryu/board.h
+++ b/board/ryu/board.h
@@ -98,24 +98,32 @@
 #define USB_IFACE_CONSOLE   0
 #define USB_IFACE_AP_STREAM 1
 #define USB_IFACE_SH_STREAM 2
-#define USB_IFACE_COUNT     3
+#define USB_IFACE_SPI       3
+#define USB_IFACE_COUNT     4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL   0
 #define USB_EP_CONSOLE   1
 #define USB_EP_AP_STREAM 2
 #define USB_EP_SH_STREAM 3
-#define USB_EP_COUNT     4
+#define USB_EP_SPI       4
+#define USB_EP_COUNT     5
 
 /* Enable console over USB */
 #define CONFIG_USB_CONSOLE
 
+/* Enable control of SPI over USB */
+#define CONFIG_SPI_MASTER_PORT 2
+#define CONFIG_SPI_CS_GPIO     GPIO_SPI_FLASH_NSS
+
+#define CONFIG_USB_SPI
+
 /* Enable Case Closed Debugging */
 #define CONFIG_CASE_CLOSED_DEBUG
 
 /* Maximum number of deferrable functions */
 #undef  DEFERRABLE_MAX_COUNT
-#define DEFERRABLE_MAX_COUNT 11
+#define DEFERRABLE_MAX_COUNT 12
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/ryu/gpio.inc b/board/ryu/gpio.inc
index 436fa89ee0..f526b570b9 100644
--- a/board/ryu/gpio.inc
+++ b/board/ryu/gpio.inc
@@ -95,11 +95,8 @@ GPIO(PERICOM_CLK_EN,       C, 15, GPIO_OUT_HIGH, NULL)
 
 /* Case closed debugging. */
 GPIO(USB_PU_EN_L,          C, 2,  GPIO_OUT_HIGH, NULL)
-GPIO(PD_DISABLE_DEBUG,     C, 6,  GPIO_OUT_HIGH, NULL)
+GPIO(PD_DISABLE_DEBUG,     C, 6,  GPIO_OUT_LOW,  NULL)
 GPIO(SPI_FLASH_NSS,        B, 9,  GPIO_INPUT,    NULL)
-GPIO(SPI_FLASH_SCK,        B, 10, GPIO_INPUT,    NULL)
-GPIO(SPI_FLASH_MOSI,       B, 15, GPIO_INPUT,    NULL)
-GPIO(SPI_FLASH_MISO,       B, 14, GPIO_INPUT,    NULL)
 GPIO(VDDSPI_EN,            C, 12, GPIO_OUT_LOW,  NULL)
 GPIO(SH_RESET_L,           C, 4,  GPIO_ODR_HIGH, NULL)
 GPIO(SH_BOOT,              C, 9,  GPIO_ODR_HIGH, NULL)
@@ -119,10 +116,11 @@ UNIMPLEMENTED(AP_RESET_L)
 
 #define GPIO_ODR_UP	GPIO_OPEN_DRAIN | GPIO_PULL_UP
 
-ALTERNATE(B, 0x0008, 5, MODULE_USB_PD, 0)            /* SPI1: SCK(PB3) */
-ALTERNATE(B, 0x0002, 2, MODULE_USB_PD, 0)            /* TIM3_CH4: PB1 */
-ALTERNATE(B, 0x00C0, 7, MODULE_USART,  0)            /* USART1: PB6/PB7 */
-ALTERNATE(D, 0x0060, 7, MODULE_UART,   GPIO_PULL_UP) /* USART2: PD4/PD5 */
-ALTERNATE(C, 0x0C00, 7, MODULE_USART,  GPIO_ODR_UP)  /* USART3: PC10/PC11 */
-ALTERNATE(A, 0xC600, 4, MODULE_I2C,    0)            /* I2C SLAVE:PA9/10 MASTER:PA14/15 */
-ALTERNATE(A, 0x1800,14, MODULE_USB,    0)            /* USB: PA11/12 */
+ALTERNATE(B, 0xC400, 5, MODULE_SPI_MASTER, 0)            /* SPI2: PB10/14/15 */
+ALTERNATE(B, 0x0008, 5, MODULE_USB_PD,     0)            /* SPI1: SCK(PB3) */
+ALTERNATE(B, 0x0002, 2, MODULE_USB_PD,     0)            /* TIM3_CH4: PB1 */
+ALTERNATE(B, 0x00C0, 7, MODULE_USART,      0)            /* USART1: PB6/PB7 */
+ALTERNATE(D, 0x0060, 7, MODULE_UART,       GPIO_PULL_UP) /* USART2: PD4/PD5 */
+ALTERNATE(C, 0x0C00, 7, MODULE_USART,      GPIO_ODR_UP)  /* USART3: PC10/PC11 */
+ALTERNATE(A, 0xC600, 4, MODULE_I2C,        0)            /* I2C SLAVE:PA9/10 MASTER:PA14/15 */
+ALTERNATE(A, 0x1800,14, MODULE_USB,        0)            /* USB: PA11/12 */