diff options
| author | Shamile Khan <shamile.khan@intel.com> | 2015-02-09 14:35:24 -0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-04-09 07:49:24 +0000 |
| commit | 0c74006a0af26aa044d7e39b4d836306c306e221 (patch) | |
| tree | 351d68e5653e115f3753867abae88c43c4e8cbcf | |
| parent | 55c739b9a451871f742585ddda491105eef53662 (diff) | |
| download | chrome-ec-0c74006a0af26aa044d7e39b4d836306c306e221.tar.gz | |
mec1322: Enable HW control of KBC aux buffer
This turns on hardware controlled update of bit 5 (AUXOBF) in Keyboard
Status Read Register. Previously, this bit was in user-defined mode and
not reliable.
BUG=None
TEST=Tested that keyboard becomes functional on Braswell Ref Design.
BRANCH=None
Change-Id: I192383ebebb25a027d58da9fc1ef7f3bb3e8da66
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/263948
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Kevin K Wong <kevin.k.wong@intel.com>
| -rw-r--r-- | chip/mec1322/lpc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index e9080041c9..c746374a39 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -212,6 +212,10 @@ static void setup_lpc(void) /* Set up 8042 interface at 0x60/0x64 */ MEC1322_LPC_8042_BAR = 0x00608104; + + /* Set up indication of Auxillary sts */ + MEC1322_8042_KB_CTRL |= 1 << 7; + MEC1322_8042_ACT |= 1; MEC1322_INT_ENABLE(15) |= ((1 << 13) | (1 << 14)); MEC1322_INT_BLK_EN |= 1 << 15; |