diff options
| author | Todd Broch <tbroch@chromium.org> | 2015-03-30 15:39:00 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-04-13 17:38:11 +0000 |
| commit | 0016de8250807601f46fb3736f93518155eca95f (patch) | |
| tree | 6294c39ce7241c9caeea8445381365c15a27678a | |
| parent | 0f6335451dba025328fd0a6ad3da79d57405135b (diff) | |
| download | chrome-ec-0016de8250807601f46fb3736f93518155eca95f.tar.gz | |
plankton: Initialize re-driver.
Host's single lane training algorithm in kernel (intel_dp_is_reversed)
appears to confuse the re-driver's auto training algorithm. If
however its manually configured the algorithm succeeds.
NOTE, this does present risk on the DPsrc (re-driver) to DPsink
(external monitor) side as voltage levels & pre-emphasis will NOT be
adjusted.
This may be acceptable in the short-term while determining if
additional functionality needs to be added on host side to account for
re-driver's presence
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=chrome-os-partner:35153
TEST=manual, plankton drives 4K monitor in both polarities
Change-Id: I83ea80c44d36ad1afad56528c80ec5b8a138b5be
Reviewed-on: https://chromium-review.googlesource.com/263138
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
| -rw-r--r-- | board/plankton/board.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/board/plankton/board.c b/board/plankton/board.c index b6c9c666ca..ebdd85f722 100644 --- a/board/plankton/board.c +++ b/board/plankton/board.c @@ -163,6 +163,30 @@ const struct i2c_port_t i2c_ports[] = { }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); +/* 8-bit address */ +#define SN75DP130_I2C_ADDR 0x5c + +static void sn75dp130_redriver_init(void) +{ + int i; + + /* Disable squelch detect */ + i2c_write8(1, SN75DP130_I2C_ADDR, 0x3, 0x1a); + /* Disable link training on re-driver source side */ + i2c_write8(1, SN75DP130_I2C_ADDR, 0x4, 0x0); + + /* + * Force Link voltage level & pre-emphasis by writing each of the lane's + * DPCD config registers 103-106h accordingly. + */ + i2c_write8(1, SN75DP130_I2C_ADDR, 0x1c, 0x0); + i2c_write8(1, SN75DP130_I2C_ADDR, 0x1d, 0x1); + for (i = 0x3; i < 0x7; i++) { + i2c_write8(1, SN75DP130_I2C_ADDR, 0x1e, i); + i2c_write8(1, SN75DP130_I2C_ADDR, 0x1f, 0x3); + } +} + static void board_init(void) { /* Enable interrupts on VBUS transitions. */ @@ -177,6 +201,7 @@ static void board_init(void) gpio_enable_interrupt(GPIO_DBG_MUX_FLIP_L); ina2xx_init(0, 0x399f, INA2XX_CALIB_1MA(10 /* mOhm */)); + sn75dp130_redriver_init(); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); |