oak_pd: add initial support for oak PD

Add initial support for Oak PD MCU on rev1 boards.
This does not include USB PD communication.

BUG=none
BRANCH=none
TEST=build and load on oak and get console. test we
resond to host commands from EC using "pdcmd 0 0" on
EC console.

Change-Id: I92045cf0fd682279ada6c286f5399f0e258a6305
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/271828

10 files changed, 371 insertions, 0 deletions

diff --git a/board/oak_pd/Makefile b/board/oak_pd/Makefile
new file mode 120000
index 0000000000..94aaae2c4d
--- /dev/null
+++ b/board/oak_pd/Makefile
@@ -0,0 +1 @@
+../../Makefile
\ No newline at end of file
diff --git a/board/oak_pd/board.c b/board/oak_pd/board.c
new file mode 100644
index 0000000000..4583d9fdc7
--- /dev/null
+++ b/board/oak_pd/board.c
@@ -0,0 +1,108 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* oak_pd board configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+
+void pd_send_ec_int(void)
+{
+	gpio_set_level(GPIO_EC_INT, 0);
+
+	/*
+	 * Delay long enough to guarantee EC see's the change.
+	 * TODO: make sure this delay is sufficient.
+	 */
+	usleep(5);
+
+	gpio_set_level(GPIO_EC_INT, 1);
+}
+
+void vbus0_evt(enum gpio_signal signal)
+{
+#ifdef HAS_TASK_PD_C0
+	task_wake(TASK_ID_PD_C0);
+#endif
+}
+
+void vbus1_evt(enum gpio_signal signal)
+{
+#ifdef HAS_TASK_PD_C1
+	task_wake(TASK_ID_PD_C1);
+#endif
+}
+
+void board_config_pre_init(void)
+{
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= 1 << 0;
+	/*
+	 * the DMA mapping is :
+	 *  Chan 2 : TIM1_CH1  (C0 RX)
+	 *  Chan 3 : SPI1_TX   (C0 TX)
+	 *  Chan 4 : TIM3_CH1  (C1 RX)
+	 *  Chan 5 : SPI2_TX   (C1 TX)
+	 */
+}
+
+#include "gpio_list.h"
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable interrupts on VBUS transitions. */
+	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
+	gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
+
+	/* OAK_PD: TODO: Power management of ARM based system */
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
+	[ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
+	[ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
+	[ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
+	[ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"slave", I2C_PORT_SLAVE, 1000, GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA}
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+void tcpc_alert(void)
+{
+	pd_send_ec_int();
+}
+
+/****************************************************************************/
+/* Console commands */
+static int command_ec_int(int argc, char **argv)
+{
+	pd_send_ec_int();
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ecint, command_ec_int,
+			"",
+			"Toggle EC interrupt line",
+			NULL);
+
diff --git a/board/oak_pd/board.h b/board/oak_pd/board.h
new file mode 100644
index 0000000000..15c8cc5f0e
--- /dev/null
+++ b/board/oak_pd/board.h
@@ -0,0 +1,94 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* oak_pd board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/*
+ * The flash size is only 32kB.
+ * No space for 2 partitions,
+ * put only RW at the beginning of the flash
+ */
+#undef CONFIG_FW_INCLUDE_RO
+#undef CONFIG_RW_MEM_OFF
+#define CONFIG_RW_MEM_OFF 0
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE 0
+/* Fake full size if we had a RO partition */
+#undef CONFIG_FW_IMAGE_SIZE
+#define CONFIG_FW_IMAGE_SIZE (64*1024)
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART1 (PA9/PA10) */
+#undef  CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 1
+
+/* Optional features */
+#define CONFIG_ADC
+#define CONFIG_BOARD_PRE_INIT
+#undef  CONFIG_CMD_I2C_SCAN
+#undef  CONFIG_CMD_I2C_XFER
+#undef  CONFIG_CMD_IDLE_STATS
+#undef  CONFIG_CMD_SHMEM
+#define CONFIG_COMMON_GPIO_SHORTNAMES
+#define CONFIG_CONSOLE_CMDHELP
+#define CONFIG_CONSOLE_HISTORY 3
+#undef  CONFIG_DEBUG_ASSERT
+#define CONFIG_FORCE_CONSOLE_RESUME
+#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP2)
+#undef  CONFIG_HOSTCMD_EVENTS
+#define CONFIG_HW_CRC
+#define CONFIG_I2C
+#undef  CONFIG_LID_SWITCH
+#undef  CONFIG_LOW_POWER_IDLE
+#define CONFIG_STM_HWTIMER32
+#undef  CONFIG_TASK_PROFILING
+#undef  CONFIG_UART_TX_BUF_SIZE
+#undef  CONFIG_UART_TX_DMA
+#undef  CONFIG_UART_RX_DMA
+#define CONFIG_UART_TX_BUF_SIZE 128
+#define CONFIG_VBOOT_HASH
+#undef  CONFIG_WATCHDOG
+#undef  CONFIG_WATCHDOG_HELP
+
+/* Use PSTATE embedded in the RO image, not in its own erase block */
+#undef  CONFIG_FLASH_PSTATE_BANK
+#undef  CONFIG_FW_PSTATE_SIZE
+#define CONFIG_FW_PSTATE_SIZE 0
+
+/* I2C ports configuration */
+#define I2C_PORT_SLAVE  0
+#define I2C_PORT_EC I2C_PORT_SLAVE
+
+/* slave address for host commands */
+#ifdef HAS_TASK_HOSTCMD
+#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR CONFIG_USB_PD_I2C_SLAVE_ADDR
+#endif
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_ADC     3
+
+#include "gpio_signal.h"
+
+/* ADC signal */
+enum adc_channel {
+	ADC_C1_CC1_PD = 0,
+	ADC_C0_CC1_PD,
+	ADC_C0_CC2_PD,
+	ADC_C1_CC2_PD,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
diff --git a/board/oak_pd/build.mk b/board/oak_pd/build.mk
new file mode 100644
index 0000000000..392c3026e3
--- /dev/null
+++ b/board/oak_pd/build.mk
@@ -0,0 +1,13 @@
+# -*- makefile -*-
+# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F051C8T
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f05x
+
+board-y=board.o
diff --git a/board/oak_pd/ec.tasklist b/board/oak_pd/ec.tasklist
new file mode 100644
index 0000000000..c5b5933dd8
--- /dev/null
+++ b/board/oak_pd/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/oak_pd/gpio.inc b/board/oak_pd/gpio.inc
new file mode 100644
index 0000000000..542f887f35
--- /dev/null
+++ b/board/oak_pd/gpio.inc
@@ -0,0 +1,64 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupts */
+GPIO_INT(USB_C0_VBUS_WAKE_L,     PIN(C, 14),  GPIO_INT_BOTH,    vbus0_evt)
+GPIO_INT(USB_C1_VBUS_WAKE_L,     PIN(C, 15),  GPIO_INT_BOTH,    vbus1_evt)
+
+/* PD RX/TX */
+GPIO(USB_C0_CC1_PD,          PIN(A, 2),  GPIO_ANALOG)
+GPIO(USB_C_REF,              PIN(A, 1),  GPIO_ANALOG)
+GPIO(USB_C1_CC1_PD,          PIN(A, 0),  GPIO_ANALOG)
+GPIO(USB_C0_CC2_PD,          PIN(A, 4),  GPIO_ANALOG)
+GPIO(USB_C1_CC2_PD,          PIN(A, 5),  GPIO_ANALOG)
+
+GPIO(USB_C1_CCX_TX_DATA,     PIN(B, 14), GPIO_INPUT)
+GPIO(USB_C0_CC1_TX_DATA,     PIN(B, 4),  GPIO_INPUT)
+GPIO(USB_C1_CC2_TX_SEL,      PIN(B, 0),  GPIO_OUT_LOW) /* C1_CC2_TX_SEL */
+GPIO(USB_C0_CC2_TX_DATA,     PIN(A, 6),  GPIO_INPUT)
+GPIO(USB_PD_VBUS_WAKE,       PIN(C, 13), GPIO_INPUT)
+
+GPIO(PP3300_USB_PD_EN,     PIN(A, 15), GPIO_OUT_HIGH)
+GPIO(USB_C0_CC1_VCONN1_EN, PIN(B, 1),  GPIO_OUT_LOW)
+GPIO(USB_C0_CC2_VCONN1_EN, PIN(B, 2),  GPIO_OUT_LOW)
+GPIO(USB_C1_CC1_VCONN1_EN, PIN(B, 9),  GPIO_OUT_LOW)
+GPIO(USB_C1_CC2_VCONN1_EN, PIN(F, 0),  GPIO_OUT_LOW)
+
+GPIO(USB_C0_HOST_HIGH,       PIN(A, 3),  GPIO_OUT_LOW)
+GPIO(USB_C1_HOST_HIGH,       PIN(A, 7),  GPIO_OUT_LOW)
+GPIO(USB_C0_CC1_ODL,         PIN(A, 11), GPIO_ODR_LOW)
+GPIO(USB_C0_CC2_ODL,         PIN(A, 12), GPIO_ODR_LOW)
+GPIO(USB_C1_CC1_ODL,         PIN(B, 12), GPIO_ODR_LOW)
+GPIO(USB_C1_CC2_ODL,         PIN(A, 8),  GPIO_ODR_LOW)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(SLAVE_I2C_SCL,          PIN(B, 6),  GPIO_INPUT)
+GPIO(SLAVE_I2C_SDA,          PIN(B, 7),  GPIO_INPUT)
+
+/* Case closed debugging. */
+GPIO(EC_INT,                 PIN(A, 14), GPIO_OUT_HIGH)
+GPIO(TP_194,                 PIN(B, 5),  GPIO_OUT_LOW)
+UNIMPLEMENTED(WP_L)
+UNIMPLEMENTED(ENTERING_RW)
+
+#if 0
+/* Alternate functions */
+GPIO(USB_C1_TX_CLKOUT,       PIN(B, 15), GPIO_OUT_LOW)
+GPIO(USB_C0_TX_CLKOUT,       PIN(B, 8),  GPIO_OUT_LOW)
+GPIO(USB_C1_TX_CLKIN,        PIN(B, 13), GPIO_OUT_LOW)
+GPIO(USB_C0_TX_CLKIN,        PIN(B, 3),  GPIO_OUT_LOW)
+#endif
+
+ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
+ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */
+ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8   */
+ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15  */
+ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART,   0) /* USART1: PA9/PA10 */
+ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C,    0) /* I2C SLAVE:PB6/7  */
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c
index 3586b64a5c..8940577f94 100644
--- a/chip/stm32/clock-stm32f0.c
+++ b/chip/stm32/clock-stm32f0.c
@@ -46,6 +46,8 @@ static int dsleep_recovery_margin_us = 1000000;
  */
 #ifdef CHIP_VARIANT_STM32F373
 #define STOP_MODE_LATENCY 500  /* us */
+#elif defined(CHIP_VARIANT_STM32F05X)
+#define STOP_MODE_LATENCY 300  /* us */
 #elif (CPU_CLOCK == PLL_CLOCK)
 #define STOP_MODE_LATENCY 300   /* us */
 #else
@@ -245,6 +247,45 @@ static void config_hispeed_clock(void)
 	/* Wait until the PLL is the clock source */
 	while ((STM32_RCC_CFGR & 0xc) != 0x8)
 		;
+#elif defined(CHIP_VARIANT_STM32F05X)
+	/* If PLL is the clock source, PLL has already been set up. */
+	if ((STM32_RCC_CFGR & 0xc) == 0x8)
+		return;
+
+	/* Ensure that HSI is ON */
+	if (!(STM32_RCC_CR & (1<<1))) {
+		/* Enable HSI */
+		STM32_RCC_CR |= (1<<0);
+		/* Wait for HSI to be ready */
+		while (!(STM32_RCC_CR & (1<<1)))
+			;
+	}
+
+	/*
+	 * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz
+	 * therefore PCLK = FCLK = SYSCLK = 48MHz
+	 */
+	/* Switch the PLL source to HSI/2 */
+	STM32_RCC_CFGR &= ~(0x00018000);
+
+	/*
+	 * Specify HSI/2 clock as input clock to PLL and set PLL (*12).
+	 */
+	STM32_RCC_CFGR |= 0x00280000;
+
+	/* Enable the PLL. */
+	STM32_RCC_CR |= 0x01000000;
+
+	/* Wait until PLL is ready. */
+	while (!(STM32_RCC_CR & 0x02000000))
+		;
+
+	/* Switch SYSCLK to PLL. */
+	STM32_RCC_CFGR |= 0x2;
+
+	/* wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
 #else
 	/* Ensure that HSI48 is ON */
 	if (!(STM32_RCC_CR2 & (1 << 17))) {
diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h
new file mode 100644
index 0000000000..9b1701a407
--- /dev/null
+++ b/chip/stm32/config-stm32f05x.h
@@ -0,0 +1,24 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Memory mapping */
+#define CONFIG_FLASH_BASE       0x08000000
+#define CONFIG_FLASH_PHYSICAL_SIZE (64 * 1024)
+#define CONFIG_FLASH_BANK_SIZE  0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+
+/* No page mode on STM32F, so no benefit to larger write sizes */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
+
+#define CONFIG_RAM_BASE         0x20000000
+#define CONFIG_RAM_SIZE         0x00002000
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT 32
+
+/* Reduced history because of limited RAM */
+#undef CONFIG_CONSOLE_HISTORY
+#define CONFIG_CONSOLE_HISTORY 3
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index 88c080dc59..976e929b6e 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -36,6 +36,9 @@
 #elif defined(CHIP_VARIANT_STM32F07X)
 /* STM32F07xx */
 #include "config-stm32f07x.h"
+#elif defined(CHIP_VARIANT_STM32F05X)
+/* STM32F05xx */
+#include "config-stm32f05x.h"
 #elif defined(CHIP_VARIANT_STM32F03X)
 /* STM32F03x */
 #include "config-stm32f03x.h"
diff --git a/test/build.mk b/test/build.mk
index b138a94683..2742b371c4 100644
--- a/test/build.mk
+++ b/test/build.mk
@@ -28,6 +28,7 @@ test-list-$(BOARD_LLAMA)=
 # For some tests, we are running out of RAM for Samus PD. Disable them for
 # now.
 test-list-$(BOARD_SAMUS_PD)=
+test-list-$(BOARD_OAK_PD)=
 
 # Emulator tests
 test-list-host=mutex pingpong utils kb_scan kb_mkbp lid_sw power_button hooks