diff options
| author | Alec Berg <alecaberg@chromium.org> | 2015-06-12 15:05:25 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-06-13 02:53:12 +0000 |
| commit | 1599e7a6f1734b457e8f35c287c90182189a7461 (patch) | |
| tree | ca1f04adb540f15c126a92727aa17627c014c58a | |
| parent | 181913141d3dacbe6d5050267099e8f8b8de9865 (diff) | |
| download | chrome-ec-1599e7a6f1734b457e8f35c287c90182189a7461.tar.gz | |
glados_pd: oak_pd: fix PD tx_disable timing
Disabling CC TX_DATA needs to be very fast to avoid clocking out
an extra garbage bit at the end of transmit. This change fixes
pd_tx_disable() to disable the TX_DATA line as fast as possible.
BUG=chrome-os-partner:40920
BRANCH=none
TEST=test on glados with scope attached to CC. note before this
change we occasionally get a garbage bit at the end of CC transmit.
With this change, it looks clean.
Change-Id: I86b47881e3846b2e3dd4fc2afcf2d28386a068a6
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277295
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | board/glados_pd/usb_pd_config.h | 34 | ||||
| -rw-r--r-- | board/oak_pd/usb_pd_config.h | 34 |
2 files changed, 36 insertions, 32 deletions
diff --git a/board/glados_pd/usb_pd_config.h b/board/glados_pd/usb_pd_config.h index d704e2a8ae..28f5cff6f9 100644 --- a/board/glados_pd/usb_pd_config.h +++ b/board/glados_pd/usb_pd_config.h @@ -170,32 +170,34 @@ static inline void pd_tx_enable(int port, int polarity) static inline void pd_tx_disable(int port, int polarity) { if (port == 0) { - if (polarity) {/* PA6 is SPI1 MISO */ - /* set ADC PA4 pin to ADC function (Hi-Z) */ + if (polarity) { + /* Set TX_DATA to Hi-Z, PA6 is SPI1 MISO */ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*4))) /* PA4 as ADC */ - & ~(1 << (2*4)); /* disable GPO */ - gpio_set_alternate_function(GPIO_A, 0x0040, -1); - } else {/* PB4 is SPI1 MISO */ + & ~(3 << (2*6))); /* set ADC PA4 pin to ADC function (Hi-Z) */ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*2))) /* PA2 as ADC */ - & ~(1 << (2*2)); /* disable GPO */ - gpio_set_alternate_function(GPIO_B, 0x0010, -1); + | (3 << (2*4))); /* PA4 as ADC */ + } else { + /* Set TX_DATA to Hi-Z, PB4 is SPI1 MISO */ + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) + & ~(3 << (2*4))); + /* set ADC PA2 pin to ADC function (Hi-Z) */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + | (3 << (2*2))); /* PA2 as ADC */ } } else { + /* Set TX_DATA (PB14) Hi-Z */ + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) + & ~(3 << (2*14))); if (polarity) { - /* set ADC PA4 pin to ADC function (Hi-Z) */ + /* set ADC PA5 pin to ADC function (Hi-Z) */ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*5))) /* PA5 as ADC */ - & ~(1 << (2*5)); /* disable GPO */ + | (3 << (2*5))); /* PA5 as ADC */ } else { - /* set ADC PA4 pin to ADC function (Hi-Z) */ + /* set ADC PA0 pin to ADC function (Hi-Z) */ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*0))) /* PA0 as ADC */ - & ~(1 << (2*0)); /* disable GPO */ + | (3 << (2*0))); /* PA0 as ADC */ } - gpio_set_alternate_function(GPIO_B, 0x4000, -1); } } diff --git a/board/oak_pd/usb_pd_config.h b/board/oak_pd/usb_pd_config.h index d704e2a8ae..28f5cff6f9 100644 --- a/board/oak_pd/usb_pd_config.h +++ b/board/oak_pd/usb_pd_config.h @@ -170,32 +170,34 @@ static inline void pd_tx_enable(int port, int polarity) static inline void pd_tx_disable(int port, int polarity) { if (port == 0) { - if (polarity) {/* PA6 is SPI1 MISO */ - /* set ADC PA4 pin to ADC function (Hi-Z) */ + if (polarity) { + /* Set TX_DATA to Hi-Z, PA6 is SPI1 MISO */ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*4))) /* PA4 as ADC */ - & ~(1 << (2*4)); /* disable GPO */ - gpio_set_alternate_function(GPIO_A, 0x0040, -1); - } else {/* PB4 is SPI1 MISO */ + & ~(3 << (2*6))); /* set ADC PA4 pin to ADC function (Hi-Z) */ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*2))) /* PA2 as ADC */ - & ~(1 << (2*2)); /* disable GPO */ - gpio_set_alternate_function(GPIO_B, 0x0010, -1); + | (3 << (2*4))); /* PA4 as ADC */ + } else { + /* Set TX_DATA to Hi-Z, PB4 is SPI1 MISO */ + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) + & ~(3 << (2*4))); + /* set ADC PA2 pin to ADC function (Hi-Z) */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + | (3 << (2*2))); /* PA2 as ADC */ } } else { + /* Set TX_DATA (PB14) Hi-Z */ + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) + & ~(3 << (2*14))); if (polarity) { - /* set ADC PA4 pin to ADC function (Hi-Z) */ + /* set ADC PA5 pin to ADC function (Hi-Z) */ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*5))) /* PA5 as ADC */ - & ~(1 << (2*5)); /* disable GPO */ + | (3 << (2*5))); /* PA5 as ADC */ } else { - /* set ADC PA4 pin to ADC function (Hi-Z) */ + /* set ADC PA0 pin to ADC function (Hi-Z) */ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*0))) /* PA0 as ADC */ - & ~(1 << (2*0)); /* disable GPO */ + | (3 << (2*0))); /* PA0 as ADC */ } - gpio_set_alternate_function(GPIO_B, 0x4000, -1); } } |