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| author | Kumar, Gomathi <gomathi.kumar@intel.com> | 2015-08-07 16:02:28 +0530 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-11 19:52:35 +0000 |
| commit | 3cbc31aec352ab104dc8809d57cec13dfa27aa35 (patch) | |
| tree | d307797456993b2f3e766bfb29a0608027df557b | |
| parent | 3f9ecd30d70e65771b541f250a0e532c14257424 (diff) | |
| download | chrome-ec-3cbc31aec352ab104dc8809d57cec13dfa27aa35.tar.gz | |
strago: Power state transition in case of apshutdown
In case of 'apshutdown', during transition to S5 state,
GPIO_PCH_SLP_S4_L signal was not getting deasserted but
required rail went away (GPIO_PCH_SYS_PWROK). So it was
going on a loop S5 -> S3 and S3 -> S5.
In strago GPIO_PCH_SYS_PWROK is the PMIC_EN GPIO and hence
conditinally setting it based on CONFIG_PMIC
BUG=none
TEST=apshutdown on strago
BRANCH=none
Change-Id: I9c581a3dfcb9cc84a22b41505e7df496d72d5f4c
Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com>
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292024
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | power/braswell.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/power/braswell.c b/power/braswell.c index 50f6c5cbf1..5998e99339 100644 --- a/power/braswell.c +++ b/power/braswell.c @@ -61,7 +61,9 @@ void chipset_force_shutdown(void) * Force power off. This condition will reset once the state machine * transitions to G3. */ +#ifndef CONFIG_PMIC gpio_set_level(GPIO_PCH_SYS_PWROK, 0); +#endif gpio_set_level(GPIO_PCH_RSMRST_L, 0); forcing_shutdown = 1; } @@ -291,6 +293,8 @@ enum power_state power_handle_state(enum power_state state) gpio_config_module(MODULE_GPIO, 1); #ifndef CONFIG_PMIC gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1); +#else + gpio_set_level(GPIO_PCH_SYS_PWROK, 0); #endif forcing_shutdown = 0; |