stm32: Enable 3rd SPI interface

Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.

BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.

Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514

8 files changed, 40 insertions, 22 deletions

diff --git a/board/discovery-stm32f072/board.c b/board/discovery-stm32f072/board.c
index 7aa9a70555..5aa185ffc3 100644
--- a/board/discovery-stm32f072/board.c
+++ b/board/discovery-stm32f072/board.c
@@ -157,7 +157,7 @@ void usb_spi_board_enable(struct usb_spi_config const *config)
 	STM32_SYSCFG_CFGR1 |= (1 << 24);
 
 	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_FLASH, 1);
 
 	/* Set all four SPI pins to high speed */
 	STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
@@ -180,7 +180,7 @@ void usb_spi_board_disable(struct usb_spi_config const *config)
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Release SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_FLASH, 0);
 }
 
 USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI);
diff --git a/board/discovery-stm32f072/gpio.inc b/board/discovery-stm32f072/gpio.inc
index 4311634dc3..14272dcadd 100644
--- a/board/discovery-stm32f072/gpio.inc
+++ b/board/discovery-stm32f072/gpio.inc
@@ -19,7 +19,7 @@ GPIO(SPI_WP,   PIN(C,  3), GPIO_OUT_HIGH)
 GPIO(SPI_HOLD, PIN(C,  4), GPIO_OUT_HIGH)
 GPIO(SPI_CS,   PIN(B, 12), GPIO_OUT_HIGH)
 
-ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_MASTER, 0)
+ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_FLASH, 0)
 
 /* Unimplemented signals which we need to emulate for now */
 UNIMPLEMENTED(ENTERING_RW)
diff --git a/board/ryu/board.c b/board/ryu/board.c
index 43843e653c..4a41366ed6 100644
--- a/board/ryu/board.c
+++ b/board/ryu/board.c
@@ -489,7 +489,7 @@ void usb_spi_board_enable(struct usb_spi_config const *config)
 	gpio_set_level(GPIO_PMIC_WARM_RESET_L, 0);
 
 	/* Configure SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 1);
+	gpio_config_module(MODULE_SPI_FLASH, 1);
 	gpio_set_flags(SPI_FLASH_DEVICE->gpio_cs, GPIO_OUT_HIGH);
 
 	/* Set all four SPI pins to high speed */
@@ -519,7 +519,7 @@ void usb_spi_board_disable(struct usb_spi_config const *config)
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 
 	/* Release SPI GPIOs */
-	gpio_config_module(MODULE_SPI_MASTER, 0);
+	gpio_config_module(MODULE_SPI_FLASH, 0);
 	gpio_set_flags(SPI_FLASH_DEVICE->gpio_cs, GPIO_INPUT);
 
 	/* Release AP from reset */
diff --git a/board/ryu/gpio.inc b/board/ryu/gpio.inc
index 009bfd98a2..45e839c113 100644
--- a/board/ryu/gpio.inc
+++ b/board/ryu/gpio.inc
@@ -130,11 +130,11 @@ UNIMPLEMENTED(AP_RESET_L)
 
 #define GPIO_ODR_UP	GPIO_OPEN_DRAIN | GPIO_PULL_UP
 
-ALTERNATE(PIN_MASK(B, 0xC400), 5, MODULE_SPI_MASTER, 0)            /* SPI2: PB10/14/15 */
-ALTERNATE(PIN_MASK(B, 0x0008), 5, MODULE_USB_PD,     0)            /* SPI1: SCK(PB3) */
-ALTERNATE(PIN_MASK(B, 0x0002), 2, MODULE_USB_PD,     0)            /* TIM3_CH4: PB1 */
-ALTERNATE(PIN_MASK(B, 0x00C0), 7, MODULE_USART,      0)            /* USART1: PB6/PB7 */
-ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART,       GPIO_PULL_UP) /* USART2: PD4/PD5 */
-ALTERNATE(PIN_MASK(C, 0x0C00), 7, MODULE_USART,      GPIO_ODR_UP)  /* USART3: PC10/PC11 */
-ALTERNATE(PIN_MASK(A, 0xC600), 4, MODULE_I2C,        0)            /* I2C SLAVE:PA9/10 MASTER:PA14/15 */
-ALTERNATE(PIN_MASK(A, 0x1800),14, MODULE_USB,        0)            /* USB: PA11/12 */
+ALTERNATE(PIN_MASK(B, 0xC400), 5, MODULE_SPI_FLASH,        0)  /* SPI2: PB10/14/15 */
+ALTERNATE(PIN_MASK(B, 0x0008), 5, MODULE_USB_PD,           0)  /* SPI1: SCK(PB3) */
+ALTERNATE(PIN_MASK(B, 0x0002), 2, MODULE_USB_PD,           0)  /* TIM3_CH4: PB1 */
+ALTERNATE(PIN_MASK(B, 0x00C0), 7, MODULE_USART,            0)  /* USART1: PB6/PB7 */
+ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART,  GPIO_PULL_UP)  /* USART2: PD4/PD5 */
+ALTERNATE(PIN_MASK(C, 0x0C00), 7, MODULE_USART,  GPIO_ODR_UP)  /* USART3: PC10/PC11 */
+ALTERNATE(PIN_MASK(A, 0xC600), 4, MODULE_I2C,              0)  /* I2C SLAVE:PA9/10 MASTER:PA14/15 */
+ALTERNATE(PIN_MASK(A, 0x1800),14, MODULE_USB,              0)  /* USB: PA11/12 */
diff --git a/chip/g/clock.c b/chip/g/clock.c
index 098c6a4aa7..d34caf6a29 100644
--- a/chip/g/clock.c
+++ b/chip/g/clock.c
@@ -28,6 +28,7 @@ void clock_enable_module(enum module_id module, int enable)
 		clock_func(PERIPH_I2C0);
 		clock_func(PERIPH_I2C1);
 		break;
+	case MODULE_SPI_FLASH:
 	case MODULE_SPI_MASTER:
 		clock_func(PERIPH_SPI);
 		break;
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 4970ea5f4b..f9f27f25f5 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -605,6 +605,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32_RCC_PB1_WWDG		(1 << 11)
 #define STM32_RCC_PB1_IWDG		(1 << 12) /* DBGMCU only */
 #define STM32_RCC_PB1_SPI2		(1 << 14)
+#define STM32_RCC_PB1_SPI3		(1 << 15)
 #define STM32_RCC_PB1_USART2		(1 << 17)
 #define STM32_RCC_PB1_USART3		(1 << 18)
 #define STM32_RCC_PB1_USART4		(1 << 19)
@@ -681,9 +682,6 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32_SPI2_BASE             0x40003800
 #define STM32_SPI3_BASE             0x40003c00 /* STM32F373 */
 
-#define STM32_SPI1_PORT             0
-#define STM32_SPI2_PORT             1
-
 /* The SPI controller registers */
 struct stm32_spi_regs {
 	uint16_t cr1;
@@ -705,6 +703,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 
 #define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
 #define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE)
+#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 
 #define STM32_SPI_CR1_BIDIMODE		(1 << 15)
 #define STM32_SPI_CR1_BIDIOE		(1 << 14)
@@ -1160,6 +1159,8 @@ enum dma_channel {
 #ifdef CHIP_VARIANT_STM32F373
 	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
 	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
+	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
+	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
 
 	STM32_DMAC_COUNT = 10,
 #else
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c
index 858fede3f0..26d279f19c 100644
--- a/chip/stm32/spi_master.c
+++ b/chip/stm32/spi_master.c
@@ -17,6 +17,9 @@
 /* The second (and third if available) SPI port are used as master */
 static stm32_spi_regs_t *SPI_REGS[] = {
 	STM32_SPI2_REGS,
+#ifdef CHIP_VARIANT_STM32F373
+	STM32_SPI3_REGS,
+#endif
 };
 
 #define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
@@ -27,6 +30,12 @@ static const struct dma_option dma_tx_option[] = {
 		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr,
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 	},
+#ifdef CHIP_VARIANT_STM32F373
+	{
+		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
+		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
+	},
+#endif
 };
 
 static const struct dma_option dma_rx_option[] = {
@@ -34,6 +43,12 @@ static const struct dma_option dma_rx_option[] = {
 		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr,
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 	},
+#ifdef CHIP_VARIANT_STM32F373
+	{
+		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
+		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
+	},
+#endif
 };
 
 static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
diff --git a/include/module_id.h b/include/module_id.h
index 0a58eaab78..bc1ef0ab09 100644
--- a/include/module_id.h
+++ b/include/module_id.h
@@ -35,18 +35,19 @@ enum module_id {
 	MODULE_PWM_KBLIGHT,
 	MODULE_PWM_LED,
 	MODULE_SPI,
-	MODULE_SPI_MASTER,
-	MODULE_SWITCH,	/* 25 */
+	MODULE_SPI_FLASH,
+	MODULE_SPI_MASTER,	/* 25 */
+	MODULE_SWITCH,
 	MODULE_SYSTEM,
 	MODULE_TASK,
 	MODULE_THERMAL,
-	MODULE_UART,
-	MODULE_USART,	/* 30 */
+	MODULE_UART,	/* 30 */
+	MODULE_USART,
 	MODULE_USB,
 	MODULE_USB_DEBUG,
 	MODULE_USB_PD,
-	MODULE_USB_PORT_POWER,
-	MODULE_USB_SWITCH,	/* 35 */
+	MODULE_USB_PORT_POWER,	/* 35 */
+	MODULE_USB_SWITCH,
 	MODULE_VBOOT,
 
 	/* Module count; not an actual module */