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authorBill Richardson <wfrichar@chromium.org>2015-09-02 11:25:01 -0700
committerchrome-bot <chrome-bot@chromium.org>2015-09-03 15:11:45 -0700
commitab8cad32ee1537521ba49916a05d7b7e1fb2417c (patch)
tree8249bad9d8e9ccaea6916a8724ffc4cb9c06767c
parent229bac23f15a7636ccb25b6861655e3e0923a0e9 (diff)
downloadchrome-ec-ab8cad32ee1537521ba49916a05d7b7e1fb2417c.tar.gz
Update some TODO comments.
BUG=chrome-os-partner:44803 BRANCH=none TEST=make buildall Comment change only. Change-Id: I68c2fba64b7f613e3936f4e7ddf6b48430c7b858 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297021 Reviewed-by: Randall Spangler <rspangler@chromium.org>
-rw-r--r--chip/g/config_chip.h4
-rw-r--r--common/rwsig.c1
2 files changed, 1 insertions, 4 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h
index 807c8f82c2..9e763d1822 100644
--- a/chip/g/config_chip.h
+++ b/chip/g/config_chip.h
@@ -17,7 +17,6 @@
#define CONFIG_RAM_SIZE 0x10000
/* Flash chip specifics */
-/* TODO(crosbug.com/p/33815): These are probably wrong. Don't use them yet. */
#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */
#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */
#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
@@ -25,9 +24,6 @@
/* Describe the flash layout */
#define CONFIG_FLASH_BASE 0x40000
-/* TODO(wfrichar): Lying about this, so image signing works.
- * I'll file a bug once this CL goes in. */
-/* #define CONFIG_FLASH_PHYSICAL_SIZE (512 * 1024) */
#define CONFIG_FLASH_PHYSICAL_SIZE (512 * 1024)
/* Compute the rest of the flash params from these */
diff --git a/common/rwsig.c b/common/rwsig.c
index e3224c1df8..ef86c19c23 100644
--- a/common/rwsig.c
+++ b/common/rwsig.c
@@ -57,6 +57,7 @@ void check_rw_signature(void)
}
/* SHA-256 Hash of the RW firmware */
+ /* TODO(crosbug.com/p/44803): Do we have to hash the whole region? */
SHA256_init(&ctx);
SHA256_update(&ctx, (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF,
CONFIG_RW_SIZE - RSANUMBYTES);