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authorShawn Nematbakhsh <shawnn@chromium.org>2015-09-22 18:44:13 -0700
committerchrome-bot <chrome-bot@chromium.org>2015-09-24 18:07:01 -0700
commit854d5a6e7fa47e44797891e6fad392a344003b46 (patch)
tree5a2fd4137eb9660ef5c4d459b88d20f987498fd7
parent324d6b807f18c456c16dad534f88ef22da34fdc5 (diff)
downloadchrome-ec-854d5a6e7fa47e44797891e6fad392a344003b46.tar.gz
cleanup: Remove CONFIG_FW_IMAGE_SIZE
Since CONFIG_RO_SIZE and CONFIG_RW_SIZE now exist (which may theoretically be different sizes), it is no longer useful to globally define the size of an image. BUG=chromium:535027 BRANCH=None TEST=`make buildall -j`. Also, verify glados / glados_pd continue to function as expected. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie29959923bc5d02b4d7d6d507ff2191bcb7d24c8 Reviewed-on: https://chromium-review.googlesource.com/301743 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
-rw-r--r--board/glados_pd/board.h4
-rw-r--r--board/oak_pd/board.h4
-rw-r--r--chip/mec1322/config_flash_layout.h8
-rw-r--r--chip/mec1322/lfw/ec_lfw.c5
-rw-r--r--chip/npcx/config_flash_layout.h9
-rw-r--r--core/cortex-m/mpu.c2
-rw-r--r--include/config.h1
-rw-r--r--include/config_std_internal_flash.h22
8 files changed, 24 insertions, 31 deletions
diff --git a/board/glados_pd/board.h b/board/glados_pd/board.h
index ce265028c4..fe0eecc07f 100644
--- a/board/glados_pd/board.h
+++ b/board/glados_pd/board.h
@@ -19,8 +19,8 @@
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE 0
/* Fake full size if we had a RO partition */
-#undef CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_IMAGE_SIZE (64*1024)
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
diff --git a/board/oak_pd/board.h b/board/oak_pd/board.h
index c2c1818323..52fb775c78 100644
--- a/board/oak_pd/board.h
+++ b/board/oak_pd/board.h
@@ -21,8 +21,8 @@
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE 0
/* Fake full size if we had a RO partition */
-#undef CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_IMAGE_SIZE (64*1024)
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
index 4822329ae3..e79dd8b70e 100644
--- a/chip/mec1322/config_flash_layout.h
+++ b/chip/mec1322/config_flash_layout.h
@@ -26,12 +26,6 @@
#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x40000)
#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
-
-/* Size of one firmware image in flash */
-#ifndef CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_IMAGE_SIZE (96 * 1024)
-#endif
-
/* Loader resides at the beginning of program memory */
#define CONFIG_LOADER_MEM_OFF 0
#define CONFIG_LOADER_SIZE 0x1000
@@ -50,7 +44,7 @@
*/
#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \
CONFIG_LOADER_SIZE)
-#define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_SIZE (96 * 1024)
#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
#define CONFIG_RW_SIZE CONFIG_RO_SIZE
diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
index 8dffa6da72..3bb3e31398 100644
--- a/chip/mec1322/lfw/ec_lfw.c
+++ b/chip/mec1322/lfw/ec_lfw.c
@@ -95,9 +95,10 @@ int spi_image_load(uint32_t offset)
CONFIG_PROGRAM_MEMORY_BASE);
uint32_t i;
- memset((void *)buf, 0xFF, (CONFIG_FW_IMAGE_SIZE - 4));
+ BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE);
+ memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4));
- for (i = 0; i < CONFIG_FW_IMAGE_SIZE; i += SPI_CHUNK_SIZE)
+ for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE)
spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
return 0;
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index 60e9795890..497be03089 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -31,11 +31,6 @@
#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000
#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
-/* Size of one firmware image in flash */
-#ifndef CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_IMAGE_SIZE (96 * 1024) /* 96 KB for FW images */
-#endif
-
/* Header support which is used by booter to copy FW from flash to code ram */
#define NPCX_RO_HEADER
#define CONFIG_RO_HDR_MEM_OFF 0x0
@@ -46,11 +41,11 @@
/* RO firmware offset in flash */
#define CONFIG_RO_MEM_OFF 0
-#define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE /* 96KB for RW FW */
+#define CONFIG_RO_SIZE (96 * 1024) /* 96KB for RO FW */
/* RW firmware offset in flash */
#define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE /* 96KB for RW FW */
+#define CONFIG_RW_SIZE (96 * 1024) /* 96KB for RW FW */
/* The storage offset of ec.R*.flat which is used for firmware_image.lds */
#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c
index 8cdf4c9194..e49a8d533d 100644
--- a/core/cortex-m/mpu.c
+++ b/core/cortex-m/mpu.c
@@ -141,7 +141,7 @@ int mpu_protect_ram(void)
int mpu_lock_ro_flash(void)
{
return mpu_lock_region(REGION_FLASH_MEMORY, CONFIG_RO_MEM_OFF,
- CONFIG_FW_IMAGE_SIZE, MPU_ATTR_FLASH_MEMORY);
+ CONFIG_RO_SIZE, MPU_ATTR_FLASH_MEMORY);
}
int mpu_lock_rw_flash(void)
diff --git a/include/config.h b/include/config.h
index 5e3a78e345..1094c89f11 100644
--- a/include/config.h
+++ b/include/config.h
@@ -774,7 +774,6 @@
/*****************************************************************************/
/* Firmware region configuration */
-#undef CONFIG_FW_IMAGE_SIZE
#undef CONFIG_FW_PSTATE_OFF
#undef CONFIG_FW_PSTATE_SIZE
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h
index cfe31773ea..4b722f86d9 100644
--- a/include/config_std_internal_flash.h
+++ b/include/config_std_internal_flash.h
@@ -33,34 +33,38 @@
*/
/*
+ * Size of one firmware image in flash - half for RO, half for RW.
+ * This is NOT a globally defined config, and is only used in this file
+ * for convenience.
+ */
+#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE - \
+ CONFIG_SHAREDLIB_SIZE) / 2)
+
+/*
* The EC uses the one bank of flash to emulate a SPI-like write protect
* register with persistent state.
*/
#define CONFIG_FLASH_PSTATE
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE ((CONFIG_FLASH_SIZE - \
- CONFIG_SHAREDLIB_SIZE) / 2)
+#define CONFIG_FW_PSTATE_OFF (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
/*
* By default, there is no shared objects library. However, if configured, the
* shared objects library will be placed after the RO image.
*/
#define CONFIG_SHAREDLIB_MEM_OFF (CONFIG_RO_MEM_OFF + \
- CONFIG_FW_IMAGE_SIZE)
+ _IMAGE_SIZE)
#define CONFIG_SHAREDLIB_STORAGE_OFF (CONFIG_RO_STORAGE_OFF + \
- CONFIG_FW_IMAGE_SIZE)
+ _IMAGE_SIZE)
#define CONFIG_SHAREDLIB_SIZE 0
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_STORAGE_OFF 0
-#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RO_SIZE (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF (CONFIG_SHAREDLIB_MEM_OFF + \
CONFIG_SHAREDLIB_SIZE)
#define CONFIG_RW_STORAGE_OFF 0
-#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE _IMAGE_SIZE
#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF