summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorli feng <li1.feng@intel.com>2015-10-30 17:36:32 -0700
committerchrome-bot <chrome-bot@chromium.org>2015-11-04 07:09:07 -0800
commit7e31d2650b2c5c56303dd086e53d35cd9b594a1c (patch)
tree30e1fed68165e752e142ddcedcfd5f6f8ace6496
parent1915367112b82a2311e4938e25aee38736af44d0 (diff)
downloadchrome-ec-7e31d2650b2c5c56303dd086e53d35cd9b594a1c.tar.gz
mec1322: reduce system stack size
Reduce system stack size from 4096 to 1024. Increase code RAM size to 104K and reduce data RAM size to 20K. BUG=chrome-os-partner:45690 BRANCH=None TEST=Tested on Kunimitsu 1. Flash EC, boot up, force to S5/G3, back to S0; and powerd_dbus_suspend to S3, all work fine. 2. Use console command to dump system stack memory values, the size used is around 350, >600 still available. Change-Id: Ib004678cc16f10c94c333063b728a2816ed5b3c5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/310581 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
-rw-r--r--board/glados/board.h2
-rw-r--r--board/kunimitsu/board.h2
-rw-r--r--chip/mec1322/config_chip.h17
3 files changed, 10 insertions, 11 deletions
diff --git a/board/glados/board.h b/board/glados/board.h
index e44d0dd96a..b9d0a48255 100644
--- a/board/glados/board.h
+++ b/board/glados/board.h
@@ -53,7 +53,7 @@
#define CONFIG_POWER_COMMON
/* All data won't fit in data RAM. So, moving boundary slightly. */
#undef CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE (100 * 1024)
+#define CONFIG_RO_SIZE (104 * 1024)
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
/* We're space constrained on GLaDOS, so reduce the UART TX buffer size. */
#undef CONFIG_UART_TX_BUF_SIZE
diff --git a/board/kunimitsu/board.h b/board/kunimitsu/board.h
index a58fed90b1..6783315c09 100644
--- a/board/kunimitsu/board.h
+++ b/board/kunimitsu/board.h
@@ -75,7 +75,7 @@
#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
/* All data won't fit in data RAM. So, moving boundary slightly. */
#undef CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE (100 * 1024)
+#define CONFIG_RO_SIZE (104 * 1024)
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
/* We're space constrained on Kunimitsu, so reduce the UART TX buffer size. */
#undef CONFIG_UART_TX_BUF_SIZE
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index f81069f753..08f041f3ce 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -37,13 +37,12 @@
/*
* The memory region for RAM is actually 0x00100000-0x00120000.
- * RAM for Loader = 2k
- * RAM for RO/RW = 24k
- * CODE size of the Loader is 4k
- * As per the above configuartion the upper 26k
+ * RAM for RO/RW = 20k
+ * CODE size of the Loader is 3k
+ * As per the above configuartion the upper 20k
* is used to store data.The rest is for code.
- * the lower 100K is flash[ 4k Loader and 96k RO/RW],
- * and the higher 26K is RAM shared by loader and RO/RW.
+ * the lower 107K is flash[ 3k Loader and 104k RO/RW],
+ * and the higher 20K is RAM shared by loader and RO/RW.
*/
/****************************************************************************/
@@ -54,13 +53,13 @@
#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \
CONFIG_MEC_SRAM_BASE_START)
-/* 24k RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE 0x00006000
+/* 20k RAM for RO / RW / loader */
+#define CONFIG_RAM_SIZE 0x00005000
#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \
CONFIG_RAM_SIZE)
/* System stack size */
-#define CONFIG_STACK_SIZE 4096
+#define CONFIG_STACK_SIZE 1024
/* non-standard task stack sizes */
#define IDLE_TASK_STACK_SIZE 512