diff options
| author | Ben Lok <ben.lok@mediatek.com> | 2015-10-20 19:48:29 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-28 11:45:08 -0700 |
| commit | b347f36b1053342c50990cdc9c711df9ee093af6 (patch) | |
| tree | 503b9e5a0a6e510977e2d56005733d3d294b15d0 | |
| parent | b86e256fb7c73a51662038253de2deb7b4799f42 (diff) | |
| download | chrome-ec-b347f36b1053342c50990cdc9c711df9ee093af6.tar.gz | |
oak: ensure PMIC power button is released after SYSJUMP.
There is a race condition between SYSJUMP and function
release_pmic_pwron_deferred().
Process of EC SW Sync will delay the execution time of
release_pmic_pwron_deferred(). PMIC will shutdown the power, if
PMIC power button can not be released within 8 seconds (depends
on PMIC spec). In order to ensure PMIC power button will be
released in time, just release it after SYSJUMP.
BUG=chrome-os-partner:46392
BUG=chrome-os-partner:46656
BRANCH=none
TEST=make buildall -j;
Enable EC SW sync and normal mode in coreboot,
Kernel should bootup successfully.
Change-Id: I45d4aa0f0d4280e68282ea11ccfda05201f88aae
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/307220
Reviewed-by: Rong Chang <rongchang@chromium.org>
| -rw-r--r-- | power/mediatek.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/power/mediatek.c b/power/mediatek.c index 90a23aa2d4..49b9154edf 100644 --- a/power/mediatek.c +++ b/power/mediatek.c @@ -416,6 +416,14 @@ enum power_state power_chipset_init(void) /* In the SYSJUMP case, we check if the AP is on */ if (is_power_good_asserted()) { CPRINTS("SOC ON"); + /* + * Check and release PMIC power button signal, + * if it's deferred callback function is not triggered + * in RO before SYSJUMP. + */ + if (gpio_get_level(GPIO_PMIC_PWRON_H)) + set_pmic_pwron(0); + init_power_state = POWER_S0; if (is_suspend_asserted()) enable_sleep(SLEEP_MASK_AP_RUN); |