diff options
| author | Dino Li <dino.li@ite.com.tw> | 2015-12-14 17:10:44 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-12-14 20:04:53 -0800 |
| commit | 313f2ab8c5cf2c1cf52c7316ed8600894b4fc977 (patch) | |
| tree | 50865b2239e30128a29fdaf28ad37a83d4a502b9 | |
| parent | a6e82c3acd1d132f5ebd918465a0e852247a207e (diff) | |
| download | chrome-ec-313f2ab8c5cf2c1cf52c7316ed8600894b4fc977.tar.gz | |
it8380dev: To config register 'GCR' in gpio_pre_init()
The double-mapping modules(CIR, BRAM, SSPI, PECI, and UART) won't work
if GPD2 pin's status is low and GCR register's setting is at default.
We move 'IT83XX_GPIO_GCR = 0x06;' to 'gpio_pre_init()'
to prevent this case.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Register 'GCR'=0x6 after init.
2. GPD2 is low and UART works.
Change-Id: I71b4436ab6c2a8f9e77e0d6f5116e5327a3167e7
Reviewed-on: https://chromium-review.googlesource.com/318131
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | chip/it83xx/gpio.c | 2 | ||||
| -rw-r--r-- | chip/it83xx/lpc.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index cf0e51a727..ea29ace11c 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -395,6 +395,8 @@ void gpio_pre_init(void) int flags; int i; + IT83XX_GPIO_GCR = 0x06; + for (i = 0; i < GPIO_COUNT; i++, g++) { flags = g->flags; diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c index 3f7dc82a57..02a81c2bd0 100644 --- a/chip/it83xx/lpc.c +++ b/chip/it83xx/lpc.c @@ -572,8 +572,6 @@ static void lpc_init(void) */ IT83XX_GCTRL_MCCR2 |= 0x10; - IT83XX_GPIO_GCR = 0x06; - /* The register pair to access PNPCFG is 004Eh and 004Fh */ IT83XX_GCTRL_BADRSEL = 0x01; |