diff options
author | Ryan Zhang <Ryan.Zhang@quantatw.com> | 2015-12-02 21:07:53 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2015-12-06 19:00:51 -0800 |
commit | 5c8edccb941bf7fa76fac7a6cf3b16c1c0765577 (patch) | |
tree | 0f3c8b9b70955f9ec3b70baf40f1c32fd9e17788 | |
parent | a9d7417951efb95cb2c076791b0bea6d4e4d62e2 (diff) | |
download | chrome-ec-5c8edccb941bf7fa76fac7a6cf3b16c1c0765577.tar.gz |
Lars: Remove second port of PD firmware
two port PD will keep interrupt low, and cause
EC.PDCMD task stuck with exchange status loop before
entering task-while-loop
BUG=chrome-os-partner:48232
BRANCH=lars
TEST=`make BOARD=lars -j`, OS can boot up normally
Change-Id: I493c6d02170c731af430f28abf8ade38b47aff0f
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/315362
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
-rw-r--r-- | board/lars_pd/board.c | 9 | ||||
-rw-r--r-- | board/lars_pd/board.h | 6 | ||||
-rw-r--r-- | board/lars_pd/ec.tasklist | 3 | ||||
-rw-r--r-- | board/lars_pd/gpio.inc | 18 | ||||
-rw-r--r-- | board/lars_pd/usb_pd_config.h | 119 |
5 files changed, 19 insertions, 136 deletions
diff --git a/board/lars_pd/board.c b/board/lars_pd/board.c index 3dd7950759..1354e03b24 100644 --- a/board/lars_pd/board.c +++ b/board/lars_pd/board.c @@ -53,7 +53,6 @@ static void board_init(void) { /* Enable interrupts on VBUS transitions. */ gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L); - gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L); /* Set PD MCU system status bits */ if (system_jumped_to_this_image()) @@ -66,10 +65,8 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(0)}, [ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(2)}, [ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)}, - [ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)}, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -86,8 +83,7 @@ void tcpc_alert(int port) * bits in the Alert register and that bit's corresponding * location in the Alert_Mask register is set. */ - atomic_or(&ec_int_status, port ? - PD_STATUS_TCPC_ALERT_1 : PD_STATUS_TCPC_ALERT_0); + atomic_or(&ec_int_status, PD_STATUS_TCPC_ALERT_0); pd_send_ec_int(); } @@ -98,8 +94,7 @@ void tcpc_alert_clear(int port) * Alert# line needs to be set inactive. Clear * the corresponding port's bit in the static variable. */ - atomic_clear(&ec_int_status, port ? - PD_STATUS_TCPC_ALERT_1 : PD_STATUS_TCPC_ALERT_0); + atomic_clear(&ec_int_status, PD_STATUS_TCPC_ALERT_0); pd_send_ec_int(); } diff --git a/board/lars_pd/board.h b/board/lars_pd/board.h index 6831979149..8069ec89f7 100644 --- a/board/lars_pd/board.h +++ b/board/lars_pd/board.h @@ -61,7 +61,7 @@ #define CONFIG_UART_TX_BUF_SIZE 128 #define CONFIG_USB_PD_DUAL_ROLE #define CONFIG_USB_PD_INTERNAL_COMP -#define CONFIG_USB_PD_PORT_COUNT 2 +#define CONFIG_USB_PD_PORT_COUNT 1 #define CONFIG_USB_PD_TCPC #define CONFIG_USB_PD_TCPM_VBUS #define CONFIG_USBC_VCONN @@ -104,10 +104,8 @@ /* ADC signal */ enum adc_channel { - ADC_C1_CC1_PD = 0, - ADC_C0_CC1_PD, + ADC_C0_CC1_PD = 0, ADC_C0_CC2_PD, - ADC_C1_CC2_PD, /* Number of ADC channels */ ADC_CH_COUNT }; diff --git a/board/lars_pd/ec.tasklist b/board/lars_pd/ec.tasklist index 6401c10057..9bc9c5b64c 100644 --- a/board/lars_pd/ec.tasklist +++ b/board/lars_pd/ec.tasklist @@ -20,5 +20,4 @@ TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ /* TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) */ \ - TASK_ALWAYS(PD_C0, pd_task, NULL, TASK_STACK_SIZE) \ - TASK_ALWAYS(PD_C1, pd_task, NULL, TASK_STACK_SIZE) + TASK_ALWAYS(PD_C0, pd_task, NULL, TASK_STACK_SIZE) diff --git a/board/lars_pd/gpio.inc b/board/lars_pd/gpio.inc index 689b37d052..e4ec89a0ba 100644 --- a/board/lars_pd/gpio.inc +++ b/board/lars_pd/gpio.inc @@ -7,33 +7,23 @@ /* Interrupts */ GPIO_INT(USB_C0_VBUS_WAKE_L, PIN(C, 14), GPIO_INT_BOTH, pd_vbus_evt_p0) -GPIO_INT(USB_C1_VBUS_WAKE_L, PIN(C, 15), GPIO_INT_BOTH, pd_vbus_evt_p1) /* PD RX/TX */ GPIO(USB_C0_CC1_PD, PIN(A, 2), GPIO_ANALOG) GPIO(USB_C_REF, PIN(A, 1), GPIO_ANALOG) -GPIO(USB_C1_CC1_PD, PIN(A, 0), GPIO_ANALOG) GPIO(USB_C0_CC2_PD, PIN(A, 4), GPIO_ANALOG) -GPIO(USB_C1_CC2_PD, PIN(A, 5), GPIO_ANALOG) -GPIO(USB_C1_CCX_TX_DATA, PIN(B, 14), GPIO_INPUT) GPIO(USB_C0_CC1_TX_DATA, PIN(B, 4), GPIO_INPUT) -GPIO(USB_C1_CC2_TX_SEL, PIN(B, 0), GPIO_OUT_LOW) /* C1_CC2_TX_SEL */ GPIO(USB_C0_CC2_TX_DATA, PIN(A, 6), GPIO_INPUT) GPIO(USB_PD_VBUS_WAKE, PIN(C, 13), GPIO_INPUT) GPIO(PP3300_USB_PD_EN, PIN(A, 15), GPIO_OUT_HIGH) GPIO(USB_C0_CC1_VCONN1_EN, PIN(B, 1), GPIO_OUT_LOW) GPIO(USB_C0_CC2_VCONN1_EN, PIN(B, 2), GPIO_OUT_LOW) -GPIO(USB_C1_CC1_VCONN1_EN, PIN(B, 9), GPIO_OUT_LOW) -GPIO(USB_C1_CC2_VCONN1_EN, PIN(F, 0), GPIO_OUT_LOW) GPIO(USB_C0_HOST_HIGH, PIN(A, 3), GPIO_OUT_LOW) -GPIO(USB_C1_HOST_HIGH, PIN(A, 7), GPIO_OUT_LOW) GPIO(USB_C0_CC1_ODL, PIN(A, 11), GPIO_ODR_LOW) GPIO(USB_C0_CC2_ODL, PIN(A, 12), GPIO_ODR_LOW) -GPIO(USB_C1_CC1_ODL, PIN(B, 12), GPIO_ODR_LOW) -GPIO(USB_C1_CC2_ODL, PIN(A, 8), GPIO_ODR_LOW) /* * I2C pins should be configured as inputs until I2C module is @@ -42,26 +32,18 @@ GPIO(USB_C1_CC2_ODL, PIN(A, 8), GPIO_ODR_LOW) GPIO(SLAVE_I2C_SCL, PIN(B, 6), GPIO_INPUT) GPIO(SLAVE_I2C_SDA, PIN(B, 7), GPIO_INPUT) -#ifdef BOARD_OAK_PD -GPIO(EC_INT, PIN(B, 5), GPIO_OUT_HIGH) -#else GPIO(EC_INT, PIN(A, 14), GPIO_OUT_HIGH) -#endif UNIMPLEMENTED(WP_L) UNIMPLEMENTED(ENTERING_RW) #if 0 /* Alternate functions */ -GPIO(USB_C1_TX_CLKOUT, PIN(B, 15), GPIO_OUT_LOW) GPIO(USB_C0_TX_CLKOUT, PIN(B, 8), GPIO_OUT_LOW) -GPIO(USB_C1_TX_CLKIN, PIN(B, 13), GPIO_OUT_LOW) GPIO(USB_C0_TX_CLKIN, PIN(B, 3), GPIO_OUT_LOW) #endif ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */ -ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */ ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8 */ -ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15 */ ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA9/PA10 */ ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */ diff --git a/board/lars_pd/usb_pd_config.h b/board/lars_pd/usb_pd_config.h index 8df3f84dc1..0e0cc856ef 100644 --- a/board/lars_pd/usb_pd_config.h +++ b/board/lars_pd/usb_pd_config.h @@ -16,46 +16,36 @@ /* Timer selection for baseband PD communication */ #define TIM_CLOCK_PD_TX_C0 16 #define TIM_CLOCK_PD_RX_C0 1 -#define TIM_CLOCK_PD_TX_C1 15 -#define TIM_CLOCK_PD_RX_C1 3 /* Timer channel */ #define TIM_TX_CCR_C0 1 #define TIM_RX_CCR_C0 1 -#define TIM_TX_CCR_C1 2 -#define TIM_RX_CCR_C1 1 -#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_C1 : TIM_CLOCK_PD_TX_C0) -#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_C1 : TIM_CLOCK_PD_RX_C0) +#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0 +#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0 /* RX timer capture/compare register */ #define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0)) -#define TIM_CCR_C1 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C1, TIM_RX_CCR_C1)) -#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_C1 : TIM_CCR_C0) +#define TIM_RX_CCR_REG(p) (TIM_CCR_C0) /* TX and RX timer register */ #define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0)) #define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0)) -#define TIM_REG_TX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C1)) -#define TIM_REG_RX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C1)) -#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_C1 : TIM_REG_TX_C0) -#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_C1 : TIM_REG_RX_C0) +#define TIM_REG_TX(p) (TIM_REG_TX_C0) +#define TIM_REG_RX(p) (TIM_REG_RX_C0) /* use the hardware accelerator for CRC */ #define CONFIG_HW_CRC /* TX uses SPI1 on PB3-4 for port C0, SPI2 on PB 13-14 for port C1 */ -#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS) +#define SPI_REGS(p) (STM32_SPI1_REGS) static inline void spi_enable_clock(int port) { - if (port == 0) - STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; - else - STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; } -/* DMA for transmit uses DMA CH3 for C0 and DMA_CH5 for C1 */ -#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH5 : STM32_DMAC_CH3) +/* DMA for transmit uses DMA CH3 for C0 */ +#define DMAC_SPI_TX(p) (STM32_DMAC_CH3) /* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/ /* C1 RX use CMP1, TIM3_CH1, DMA_CH4 */ @@ -63,8 +53,8 @@ static inline void spi_enable_clock(int port) /* C0 RX use CMP2, TIM1_CH1, DMA_CH2 */ #define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1 -#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0) -#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0) +#define TIM_TX_CCR_IDX(p) (TIM_TX_CCR_C0) +#define TIM_RX_CCR_IDX(p) (TIM_RX_CCR_C0) #define TIM_CCR_CS 1 /* @@ -72,14 +62,14 @@ static inline void spi_enable_clock(int port) * EXTI line 22 is connected to the CMP2 output, * C0 uses CMP2, and C1 uses CMP1. */ -#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22)) +#define EXTI_COMP_MASK(p) (1 << 22) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ #define EXTI_XTSR STM32_EXTI_FTSR /* DMA for receive uses DMA_CH2 for C0 and DMA_CH4 for C1 */ -#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH4 : STM32_DMAC_CH2) +#define DMAC_TIM_RX(p) ( STM32_DMAC_CH2) /* the pins used for communication need to be hi-speed */ static inline void pd_set_pins_speed(int port) @@ -93,13 +83,6 @@ static inline void pd_set_pins_speed(int port) * (USB_C0_TX_CLKOUT) */ STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000; - } else { - /* 40 MHz pin speed on SPI PB13/14, - * (USB_C1_TX_CLKIN & USB_C1_CCX_TX_DATA) - */ - STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000; - /* 40 MHz pin speed on TIM15_CH2 (PB15) */ - STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000; } } @@ -110,10 +93,6 @@ static inline void pd_tx_spi_reset(int port) /* Reset SPI1 */ STM32_RCC_APB2RSTR |= (1 << 12); STM32_RCC_APB2RSTR &= ~(1 << 12); - } else { - /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= (1 << 14); - STM32_RCC_APB1RSTR &= ~(1 << 14); } } @@ -139,30 +118,6 @@ static inline void pd_tx_enable(int port, int polarity) | (1 << (2*2)); /* Set as GPO */ gpio_set_level(GPIO_USB_C0_CC1_PD, 0); } - } else { - /* put SPI function on TX pin */ - /* USB_C1_CCX_TX_DATA: PB14 is SPI1 MISO */ - gpio_set_alternate_function(GPIO_B, 0x4000, 0); - /* MCU ADC pin output low */ - if (polarity) { - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*5))) /* PA5 disable ADC */ - | (1 << (2*5)); /* Set as GPO */ - gpio_set_level(GPIO_USB_C1_CC2_PD, 0); - } else { - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*0))) /* PA0 disable ADC */ - | (1 << (2*0)); /* Set as GPO */ - gpio_set_level(GPIO_USB_C1_CC1_PD, 0); - } - - /* - * There is a pin muxer to select CC1 or CC2 TX_DATA, - * Pin mux is controlled by USB_C1_CC2_TX_SEL pin, - * USB_C1_CC1_TX_DATA will be selected, if polarity is 0, - * USB_C1_CC2_TX_DATA will be selected, if polarity is 1 . - */ - gpio_set_level(GPIO_USB_C1_CC2_TX_SEL, polarity); } } @@ -185,19 +140,6 @@ static inline void pd_tx_disable(int port, int polarity) STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) | (3 << (2*2))); /* PA2 as ADC */ } - } else { - /* Set TX_DATA (PB14) Hi-Z */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - & ~(3 << (2*14))); - if (polarity) { - /* set ADC PA5 pin to ADC function (Hi-Z) */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*5))); /* PA5 as ADC */ - } else { - /* set ADC PA0 pin to ADC function (Hi-Z) */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*0))); /* PA0 as ADC */ - } } } @@ -214,11 +156,6 @@ static inline void pd_select_polarity(int port, int polarity) STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) | (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */ : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */ - } else { - /* C1 use the right comparator inverted input for COMP1 */ - STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) | - (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */ - : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */ } } @@ -247,23 +184,6 @@ static inline void pd_set_host_mode(int port, int enable) gpio_set_level(GPIO_USB_C0_CC1_ODL, 0); gpio_set_level(GPIO_USB_C0_CC2_ODL, 0); } - } else { - if (enable) { - /* Pull up for host mode */ - gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_OUTPUT); - gpio_set_level(GPIO_USB_C1_HOST_HIGH, 1); - /* High-Z is used for host mode. */ - gpio_set_level(GPIO_USB_C1_CC1_ODL, 1); - gpio_set_level(GPIO_USB_C1_CC2_ODL, 1); - /* Set TX Hi-Z */ - gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT); - } else { - /* Set HOST_HIGH to High-Z for device mode. */ - gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_INPUT); - /* Pull low for device mode. */ - gpio_set_level(GPIO_USB_C1_CC1_ODL, 0); - gpio_set_level(GPIO_USB_C1_CC2_ODL, 0); - } } } @@ -292,18 +212,12 @@ static inline void pd_config_init(int port, uint8_t power_role) if (port == 0) { gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN, 0); gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN, 0); - } else { - gpio_set_level(GPIO_USB_C1_CC1_VCONN1_EN, 0); - gpio_set_level(GPIO_USB_C1_CC2_VCONN1_EN, 0); } } static inline int pd_adc_read(int port, int cc) { - if (port == 0) - return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD); - else - return adc_read_channel(cc ? ADC_C1_CC2_PD : ADC_C1_CC1_PD); + return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD); } static inline void pd_set_vconn(int port, int polarity, int enable) @@ -315,11 +229,6 @@ static inline void pd_set_vconn(int port, int polarity, int enable) /* Set TX_DATA pin to Hi-Z */ gpio_set_flags(polarity ? GPIO_USB_C0_CC1_TX_DATA : GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT); - } else { - gpio_set_level(polarity ? GPIO_USB_C1_CC1_VCONN1_EN : - GPIO_USB_C1_CC2_VCONN1_EN, enable); - /* Set TX_DATA pin to Hi-Z */ - gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT); } } |