cr50: integrate register definitions consistent with real silicon

The new register definitions file has been supplied, it is not
defining some fields which were present only in FPGA. Some tweaks are
required to accommodate this.

BRANCH=none
BUG=chrome-os-partner:50141
TEST=new code successfully boots on the evaluation board

Change-Id: Ie4158554e0aaf039d59669558861a763a23f0ceb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326803
Reviewed-by: Bill Richardson <wfrichar@chromium.org>

4 files changed, 99 insertions, 126 deletions

diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h
index c492bb2da6..85a15dc93d 100644
--- a/chip/g/config_chip.h
+++ b/chip/g/config_chip.h
@@ -59,7 +59,7 @@
 #define GPIO_PIN(port, index) GPIO_##port, (1 << index)
 #define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask)
 
-#define PCLK_FREQ  (GC_CONST_FPGA_TIMER_FIXED_FREQ * 1000 * 1000)
+#define PCLK_FREQ  (24 * 1000 * 1000)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT (GC_INTERRUPTS_COUNT - 16)
diff --git a/chip/g/hw_regdefs.h b/chip/g/hw_regdefs.h
index e58b214a68..dabf9dfc40 100644
--- a/chip/g/hw_regdefs.h
+++ b/chip/g/hw_regdefs.h
@@ -4,7 +4,7 @@
  * found in the LICENSE file.
  */
 
-/* This file is autogenerated by the cr50_regs utility. Do not edit. */
+/* This file is autogenerated by the g_regs utility. Do not edit. */
 
 #ifndef __EC_CHIP_G_CR50_FPGA_REGDEFS_H
 #define __EC_CHIP_G_CR50_FPGA_REGDEFS_H
@@ -649,9 +649,9 @@
 #define GC_CAMO_CLEAR_COUNTER_OFFSET             0x4
 #define GC_CAMO_CLEAR_COUNTER_DEFAULT            0x0
 #define GC_CAMO_VERSION_OFFSET                   0x8
-#define GC_CAMO_VERSION_DEFAULT                  0x3011319
+#define GC_CAMO_VERSION_DEFAULT                  0x1014125
 #define GC_CRYPTO_VERSION_OFFSET                 0x0
-#define GC_CRYPTO_VERSION_DEFAULT                0x2b012fb1
+#define GC_CRYPTO_VERSION_DEFAULT                0x101424a
 #define GC_CRYPTO_CONTROL_OFFSET                 0x4
 #define GC_CRYPTO_CONTROL_DEFAULT                0x0
 #define GC_CRYPTO_PARITY_CFG_OFFSET              0x8
@@ -695,7 +695,7 @@
 #define GC_CRYPTO_DMEM_DUMMY_OFFSET              0x4000
 #define GC_CRYPTO_IMEM_DUMMY_OFFSET              0x8000
 #define GC_DMA_VERSION_OFFSET                    0x0
-#define GC_DMA_VERSION_DEFAULT                   0x14012f32
+#define GC_DMA_VERSION_DEFAULT                   0x101424a
 #define GC_DMA_INT_ENABLE_OFFSET                 0x4
 #define GC_DMA_INT_ENABLE_DEFAULT                0x0
 #define GC_DMA_INT_STATE_OFFSET                  0x8
@@ -881,15 +881,15 @@
 #define GC_FLASH_FSH_PE_CONTROL0_OFFSET          0x0
 #define GC_FLASH_FSH_PE_CONTROL0_DEFAULT         0x0
 #define GC_FLASH_FSH_PE_CONTROL0_PROG            0x27182818
-#define GC_FLASH_FSH_PE_CONTROL0_ERASE           0x31415927
-#define GC_FLASH_FSH_PE_CONTROL0_BULKERASE       0x1d1e2bad
 #define GC_FLASH_FSH_PE_CONTROL0_READ            0x16021765
+#define GC_FLASH_FSH_PE_CONTROL0_BULKERASE       0x1d1e2bad
+#define GC_FLASH_FSH_PE_CONTROL0_ERASE           0x31415927
 #define GC_FLASH_FSH_PE_CONTROL1_OFFSET          0x4
 #define GC_FLASH_FSH_PE_CONTROL1_DEFAULT         0x0
 #define GC_FLASH_FSH_PE_CONTROL1_PROG            0x27182818
-#define GC_FLASH_FSH_PE_CONTROL1_ERASE           0x31415927
-#define GC_FLASH_FSH_PE_CONTROL1_BULKERASE       0x1d1e2bad
 #define GC_FLASH_FSH_PE_CONTROL1_READ            0x16021765
+#define GC_FLASH_FSH_PE_CONTROL1_BULKERASE       0x1d1e2bad
+#define GC_FLASH_FSH_PE_CONTROL1_ERASE           0x31415927
 #define GC_FLASH_FSH_TRANS_OFFSET                0x8
 #define GC_FLASH_FSH_TRANS_DEFAULT               0x0
 #define GC_FLASH_FSH_PROTECT_INFO1_OFFSET        0xc
@@ -1089,16 +1089,16 @@
 #define GC_FUSE_STATUS_DEFAULT                   0x0
 #define GC_FUSE_READ_START_OFFSET                0x4
 #define GC_FUSE_READ_START_DEFAULT               0x0
-#define GC_FUSE_READ_START_ENABLE                0xc8eca61e
 #define GC_FUSE_READ_START_DISABLE               0x0
+#define GC_FUSE_READ_START_ENABLE                0xc8eca61e
 #define GC_FUSE_PROG_START_OFFSET                0x8
 #define GC_FUSE_PROG_START_DEFAULT               0x0
-#define GC_FUSE_PROG_START_ENABLE                0xdc98157b
 #define GC_FUSE_PROG_START_DISABLE               0x0
+#define GC_FUSE_PROG_START_ENABLE                0xdc98157b
 #define GC_FUSE_OVERRIDE_START_OFFSET            0xc
 #define GC_FUSE_OVERRIDE_START_DEFAULT           0x0
-#define GC_FUSE_OVERRIDE_START_ENABLE            0x894e4cf3
 #define GC_FUSE_OVERRIDE_START_DISABLE           0x0
+#define GC_FUSE_OVERRIDE_START_ENABLE            0x894e4cf3
 #define GC_FUSE_FPGA_MODEL_CTRL_OFFSET           0x10
 #define GC_FUSE_FPGA_MODEL_CTRL_DEFAULT          0x0
 #define GC_FUSE_SCRUB_PRBS_CLK_DIV_OFFSET        0x14
@@ -1107,18 +1107,18 @@
 #define GC_FUSE_SCRUB_PRBS_THRESHOLD_VAL_DEFAULT 0x7fff
 #define GC_FUSE_SCRUB_ENABLE_OFFSET              0x1c
 #define GC_FUSE_SCRUB_ENABLE_DEFAULT             0x0
-#define GC_FUSE_SCRUB_ENABLE_ENABLE              0x5
 #define GC_FUSE_SCRUB_ENABLE_DISABLE             0x0
+#define GC_FUSE_SCRUB_ENABLE_ENABLE              0x5
 #define GC_FUSE_ERROR_INJECT_OFFSET              0x20
 #define GC_FUSE_ERROR_INJECT_DEFAULT             0x0
-#define GC_FUSE_ERROR_INJECT_ENABLE              0x690c7334
 #define GC_FUSE_ERROR_INJECT_DISABLE             0x0
+#define GC_FUSE_ERROR_INJECT_ENABLE              0x690c7334
 #define GC_FUSE_VDDQ_RAMP_TIMING_OFFSET          0x24
 #define GC_FUSE_VDDQ_RAMP_TIMING_DEFAULT         0x1d4c0
 #define GC_FUSE_ANTEST_EN_OFFSET                 0x28
 #define GC_FUSE_ANTEST_EN_DEFAULT                0x0
 #define GC_FUSE_VERSION_OFFSET                   0x2c
-#define GC_FUSE_VERSION_DEFAULT                  0x12012324
+#define GC_FUSE_VERSION_DEFAULT                  0x1014125
 #define GC_FUSE_BNK0_INTG_CHKSUM_OFFSET          0x30
 #define GC_FUSE_BNK0_INTG_CHKSUM_DEFAULT         0x55000000
 #define GC_FUSE_BNK0_INTG_LOCK_OFFSET            0x34
@@ -3290,7 +3290,7 @@
 #define GC_I2C_ITOP_OFFSET                       0xf04
 #define GC_I2C_ITOP_DEFAULT                      0x0
 #define GC_I2CS_VERSION_OFFSET                   0x0
-#define GC_I2CS_VERSION_DEFAULT                  0x600f6a0
+#define GC_I2CS_VERSION_DEFAULT                  0x101424a
 #define GC_I2CS_INT_ENABLE_OFFSET                0x4
 #define GC_I2CS_INT_ENABLE_DEFAULT               0x0
 #define GC_I2CS_INT_STATE_OFFSET                 0x8
@@ -4053,37 +4053,37 @@
 #define GC_PMU_RST1_OFFSET                       0x9c
 #define GC_PMU_RST1_DEFAULT                      0x0
 #define GC_PMU_PWRDN_SCRATCH0_OFFSET             0xa0
-#define GC_PMU_PWRDN_SCRATCH0_DEFAULT            0x8109eac4
+#define GC_PMU_PWRDN_SCRATCH0_DEFAULT            0x7020eceb
 #define GC_PMU_PWRDN_SCRATCH1_OFFSET             0xa4
-#define GC_PMU_PWRDN_SCRATCH1_DEFAULT            0x6def50a4
+#define GC_PMU_PWRDN_SCRATCH1_DEFAULT            0x2ebe9116
 #define GC_PMU_PWRDN_SCRATCH2_OFFSET             0xa8
-#define GC_PMU_PWRDN_SCRATCH2_DEFAULT            0x9c8b751d
+#define GC_PMU_PWRDN_SCRATCH2_DEFAULT            0x13b4a4d9
 #define GC_PMU_PWRDN_SCRATCH3_OFFSET             0xac
-#define GC_PMU_PWRDN_SCRATCH3_DEFAULT            0x4407f7d
+#define GC_PMU_PWRDN_SCRATCH3_DEFAULT            0x3d2dd072
 #define GC_PMU_PWRDN_SCRATCH4_OFFSET             0xb0
-#define GC_PMU_PWRDN_SCRATCH4_DEFAULT            0x35e79243
+#define GC_PMU_PWRDN_SCRATCH4_DEFAULT            0x13eda68b
 #define GC_PMU_PWRDN_SCRATCH5_OFFSET             0xb4
-#define GC_PMU_PWRDN_SCRATCH5_DEFAULT            0x75f5b26c
+#define GC_PMU_PWRDN_SCRATCH5_DEFAULT            0x295c9f66
 #define GC_PMU_PWRDN_SCRATCH6_OFFSET             0xb8
-#define GC_PMU_PWRDN_SCRATCH6_DEFAULT            0x6c54e11e
+#define GC_PMU_PWRDN_SCRATCH6_DEFAULT            0x2a23c2db
 #define GC_PMU_PWRDN_SCRATCH7_OFFSET             0xbc
-#define GC_PMU_PWRDN_SCRATCH7_DEFAULT            0x8d7cc6e
+#define GC_PMU_PWRDN_SCRATCH7_DEFAULT            0x8ef4ab68
 #define GC_PMU_PWRDN_SCRATCH8_OFFSET             0xc0
-#define GC_PMU_PWRDN_SCRATCH8_DEFAULT            0x4139bd1f
+#define GC_PMU_PWRDN_SCRATCH8_DEFAULT            0x35057fa1
 #define GC_PMU_PWRDN_SCRATCH9_OFFSET             0xc4
-#define GC_PMU_PWRDN_SCRATCH9_DEFAULT            0x55793843
+#define GC_PMU_PWRDN_SCRATCH9_DEFAULT            0x4bfc60a3
 #define GC_PMU_PWRDN_SCRATCH10_OFFSET            0xc8
-#define GC_PMU_PWRDN_SCRATCH10_DEFAULT           0x1340f7d7
+#define GC_PMU_PWRDN_SCRATCH10_DEFAULT           0xa82ff9e
 #define GC_PMU_PWRDN_SCRATCH11_OFFSET            0xcc
-#define GC_PMU_PWRDN_SCRATCH11_DEFAULT           0x4bbcb617
+#define GC_PMU_PWRDN_SCRATCH11_DEFAULT           0x3898bda0
 #define GC_PMU_PWRDN_SCRATCH12_OFFSET            0xd0
-#define GC_PMU_PWRDN_SCRATCH12_DEFAULT           0x1aec1870
+#define GC_PMU_PWRDN_SCRATCH12_DEFAULT           0x3c64367b
 #define GC_PMU_PWRDN_SCRATCH13_OFFSET            0xd4
-#define GC_PMU_PWRDN_SCRATCH13_DEFAULT           0x3ffb5b92
+#define GC_PMU_PWRDN_SCRATCH13_DEFAULT           0x1f653095
 #define GC_PMU_PWRDN_SCRATCH14_OFFSET            0xd8
-#define GC_PMU_PWRDN_SCRATCH14_DEFAULT           0x2b0c6626
+#define GC_PMU_PWRDN_SCRATCH14_DEFAULT           0x21d285ad
 #define GC_PMU_PWRDN_SCRATCH15_OFFSET            0xdc
-#define GC_PMU_PWRDN_SCRATCH15_DEFAULT           0x37a79be
+#define GC_PMU_PWRDN_SCRATCH15_DEFAULT           0x2fe32196
 #define GC_PMU_PWRDN_SCRATCH16_OFFSET            0xe0
 #define GC_PMU_PWRDN_SCRATCH16_DEFAULT           0x0
 #define GC_PMU_PWRDN_SCRATCH17_OFFSET            0xe4
@@ -4231,7 +4231,7 @@
 #define GC_RBOX_WAKEUP_INTR_OFFSET               0x9c
 #define GC_RBOX_WAKEUP_INTR_DEFAULT              0x0
 #define GC_RBOX_VERSION_OFFSET                   0xa0
-#define GC_RBOX_VERSION_DEFAULT                  0x38012a71
+#define GC_RBOX_VERSION_DEFAULT                  0x1014125
 #define GC_RDD_VERSION_OFFSET                    0x0
 #define GC_RDD_VERSION_DEFAULT                   0x24011f09
 #define GC_RDD_INT_ENABLE_OFFSET                 0x4
@@ -4561,21 +4561,15 @@
 #define GC_SWDP_HEADER_MD5SUM_OFFSET             0x28
 #define GC_SWDP_HEADER_MD5SUM_DEFAULT            0x0
 #define GC_SWDP_P4_LAST_SYNC_OFFSET              0x2c
-#define GC_SWDP_P4_LAST_SYNC_DEFAULT             0x13bf1
+#define GC_SWDP_P4_LAST_SYNC_DEFAULT             0x0
 #define GC_SWDP_BUILD_DATE_OFFSET                0x30
-#define GC_SWDP_BUILD_DATE_DEFAULT               0x1337b4e
+#define GC_SWDP_BUILD_DATE_DEFAULT               0x0
 #define GC_SWDP_BUILD_TIME_OFFSET                0x34
-#define GC_SWDP_BUILD_TIME_DEFAULT               0x2bd2
+#define GC_SWDP_BUILD_TIME_DEFAULT               0x0
 #define GC_SWDP_TEST_PORT_DISABLE_OFFSET         0x38
 #define GC_SWDP_TEST_PORT_DISABLE_DEFAULT        0x0
-#define GC_SWDP_FPGA_CONFIG_OFFSET               0x3c
-#define GC_SWDP_FPGA_CONFIG_DEFAULT              0x1
-#define GC_SWDP_FPGA_JITTER_FIXED_FREQ_OFFSET    0x40
-#define GC_SWDP_FPGA_JITTER_FIXED_FREQ_DEFAULT   0xb71b00
-#define GC_SWDP_FPGA_TIMER_FIXED_FREQ_OFFSET     0x44
-#define GC_SWDP_FPGA_TIMER_FIXED_FREQ_DEFAULT    0x16e3600
 #define GC_TEMP_VERSION_OFFSET                   0x0
-#define GC_TEMP_VERSION_DEFAULT                  0x9012df1
+#define GC_TEMP_VERSION_DEFAULT                  0x1014125
 #define GC_TEMP_ADC_INT_ENABLE_OFFSET            0x4
 #define GC_TEMP_ADC_INT_ENABLE_DEFAULT           0x0
 #define GC_TEMP_ADC_INT_STATE_OFFSET             0x8
@@ -4618,18 +4612,6 @@
 #define GC_TEMP_SAMPLE_CTR_STATE_DEFAULT         0x0
 #define GC_TEMP_ANTEST_EN_OFFSET                 0x54
 #define GC_TEMP_ANTEST_EN_DEFAULT                0x0
-#define GC_TEMP_FPGA_MODEL_TEMP_OFFSET           0x58
-#define GC_TEMP_FPGA_MODEL_TEMP_DEFAULT          0x8000
-#define GC_TEMP_FPGA_MODEL_DRIFT_PERIOD_OFFSET   0x5c
-#define GC_TEMP_FPGA_MODEL_DRIFT_PERIOD_DEFAULT  0x100
-#define GC_TEMP_FPGA_MODEL_DRIFT_AMOUNT_OFFSET   0x60
-#define GC_TEMP_FPGA_MODEL_DRIFT_AMOUNT_DEFAULT  0x0
-#define GC_TEMP_FPGA_MODEL_TEMP_MAX_OFFSET       0x64
-#define GC_TEMP_FPGA_MODEL_TEMP_MAX_DEFAULT      0xc000
-#define GC_TEMP_FPGA_MODEL_TEMP_MIN_OFFSET       0x68
-#define GC_TEMP_FPGA_MODEL_TEMP_MIN_DEFAULT      0x4000
-#define GC_TEMP_FPGA_MODEL_STAT_CALLS_OFFSET     0x6c
-#define GC_TEMP_FPGA_MODEL_STAT_CALLS_DEFAULT    0x0
 #define GC_TIMEHS_TIMER1LOAD_OFFSET              0x0
 #define GC_TIMEHS_TIMER1LOAD_DEFAULT             0x0
 #define GC_TIMEHS_TIMER1VALUE_OFFSET             0x4
@@ -4735,7 +4717,7 @@
 #define GC_TIMELS_ITOP_OFFSET                    0xf04
 #define GC_TIMELS_ITOP_DEFAULT                   0x0
 #define GC_TIMEUS_VERSION_OFFSET                 0x0
-#define GC_TIMEUS_VERSION_DEFAULT                0x800ea91
+#define GC_TIMEUS_VERSION_DEFAULT                0x101424a
 #define GC_TIMEUS_INT_ENABLE_OFFSET              0x4
 #define GC_TIMEUS_INT_ENABLE_DEFAULT             0x0
 #define GC_TIMEUS_INT_STATE_OFFSET               0x8
@@ -4799,7 +4781,7 @@
 #define GC_TIMEUS_CUR_MINOR_CNTR3_OFFSET         0x418
 #define GC_TIMEUS_CUR_MINOR_CNTR3_DEFAULT        0x0
 #define GC_TRNG_VERSION_OFFSET                   0x0
-#define GC_TRNG_VERSION_DEFAULT                  0x2d013316
+#define GC_TRNG_VERSION_DEFAULT                  0x1014125
 #define GC_TRNG_INT_ENABLE_OFFSET                0x4
 #define GC_TRNG_INT_ENABLE_DEFAULT               0x0
 #define GC_TRNG_INT_STATE_OFFSET                 0x8
@@ -4862,18 +4844,6 @@
 #define GC_TRNG_CUR_NUM_ONES_DEFAULT             0x0
 #define GC_TRNG_EMPTY_OFFSET                     0x7c
 #define GC_TRNG_EMPTY_DEFAULT                    0x1
-#define GC_TRNG_FPGA_MODEL_MEAN_OFFSET           0x80
-#define GC_TRNG_FPGA_MODEL_MEAN_DEFAULT          0x400
-#define GC_TRNG_FPGA_MODEL_DIST_MASK_OFFSET      0x84
-#define GC_TRNG_FPGA_MODEL_DIST_MASK_DEFAULT     0x3ff
-#define GC_TRNG_FPGA_MODEL_PPM_TIMEOUT_OFFSET    0x88
-#define GC_TRNG_FPGA_MODEL_PPM_TIMEOUT_DEFAULT   0x0
-#define GC_TRNG_FPGA_MODEL_STAT_CALLS_OFFSET     0x8c
-#define GC_TRNG_FPGA_MODEL_STAT_CALLS_DEFAULT    0x0
-#define GC_TRNG_FPGA_MODEL_STAT_TIMEOUTS_OFFSET  0x90
-#define GC_TRNG_FPGA_MODEL_STAT_TIMEOUTS_DEFAULT 0x0
-#define GC_TRNG_FPGA_MODEL_STAT_ABORTS_OFFSET    0x94
-#define GC_TRNG_FPGA_MODEL_STAT_ABORTS_DEFAULT   0x0
 #define GC_UART_RDATA_OFFSET                     0x0
 #define GC_UART_RDATA_DEFAULT                    0x0
 #define GC_UART_WDATA_OFFSET                     0x4
@@ -5352,7 +5322,7 @@
 #define GC_USB_PCGCCTL_DEFAULT                   0x0
 #define GC_USB_DFIFO_OFFSET                      0x20000
 #define GC_VOLT_VERSION_OFFSET                   0x0
-#define GC_VOLT_VERSION_DEFAULT                  0x50121be
+#define GC_VOLT_VERSION_DEFAULT                  0x1014125
 #define GC_VOLT_ANALOG_POWER_DOWN_B_OFFSET       0x4
 #define GC_VOLT_ANALOG_POWER_DOWN_B_DEFAULT      0x0
 #define GC_VOLT_ANALOG_CONTROL_OFFSET            0x8
@@ -5406,7 +5376,7 @@
 #define GC_WATCHDOG_WDOGPCELLID3_OFFSET          0xffc
 #define GC_WATCHDOG_WDOGPCELLID3_DEFAULT         0xb1
 #define GC_XO_VERSION_OFFSET                     0x0
-#define GC_XO_VERSION_DEFAULT                    0x1b012f5a
+#define GC_XO_VERSION_DEFAULT                    0x101424a
 #define GC_XO_CFG_WR_EN_OFFSET                   0x4
 #define GC_XO_CFG_WR_EN_DEFAULT                  0x1
 #define GC_XO_JTR_CTRL_EN_OFFSET                 0x8
@@ -6313,22 +6283,22 @@
 #define GC_CAMO_VERSION_CHANGE_LSB               0x0
 #define GC_CAMO_VERSION_CHANGE_MASK              0xffffff
 #define GC_CAMO_VERSION_CHANGE_SIZE              0x18
-#define GC_CAMO_VERSION_CHANGE_DEFAULT           0x11319
+#define GC_CAMO_VERSION_CHANGE_DEFAULT           0x14125
 #define GC_CAMO_VERSION_CHANGE_OFFSET            0x8
 #define GC_CAMO_VERSION_REVISION_LSB             0x18
 #define GC_CAMO_VERSION_REVISION_MASK            0xff000000
 #define GC_CAMO_VERSION_REVISION_SIZE            0x8
-#define GC_CAMO_VERSION_REVISION_DEFAULT         0x3
+#define GC_CAMO_VERSION_REVISION_DEFAULT         0x1
 #define GC_CAMO_VERSION_REVISION_OFFSET          0x8
 #define GC_CRYPTO_VERSION_CHANGE_LSB             0x0
 #define GC_CRYPTO_VERSION_CHANGE_MASK            0xffffff
 #define GC_CRYPTO_VERSION_CHANGE_SIZE            0x18
-#define GC_CRYPTO_VERSION_CHANGE_DEFAULT         0x12fb1
+#define GC_CRYPTO_VERSION_CHANGE_DEFAULT         0x1424a
 #define GC_CRYPTO_VERSION_CHANGE_OFFSET          0x0
 #define GC_CRYPTO_VERSION_REVISION_LSB           0x18
 #define GC_CRYPTO_VERSION_REVISION_MASK          0xff000000
 #define GC_CRYPTO_VERSION_REVISION_SIZE          0x8
-#define GC_CRYPTO_VERSION_REVISION_DEFAULT       0x2b
+#define GC_CRYPTO_VERSION_REVISION_DEFAULT       0x1
 #define GC_CRYPTO_VERSION_REVISION_OFFSET        0x0
 #define GC_CRYPTO_CONTROL_RESET_LSB              0x0
 #define GC_CRYPTO_CONTROL_RESET_MASK             0x1
@@ -6683,12 +6653,12 @@
 #define GC_DMA_VERSION_CHANGE_LSB                0x0
 #define GC_DMA_VERSION_CHANGE_MASK               0xffffff
 #define GC_DMA_VERSION_CHANGE_SIZE               0x18
-#define GC_DMA_VERSION_CHANGE_DEFAULT            0x12f32
+#define GC_DMA_VERSION_CHANGE_DEFAULT            0x1424a
 #define GC_DMA_VERSION_CHANGE_OFFSET             0x0
 #define GC_DMA_VERSION_REVISION_LSB              0x18
 #define GC_DMA_VERSION_REVISION_MASK             0xff000000
 #define GC_DMA_VERSION_REVISION_SIZE             0x8
-#define GC_DMA_VERSION_REVISION_DEFAULT          0x14
+#define GC_DMA_VERSION_REVISION_DEFAULT          0x1
 #define GC_DMA_VERSION_REVISION_OFFSET           0x0
 #define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_LSB 0x0
 #define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_MASK 0xff
@@ -7803,12 +7773,12 @@
 #define GC_FUSE_VERSION_CHANGE_LSB               0x0
 #define GC_FUSE_VERSION_CHANGE_MASK              0xffffff
 #define GC_FUSE_VERSION_CHANGE_SIZE              0x18
-#define GC_FUSE_VERSION_CHANGE_DEFAULT           0x12324
+#define GC_FUSE_VERSION_CHANGE_DEFAULT           0x14125
 #define GC_FUSE_VERSION_CHANGE_OFFSET            0x2c
 #define GC_FUSE_VERSION_REVISION_LSB             0x18
 #define GC_FUSE_VERSION_REVISION_MASK            0xff000000
 #define GC_FUSE_VERSION_REVISION_SIZE            0x8
-#define GC_FUSE_VERSION_REVISION_DEFAULT         0x12
+#define GC_FUSE_VERSION_REVISION_DEFAULT         0x1
 #define GC_FUSE_VERSION_REVISION_OFFSET          0x2c
 #define GC_FUSE_BNK0_INTG_CHKSUM_VAL_LSB         0x0
 #define GC_FUSE_BNK0_INTG_CHKSUM_VAL_MASK        0xffffff
@@ -12373,12 +12343,12 @@
 #define GC_I2CS_VERSION_CHANGE_LSB               0x0
 #define GC_I2CS_VERSION_CHANGE_MASK              0xffffff
 #define GC_I2CS_VERSION_CHANGE_SIZE              0x18
-#define GC_I2CS_VERSION_CHANGE_DEFAULT           0xf6a0
+#define GC_I2CS_VERSION_CHANGE_DEFAULT           0x1424a
 #define GC_I2CS_VERSION_CHANGE_OFFSET            0x0
 #define GC_I2CS_VERSION_REVISION_LSB             0x18
 #define GC_I2CS_VERSION_REVISION_MASK            0xff000000
 #define GC_I2CS_VERSION_REVISION_SIZE            0x8
-#define GC_I2CS_VERSION_REVISION_DEFAULT         0x6
+#define GC_I2CS_VERSION_REVISION_DEFAULT         0x1
 #define GC_I2CS_VERSION_REVISION_OFFSET          0x0
 #define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_LSB   0x0
 #define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_MASK  0x1
@@ -16148,58 +16118,68 @@
 #define GC_PMU_RST1_DUART2_CLK_TIMER_SIZE        0x1
 #define GC_PMU_RST1_DUART2_CLK_TIMER_DEFAULT     0x0
 #define GC_PMU_RST1_DUART2_CLK_TIMER_OFFSET      0x9c
-#define GC_PMU_RST1_DUSB0_AON_LSB                0x8
-#define GC_PMU_RST1_DUSB0_AON_MASK               0x100
+#define GC_PMU_RST1_DUSB0_LSB                    0x8
+#define GC_PMU_RST1_DUSB0_MASK                   0x100
+#define GC_PMU_RST1_DUSB0_SIZE                   0x1
+#define GC_PMU_RST1_DUSB0_DEFAULT                0x0
+#define GC_PMU_RST1_DUSB0_OFFSET                 0x9c
+#define GC_PMU_RST1_DUSB0_AON_LSB                0x9
+#define GC_PMU_RST1_DUSB0_AON_MASK               0x200
 #define GC_PMU_RST1_DUSB0_AON_SIZE               0x1
 #define GC_PMU_RST1_DUSB0_AON_DEFAULT            0x0
 #define GC_PMU_RST1_DUSB0_AON_OFFSET             0x9c
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_LSB   0x9
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_MASK  0x200
+#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_LSB       0xa
+#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_MASK      0x400
+#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_SIZE      0x1
+#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_DEFAULT   0x0
+#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_OFFSET    0x9c
+#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_LSB   0xb
+#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_MASK  0x800
 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_SIZE  0x1
 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_DEFAULT 0x0
 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_OFFSET 0x9c
-#define GC_PMU_RST1_DVOLT0_LSB                   0xa
-#define GC_PMU_RST1_DVOLT0_MASK                  0x400
+#define GC_PMU_RST1_DVOLT0_LSB                   0xc
+#define GC_PMU_RST1_DVOLT0_MASK                  0x1000
 #define GC_PMU_RST1_DVOLT0_SIZE                  0x1
 #define GC_PMU_RST1_DVOLT0_DEFAULT               0x0
 #define GC_PMU_RST1_DVOLT0_OFFSET                0x9c
-#define GC_PMU_RST1_DWATCHDOG0_LSB               0xb
-#define GC_PMU_RST1_DWATCHDOG0_MASK              0x800
+#define GC_PMU_RST1_DWATCHDOG0_LSB               0xd
+#define GC_PMU_RST1_DWATCHDOG0_MASK              0x2000
 #define GC_PMU_RST1_DWATCHDOG0_SIZE              0x1
 #define GC_PMU_RST1_DWATCHDOG0_DEFAULT           0x0
 #define GC_PMU_RST1_DWATCHDOG0_OFFSET            0x9c
-#define GC_PMU_RST1_DXO0_AON_LSB                 0xc
-#define GC_PMU_RST1_DXO0_AON_MASK                0x1000
+#define GC_PMU_RST1_DXO0_AON_LSB                 0xe
+#define GC_PMU_RST1_DXO0_AON_MASK                0x4000
 #define GC_PMU_RST1_DXO0_AON_SIZE                0x1
 #define GC_PMU_RST1_DXO0_AON_DEFAULT             0x0
 #define GC_PMU_RST1_DXO0_AON_OFFSET              0x9c
-#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_LSB       0xd
-#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_MASK      0x2000
+#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_LSB       0xf
+#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_MASK      0x8000
 #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_SIZE      0x1
 #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_DEFAULT   0x0
 #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_OFFSET    0x9c
-#define GC_PMU_RST1_PERI_MASTER_MATRIX_LSB       0xe
-#define GC_PMU_RST1_PERI_MASTER_MATRIX_MASK      0x4000
+#define GC_PMU_RST1_PERI_MASTER_MATRIX_LSB       0x10
+#define GC_PMU_RST1_PERI_MASTER_MATRIX_MASK      0x10000
 #define GC_PMU_RST1_PERI_MASTER_MATRIX_SIZE      0x1
 #define GC_PMU_RST1_PERI_MASTER_MATRIX_DEFAULT   0x0
 #define GC_PMU_RST1_PERI_MASTER_MATRIX_OFFSET    0x9c
-#define GC_PMU_RST1_PERI_MATRIX_LSB              0xf
-#define GC_PMU_RST1_PERI_MATRIX_MASK             0x8000
+#define GC_PMU_RST1_PERI_MATRIX_LSB              0x11
+#define GC_PMU_RST1_PERI_MATRIX_MASK             0x20000
 #define GC_PMU_RST1_PERI_MATRIX_SIZE             0x1
 #define GC_PMU_RST1_PERI_MATRIX_DEFAULT          0x0
 #define GC_PMU_RST1_PERI_MATRIX_OFFSET           0x9c
-#define GC_PMU_RST1_SEC_FABRIC_LSB               0x10
-#define GC_PMU_RST1_SEC_FABRIC_MASK              0x10000
+#define GC_PMU_RST1_SEC_FABRIC_LSB               0x12
+#define GC_PMU_RST1_SEC_FABRIC_MASK              0x40000
 #define GC_PMU_RST1_SEC_FABRIC_SIZE              0x1
 #define GC_PMU_RST1_SEC_FABRIC_DEFAULT           0x0
 #define GC_PMU_RST1_SEC_FABRIC_OFFSET            0x9c
-#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_LSB     0x11
-#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_MASK    0x20000
+#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_LSB     0x13
+#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_MASK    0x80000
 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_SIZE    0x1
 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0
 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_OFFSET  0x9c
-#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_LSB        0x12
-#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_MASK       0x40000
+#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_LSB        0x14
+#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_MASK       0x100000
 #define GC_PMU_RST1_SEC_FABRIC_CLK_HS_SIZE       0x1
 #define GC_PMU_RST1_SEC_FABRIC_CLK_HS_DEFAULT    0x0
 #define GC_PMU_RST1_SEC_FABRIC_CLK_HS_OFFSET     0x9c
@@ -17226,12 +17206,12 @@
 #define GC_RBOX_VERSION_CHANGE_LSB               0x0
 #define GC_RBOX_VERSION_CHANGE_MASK              0xffffff
 #define GC_RBOX_VERSION_CHANGE_SIZE              0x18
-#define GC_RBOX_VERSION_CHANGE_DEFAULT           0x12a71
+#define GC_RBOX_VERSION_CHANGE_DEFAULT           0x14125
 #define GC_RBOX_VERSION_CHANGE_OFFSET            0xa0
 #define GC_RBOX_VERSION_REVISION_LSB             0x18
 #define GC_RBOX_VERSION_REVISION_MASK            0xff000000
 #define GC_RBOX_VERSION_REVISION_SIZE            0x8
-#define GC_RBOX_VERSION_REVISION_DEFAULT         0x38
+#define GC_RBOX_VERSION_REVISION_DEFAULT         0x1
 #define GC_RBOX_VERSION_REVISION_OFFSET          0xa0
 #define GC_RDD_VERSION_CHANGE_LSB                0x0
 #define GC_RDD_VERSION_CHANGE_MASK               0xffffff
@@ -18211,12 +18191,12 @@
 #define GC_TEMP_VERSION_CHANGE_LSB               0x0
 #define GC_TEMP_VERSION_CHANGE_MASK              0xffffff
 #define GC_TEMP_VERSION_CHANGE_SIZE              0x18
-#define GC_TEMP_VERSION_CHANGE_DEFAULT           0x12df1
+#define GC_TEMP_VERSION_CHANGE_DEFAULT           0x14125
 #define GC_TEMP_VERSION_CHANGE_OFFSET            0x0
 #define GC_TEMP_VERSION_REVISION_LSB             0x18
 #define GC_TEMP_VERSION_REVISION_MASK            0xff000000
 #define GC_TEMP_VERSION_REVISION_SIZE            0x8
-#define GC_TEMP_VERSION_REVISION_DEFAULT         0x9
+#define GC_TEMP_VERSION_REVISION_DEFAULT         0x1
 #define GC_TEMP_VERSION_REVISION_OFFSET          0x0
 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_LSB    0x0
 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_MASK   0x1
@@ -18601,12 +18581,12 @@
 #define GC_TIMEUS_VERSION_CHANGE_LSB             0x0
 #define GC_TIMEUS_VERSION_CHANGE_MASK            0xffffff
 #define GC_TIMEUS_VERSION_CHANGE_SIZE            0x18
-#define GC_TIMEUS_VERSION_CHANGE_DEFAULT         0xea91
+#define GC_TIMEUS_VERSION_CHANGE_DEFAULT         0x1424a
 #define GC_TIMEUS_VERSION_CHANGE_OFFSET          0x0
 #define GC_TIMEUS_VERSION_REVISION_LSB           0x18
 #define GC_TIMEUS_VERSION_REVISION_MASK          0xff000000
 #define GC_TIMEUS_VERSION_REVISION_SIZE          0x8
-#define GC_TIMEUS_VERSION_REVISION_DEFAULT       0x8
+#define GC_TIMEUS_VERSION_REVISION_DEFAULT       0x1
 #define GC_TIMEUS_VERSION_REVISION_OFFSET        0x0
 #define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_LSB 0x0
 #define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_MASK 0x1
@@ -18731,12 +18711,12 @@
 #define GC_TRNG_VERSION_CHANGE_LSB               0x0
 #define GC_TRNG_VERSION_CHANGE_MASK              0xffffff
 #define GC_TRNG_VERSION_CHANGE_SIZE              0x18
-#define GC_TRNG_VERSION_CHANGE_DEFAULT           0x13316
+#define GC_TRNG_VERSION_CHANGE_DEFAULT           0x14125
 #define GC_TRNG_VERSION_CHANGE_OFFSET            0x0
 #define GC_TRNG_VERSION_REVISION_LSB             0x18
 #define GC_TRNG_VERSION_REVISION_MASK            0xff000000
 #define GC_TRNG_VERSION_REVISION_SIZE            0x8
-#define GC_TRNG_VERSION_REVISION_DEFAULT         0x2d
+#define GC_TRNG_VERSION_REVISION_DEFAULT         0x1
 #define GC_TRNG_VERSION_REVISION_OFFSET          0x0
 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_LSB  0x0
 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_MASK 0x1
@@ -25961,12 +25941,12 @@
 #define GC_VOLT_VERSION_CHANGE_LSB               0x0
 #define GC_VOLT_VERSION_CHANGE_MASK              0xffffff
 #define GC_VOLT_VERSION_CHANGE_SIZE              0x18
-#define GC_VOLT_VERSION_CHANGE_DEFAULT           0x121be
+#define GC_VOLT_VERSION_CHANGE_DEFAULT           0x14125
 #define GC_VOLT_VERSION_CHANGE_OFFSET            0x0
 #define GC_VOLT_VERSION_REVISION_LSB             0x18
 #define GC_VOLT_VERSION_REVISION_MASK            0xff000000
 #define GC_VOLT_VERSION_REVISION_SIZE            0x8
-#define GC_VOLT_VERSION_REVISION_DEFAULT         0x5
+#define GC_VOLT_VERSION_REVISION_DEFAULT         0x1
 #define GC_VOLT_VERSION_REVISION_OFFSET          0x0
 #define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_LSB     0x0
 #define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_MASK    0x1
@@ -26021,12 +26001,12 @@
 #define GC_XO_VERSION_CHANGE_LSB                 0x0
 #define GC_XO_VERSION_CHANGE_MASK                0xffffff
 #define GC_XO_VERSION_CHANGE_SIZE                0x18
-#define GC_XO_VERSION_CHANGE_DEFAULT             0x12f5a
+#define GC_XO_VERSION_CHANGE_DEFAULT             0x1424a
 #define GC_XO_VERSION_CHANGE_OFFSET              0x0
 #define GC_XO_VERSION_REVISION_LSB               0x18
 #define GC_XO_VERSION_REVISION_MASK              0xff000000
 #define GC_XO_VERSION_REVISION_SIZE              0x8
-#define GC_XO_VERSION_REVISION_DEFAULT           0x1b
+#define GC_XO_VERSION_REVISION_DEFAULT           0x1
 #define GC_XO_VERSION_REVISION_OFFSET            0x0
 #define GC_XO_CLK_JTR_CTRL_HS_SEL_LSB            0x0
 #define GC_XO_CLK_JTR_CTRL_HS_SEL_MASK           0x1
@@ -27644,16 +27624,10 @@
   -1
 #endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */
 
-#define GC_CONST_SWDP_FPGA_CONFIG_USB_CRYPTO     0x3
-#define GC_CONST_FPGA_JITTER_FIXED_FREQ          0xc
-#define GC_CONST_SWDP_FPGA_CONFIG_USB_8X8CRYPTO  0x2
-#define GC_CONST_SWDP_FPGA_CONFIG                0x1
 #define GC_CONST_FSH_PE_CONTROL_BULKERASE        0x1d1e2bad
-#define GC_CONST_FSH_PE_EN                       0xb11924e1
-#define GC_CONST_FSH_PE_CONTROL_PROGRAM          0x27182818
-#define GC_CONST_SWDP_FPGA_CONFIG_NOUSB_CRYPTO   0x1
 #define GC_CONST_FSH_PE_CONTROL_ERASE            0x31415927
+#define GC_CONST_FSH_PE_CONTROL_PROGRAM          0x27182818
+#define GC_CONST_FSH_PE_EN                       0xb11924e1
 #define GC_CONST_FSH_PE_CONTROL_READ             0x16021765
-#define GC_CONST_FPGA_TIMER_FIXED_FREQ           0x18
 #define GC_CONST_FSH_OVRD_UNLOCK                 0x13806488
 #endif /* __EC_CHIP_G_CR50_FPGA_REGDEFS_H */
diff --git a/chip/g/hwtimer.c b/chip/g/hwtimer.c
index 7f5b87ee94..d7eb3d11d5 100644
--- a/chip/g/hwtimer.c
+++ b/chip/g/hwtimer.c
@@ -56,7 +56,7 @@ static void update_prescaler(void)
 	/*
 	 * Assume the clock rate is an integer multiple of MHz.
 	 */
-	clock_mul_factor = GC_CONST_FPGA_TIMER_FIXED_FREQ;
+	clock_mul_factor = PCLK_FREQ / 1000000;
 	clock_div_factor = 0xffffffff / clock_mul_factor;
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
diff --git a/chip/g/watchdog.c b/chip/g/watchdog.c
index 84ef15cd76..0d07ddec4b 100644
--- a/chip/g/watchdog.c
+++ b/chip/g/watchdog.c
@@ -17,8 +17,7 @@
 #define WATCHDOG_MAGIC_WORD  0x1ACCE551
 
 /* Watchdog expiration */
-#define WATCHDOG_PERIOD (CONFIG_WATCHDOG_PERIOD_MS * \
-			 ((GC_CONST_FPGA_JITTER_FIXED_FREQ * 1000000) / 1000))
+#define WATCHDOG_PERIOD (CONFIG_WATCHDOG_PERIOD_MS * (PCLK_FREQ / 1000))
 
 void trace_and_reset(uint32_t excep_lr, uint32_t excep_sp)
 {