diff options
| author | Archana Patni <archana.patni@intel.com> | 2016-02-17 16:18:15 +0530 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-02-22 09:00:52 -0800 |
| commit | 74615c1011382d930f3c4be72ec043ad35856b95 (patch) | |
| tree | d62cdc72504ae8d2b292f6f8b71c1f79a0556387 | |
| parent | 2435c91b3a52071a048cc7261b966daf2e78f853 (diff) | |
| download | chrome-ec-74615c1011382d930f3c4be72ec043ad35856b95.tar.gz | |
skylake: do not clear masks in S0ix -> S0 transition
EC clears the SCI/SMI/Wake masks in the resume sequence for S3
and S0ix. This works in the S3 case because Coreboot reprograms
the masks after EC. But in S0ix, these masks stay cleared forever.
This means that no further events are sent to the host.
This patch conditionally clears the masks only in the S3 transition.
BRANCH=glados
BUG=chrome-os-partner:48834
TEST=hostevent in EC console before and after S0ix to ensure SCI masks
are preserved
Change-Id: I23751680788ee7a239e321309a1334d37adc4f43
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/320191
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | chip/mec1322/lpc.c | 14 | ||||
| -rw-r--r-- | chip/npcx/lpc.c | 13 |
2 files changed, 18 insertions, 9 deletions
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index a53a02efad..e58d7138ff 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -294,11 +294,15 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST); static void lpc_resume(void) { - /* Mask all host events until the host unmasks them itself. */ - lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0); - lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0); - lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, 0); - +#ifdef CONFIG_POWER_S0IX + if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON)) +#endif + { + /* Mask all host events until the host unmasks them itself. */ + lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0); + lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0); + lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, 0); + } /* Store port 80 event so we know where resume happened */ port_80_write(PORT_80_EVENT_RESUME); } diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index c86872e927..27cefcfce8 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -901,10 +901,15 @@ DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC); static void lpc_resume(void) { - /* Mask all host events until the host unmasks them itself. */ - lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0); - lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0); - lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, 0); +#ifdef CONFIG_POWER_S0IX + if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON)) +#endif + { + /* Mask all host events until the host unmasks them itself. */ + lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0); + lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0); + lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, 0); + } /* Store port 80 event so we know where resume happened */ port_80_write(PORT_80_EVENT_RESUME); |