diff options
| author | Divagar Mohandass <divagar.mohandass@intel.com> | 2016-01-29 14:05:22 +0530 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-02-14 19:39:03 -0800 |
| commit | 958554a97dc1e98e2538aeceab22ee3609336056 (patch) | |
| tree | ce9ff2da053fc28f3481253f06b7bf30195a8e90 | |
| parent | 80d49a433dd95b243e118c8690ad4e6b1db2b71e (diff) | |
| download | chrome-ec-958554a97dc1e98e2538aeceab22ee3609336056.tar.gz | |
Lars: Enable S0ix.
This change will enable S0ix related state transition logic
for Lars platform.
BUG=None
BRANCH=glados
TEST=In OS shell, run 'echo freeze > /sys/power/state'
command to tigger S0ix.
Change-Id: I15d273f8d9b24c24155437dae5ff673909eee50c
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/324740
Tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
(cherry picked from commit b96aa25174e50f61ae4bede5bc6b078bffef2a7e)
Reviewed-on: https://chromium-review.googlesource.com/326621
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
| -rw-r--r-- | board/lars/board.h | 4 | ||||
| -rw-r--r-- | board/lars/gpio.inc | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/board/lars/board.h b/board/lars/board.h index 0d379da3c5..c12ffe0b8f 100644 --- a/board/lars/board.h +++ b/board/lars/board.h @@ -68,6 +68,8 @@ #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_COMMON #define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 +/* Enable S0IX */ +#define CONFIG_POWER_S0IX #define CONFIG_PWM #define CONFIG_PWM_KBLIGHT /* All data won't fit in data RAM. So, moving boundary slightly. */ @@ -130,7 +132,7 @@ #define I2C_PORT_THERMAL MEC1322_I2C3 #undef DEFERRABLE_MAX_COUNT -#define DEFERRABLE_MAX_COUNT 13 +#define DEFERRABLE_MAX_COUNT 14 /* Modules we want to exclude */ #undef CONFIG_CMD_ACCEL_INFO diff --git a/board/lars/gpio.inc b/board/lars/gpio.inc index 837b941632..0968a49817 100644 --- a/board/lars/gpio.inc +++ b/board/lars/gpio.inc @@ -21,7 +21,7 @@ GPIO_INT(AC_PRESENT, PIN(30), GPIO_INT_BOTH, extpower_interrupt) GPIO_INT(WP_L, PIN(33), GPIO_INT_BOTH, switch_interrupt) /* Buffered power button input from PMIC / ROP_EC_PWR_BTN_L_R */ GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt) -GPIO_INT(PCH_SLP_S0_L, PIN(141), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) +GPIO_INT(PCH_SLP_S0_L, PIN(141), GPIO_INT_BOTH, power_signal_interrupt_S0) GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) /* RSMRST from PMIC */ GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) |