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| author | Mulin Chao <mlchao@nuvoton.com> | 2016-03-03 11:24:55 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-03-05 11:36:32 -0800 |
| commit | dca765004fddc75fad07d48469caff61d1574d1b (patch) | |
| tree | 11976b50041fd6f8dd9796c4b0edea37d0eb82df | |
| parent | f02a5e90453515e6215e27f565dfd78603a05567 (diff) | |
| download | chrome-ec-dca765004fddc75fad07d48469caff61d1574d1b.tar.gz | |
npcx: Add CHIP_VARIANT variant for different versions of npcx ec.
In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT
variant to distinguish which verson ec is.
In config_chip.h, we use CHIP_VARIANT to specify the size and start address
of program memory. Ecst tool also needs a chip parameter to make sure
the address range checking of entry pointer won't fail.
Modified sources:
1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec
of npcx ec.
2. config_flash_layout.h: Replace constant value with
CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE.
3. build.mk: Add -chip parameter for ecst tool to check entry address.
4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/330072
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | board/npcx_evb/build.mk | 3 | ||||
| -rw-r--r-- | board/npcx_evb_arm/build.mk | 3 | ||||
| -rw-r--r-- | board/wheatley/build.mk | 3 | ||||
| -rw-r--r-- | chip/npcx/build.mk | 2 | ||||
| -rw-r--r-- | chip/npcx/config_chip.h | 16 | ||||
| -rw-r--r-- | chip/npcx/config_flash_layout.h | 4 |
6 files changed, 24 insertions, 7 deletions
diff --git a/board/npcx_evb/build.mk b/board/npcx_evb/build.mk index 8689f927bc..a5be8dc055 100644 --- a/board/npcx_evb/build.mk +++ b/board/npcx_evb/build.mk @@ -6,7 +6,8 @@ # Board specific files build # -# the IC is Nuvoton M-Series EC +# the IC is Nuvoton M-Series EC (npcx5m5g, npcx5m6g) CHIP:=npcx +CHIP_VARIANT:=npcx5m5g board-y=board.o diff --git a/board/npcx_evb_arm/build.mk b/board/npcx_evb_arm/build.mk index ebebf140d8..9d848171c2 100644 --- a/board/npcx_evb_arm/build.mk +++ b/board/npcx_evb_arm/build.mk @@ -6,7 +6,8 @@ # Board specific files build # -# the IC is Nuvoton M-Series EC +# the IC is Nuvoton M-Series EC (npcx5m5g, npcx5m6g) CHIP:=npcx +CHIP_VARIANT:=npcx5m5g board-y=board.o diff --git a/board/wheatley/build.mk b/board/wheatley/build.mk index 1b835dd2da..ca3458e3b0 100644 --- a/board/wheatley/build.mk +++ b/board/wheatley/build.mk @@ -6,8 +6,9 @@ # Board specific files build # -# the IC is Nuvoton M-Series EC +# the IC is Nuvoton M-Series EC (npcx5m5g, npcx5m6g) CHIP:=npcx +CHIP_VARIANT:=npcx5m5g board-y=board.o led.o board-$(CONFIG_BATTERY_SMART)+=battery.o diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index 0fd97d33b0..09f59e3710 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -37,7 +37,7 @@ PROJECT_EXTRA+=${npcx-flash-fw-bin} show_esct_cmd=$(if $(V),,echo ' ECST ' $(subst $(out)/,,$@) ; ) # ECST options for header -bld_ecst=${out}/util/ecst -usearmrst -mode bt -ph -i $(1) -o $(2) -nohcrc \ +bld_ecst=${out}/util/ecst -chip $(CHIP_VARIANT) -usearmrst -mode bt -ph -i $(1) -o $(2) -nohcrc \ -nofcrc -flashsize 8 -spimaxclk 50 -spireadmode dual 1> /dev/null # Replace original one with the flat file including header diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 138fd47043..2910a7347f 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -47,10 +47,24 @@ /* Memory mapping */ #define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ #define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000 /* program memory base address */ #define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ #define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ +/* Use chip variant to specify the size and start address of program memory */ +#if defined(CHIP_VARIANT_NPCX5M5G) +/* 96KB RAM for FW code */ +#define CONFIG_PROGRAM_MEMORY_SIZE (96 * 1024) +/* program memory base address for 128KB RAM */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000 +#elif defined(CHIP_VARIANT_NPCX5M6G) +/* 224KB RAM for FW code */ +#define CONFIG_PROGRAM_MEMORY_SIZE (224 * 1024) +/* program memory base address for 256KB RAM */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000 +#else +#error "Unsupported chip variant" +#endif + /* System stack size */ #define CONFIG_STACK_SIZE 4096 diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h index 0aeed1d417..22322271f0 100644 --- a/chip/npcx/config_flash_layout.h +++ b/chip/npcx/config_flash_layout.h @@ -35,11 +35,11 @@ /* RO firmware offset in flash */ #define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (96 * 1024) /* 96KB for RO FW */ +#define CONFIG_RO_SIZE CONFIG_PROGRAM_MEMORY_SIZE /* RW firmware offset in flash */ #define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE /* 96KB for RW FW */ +#define CONFIG_RW_SIZE CONFIG_RO_SIZE /* The storage offset of ec.R*.flat which is used for firmware_image.lds */ #define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE |