diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2016-04-28 12:09:55 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-29 07:34:52 -0700 |
| commit | 2b79492093935e3fe2aa2117216a819a3974d70b (patch) | |
| tree | f1827fc71dbdc8ca4c74284842c3227eb13c7be8 | |
| parent | 66473502c94b71b752e72907b062357f943d818c (diff) | |
| download | chrome-ec-2b79492093935e3fe2aa2117216a819a3974d70b.tar.gz | |
STM32: Set UART clock sources to SYSCLK
Since uart_freq_change assumes we drive UARTs at system clock, we need to
set UARTs clock sources accordingly. This will allow us to clock up the
chip without worrying about prescaler values set for HCLK and PCLK or the
on/off status of HSI.
BUG=none
BRANCH=tot
TEST=make buildall. Verified LPUART on stm32l476g-eval.
Change-Id: I02898921e31b68cacbc2235a29c47a212c350afe
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341260
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 8 | ||||
| -rw-r--r-- | chip/stm32/uart.c | 8 |
2 files changed, 13 insertions, 3 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 4a15c20d2d..70c846a683 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -608,8 +608,14 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) #define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) +#define STM32_RCC_CCIPR_PCLK 0 +#define STM32_RCC_CCIPR_SYSCLK 1 +#define STM32_RCC_CCIPR_HSI 2 +#define STM32_RCC_CCIPR_LSE 3 #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) +#define STM32_RCC_CCIPR_USART1SEL_MASK (2 << STM32_RCC_CCIPR_USART1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) +#define STM32_RCC_CCIPR_LPUART1SEL_MASK (2 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) #define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index d18b4b781a..8fbb6a3436 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -268,8 +268,12 @@ void uart_init(void) STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */ #endif /* UARTN */ #elif defined(CHIP_FAMILY_STM32L4) - STM32_RCC_CCIPR |= (0x2 << STM32_RCC_CCIPR_USART1SEL_SHIFT); - STM32_RCC_CCIPR |= (0x2 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT); + STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_USART1SEL_MASK; + STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_SYSCLK << + STM32_RCC_CCIPR_USART1SEL_SHIFT); + STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_LPUART1SEL_MASK; + STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_SYSCLK << + STM32_RCC_CCIPR_LPUART1SEL_SHIFT); #endif /* CHIP_FAMILY_STM32F0 || CHIP_FAMILY_STM32F3 */ /* Enable USART clock */ |