diff options
| author | Kevin K Wong <kevin.k.wong@intel.com> | 2016-05-02 16:17:42 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-05-03 15:40:46 -0700 |
| commit | e83c06bf90f89ea8c160c9f88b166d0c2e0a982d (patch) | |
| tree | c00f560bfb7cadafa0ab62df4e8ce6494ea68286 | |
| parent | b6ad3710c48b9f7a536808aac7d6e16b3d3a526d (diff) | |
| download | chrome-ec-e83c06bf90f89ea8c160c9f88b166d0c2e0a982d.tar.gz | |
apollolake: ignore PLTRST# from SOC unless RSMRST# is deasserted
add optional chipset specific function to check if PLTRST# is valid
BUG=chrome-os-partner:52656
BRANCH=none
TEST=make buildall, able to boot to OS on amenia
Change-Id: I7a2747c4f77f50393c3250c2ab0e1625e64e5a41
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/341732
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | chip/npcx/lpc.c | 7 | ||||
| -rw-r--r-- | include/chipset.h | 7 | ||||
| -rw-r--r-- | power/apollolake.c | 15 |
3 files changed, 25 insertions, 4 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index af945c820a..e29ed6c57b 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -6,6 +6,7 @@ /* LPC module for Chrome EC */ #include "acpi.h" +#include "chipset.h" #include "clock.h" #include "common.h" #include "console.h" @@ -756,11 +757,9 @@ void lpc_lreset_pltrst_handler(void) /* Clear pending bit of WUI */ SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7); -#ifdef GPIO_PCH_RSMRST_L - /* Ignore PLTRST# from SOC unless RSMRST# to soc is deasserted */ - if (!gpio_get_level(GPIO_PCH_RSMRST_L)) + /* Ignore PLTRST# from SOC if it is not valid */ + if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid()) return; -#endif ccprintf("[%T PLTRST deasserted]\n"); diff --git a/include/chipset.h b/include/chipset.h index 4b91a6e57f..ac50df0cc1 100644 --- a/include/chipset.h +++ b/include/chipset.h @@ -101,4 +101,11 @@ static inline void power_interrupt(enum gpio_signal signal) { } #endif /* !HAS_TASK_CHIPSET */ +/** + * Optional chipset check if PLTRST# is valid. + * + * @return non-zero if PLTRST# is valid, 0 if invalid. + */ +int chipset_pltrst_is_valid(void) __attribute__((weak)); + #endif /* __CROS_EC_CHIPSET_H */ diff --git a/power/apollolake.c b/power/apollolake.c index df486ff394..8e3449da08 100644 --- a/power/apollolake.c +++ b/power/apollolake.c @@ -450,3 +450,18 @@ void power_signal_interrupt_S0(enum gpio_signal signal) } } #endif + +/** + * chipset check if PLTRST# is valid. + * + * @return non-zero if PLTRST# is valid, 0 if invalid. + */ +int chipset_pltrst_is_valid(void) +{ + /* + * Invalid PLTRST# from SOC unless RSMRST# + * from PMIC through EC to soc is deasserted. + */ + return (gpio_get_level(GPIO_RSMRST_L_PGOOD) && + gpio_get_level(GPIO_PCH_RSMRST_L)); +} |