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authorDavid Hendricks <dhendrix@chromium.org>2016-06-03 17:03:52 -0700
committerchrome-bot <chrome-bot@chromium.org>2016-06-06 18:36:38 -0700
commit32ee71f6e012e927278d120b113901ae500549b2 (patch)
treeb279b954b2ac1e5c5a14151582a63e643eaf80d8
parentc59a51081d730087032fad13a8824f5ff1faea96 (diff)
downloadchrome-ec-32ee71f6e012e927278d120b113901ae500549b2.tar.gz
reef: Rename SMI/SCI GPIOs and enable CONFIG_SCI_GPIO
This updates SMI/SCI-related config options on Reef so that SMIs and SCIs are generated correctly. BUG=chrome-os-partner:53726 BRANCH=none TEST=built and booted on Reef EC, firmware seemed more stable (stayed up longer), but still see watchdog timesouts in task 13. Change-Id: I6717f48a7655e49207fe34e6a166957eb34a05fd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/349711 Reviewed-by: Shawn N <shawnn@chromium.org>
-rw-r--r--board/reef/board.h1
-rw-r--r--board/reef/gpio.inc4
2 files changed, 3 insertions, 2 deletions
diff --git a/board/reef/board.h b/board/reef/board.h
index 21136b2e31..08cbd7235a 100644
--- a/board/reef/board.h
+++ b/board/reef/board.h
@@ -78,6 +78,7 @@
#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
#define CONFIG_PWM
/* #define CONFIG_TEMP_SENSOR */
+#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
#define CONFIG_UART_HOST 0
#define CONFIG_VBOOT_HASH
#define CONFIG_WIRELESS
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc
index 0d8aa675ea..f26bbfaabe 100644
--- a/board/reef/gpio.inc
+++ b/board/reef/gpio.inc
@@ -58,8 +58,8 @@ GPIO(EC_I2C_POWER_SCL, PIN(9, 0), GPIO_INPUT)
* See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SPS option.
*/
-GPIO(EC_SMI_ODL, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
-GPIO(EC_SCI_ODL, PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SMI_ODL */
+GPIO(PCH_SCI_L, PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_SCI_ODL */
/*
* BRD_ID1 is a an ADC pin which will be used to measure multiple values.