diff options
| author | David Hendricks <dhendrix@chromium.org> | 2016-05-25 17:24:23 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-06-06 18:36:38 -0700 |
| commit | c59a51081d730087032fad13a8824f5ff1faea96 (patch) | |
| tree | 0f4d3804aeedada8efa53a6d26af9841450b7ef4 | |
| parent | 6672aa1be1d1eaaefb7fecc0ff697c4ff54dcf8d (diff) | |
| download | chrome-ec-c59a51081d730087032fad13a8824f5ff1faea96.tar.gz | |
reef: Don't set LPC pins in gpio.inc
The default mode for the LPC pins is actually LPC. Setting the
altnerate function mode makes them GPIOs.
BUG=none
BRANCH=none
TEST=build and booted on Reef EC. Didn't seem to make much of a
difference on its own but with the follow-up things seemed more
stable.
Change-Id: Ibbc62d23d8d909be48a9bec90da8acebb9905b50
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347443
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | board/reef/gpio.inc | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc index 81db6177d0..0d8aa675ea 100644 --- a/board/reef/gpio.inc +++ b/board/reef/gpio.inc @@ -36,11 +36,6 @@ GPIO(BASE_SIXAXIS_INT_L, PIN(9, 3), GPIO_INPUT | GPIO_SEL_1P8V) GPIO(LID_ACCEL_INT_L, PIN(C, 7), GPIO_INPUT | GPIO_SEL_1P8V) //GPIO_INT(TABLET_MODE, PIN(3, 6), GPIO_INT_BOTH | GPIO_PULL_HIGH, tablet_mode_interrupt) -/* KB interrupt from EC to PCH */ -ALTERNATE(PIN_MASK(5, 0x08), 0, MODULE_LPC, GPIO_INT_HIGH | GPIO_ODR_HIGH) /* FIXME(dhendrix): LPC_SERIRQ, INT_HIGH? */ -/* Use EC_PCH_KB_INT_ODL if SERIRQ doesn't work*/ -/* GPIO(EC_PCH_KB_INT_ODL, PIN(B, 0), GPIO_OPEN_DRAIN) */ - /* I2C GPIOs will be set to alt. function later */ GPIO(EC_I2C_GYRO_SDA, PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V) GPIO(EC_I2C_GYRO_SCL, PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V) @@ -53,8 +48,18 @@ GPIO(EC_I2C_USB_C1_PD_SCL, PIN(B, 3), GPIO_INPUT) GPIO(EC_I2C_POWER_SDA, PIN(8, 7), GPIO_INPUT) GPIO(EC_I2C_POWER_SCL, PIN(9, 0), GPIO_INPUT) -GPIO(EC_SMI_ODL, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) -GPIO(EC_SCI_ODL, PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V) +/* + * LPC: + * Pins 46, 47, 51, 52, 53, 54, 55, default to LPC mode. + * Pin 56 (CLKRUN#) defaults to GPIO mode. + * Pin 57 (SER_IRQ) defaults to LPC mode, but we also have EC_PCH_KB_INT_ODL + * (Pin B0) in case it doesn't work (Set CONFIG_KEYBOARD_IRQ_GPIO in this case). + * + * See also the NO_LPC_ESPI bit in DEVALT1 and the CONFIG_HOSTCMD_SPS option. + */ + +GPIO(EC_SMI_ODL, PIN(A, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) +GPIO(EC_SCI_ODL, PIN(A, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* * BRD_ID1 is a an ADC pin which will be used to measure multiple values. @@ -142,9 +147,6 @@ ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* GPOPB3-B2 for EC_I2C_USB_C1_PD ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* GPIO87 for EC_I2C_POWER_SDA */ ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0) /* GPIO90 for EC_I2C_POWER_SCL */ -ALTERNATE(PIN_MASK(4, 0xc0), 1, MODULE_LPC, 0) -ALTERNATE(PIN_MASK(5, 0x7e), 1, MODULE_LPC, 0) - ALTERNATE(PIN(8, 0), 4, MODULE_PWM, 0) /* RED_LED (PWM3) */ GPIO(GPIO_GREEN_LED, PIN(C, 4), GPIO_INPUT) |