diff options
| author | David Hendricks <dhendrix@chromium.org> | 2016-08-17 14:20:21 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-08-24 17:41:09 -0700 |
| commit | 9342bb62d7fbc0d507d57a67cd324bab2ef6f2ae (patch) | |
| tree | d1bbee0143be55184ecb4be142ab12dbe439428f | |
| parent | 862644b9bb53013bf947d5b25f2ebbc942159517 (diff) | |
| download | chrome-ec-9342bb62d7fbc0d507d57a67cd324bab2ef6f2ae.tar.gz | |
reef: Enable PMIC after 3.3V
This changes the ordering of rail/PMIC init slightly so that the
3.3V rail comes up before the PMIC, which follows the ordering
in the PMIC datasheet for cold booting.
The way we did it earlier was to avoid interrupt storms caused by
powering the SoC's GPIO block with SLP signals before powering the
PMIC. However the PMIC ignores the SLP signals when it's first
enabled, so while the suprious interrupts were visible on the scope
it's unlikely that the software was affected. OTOH, as Kevin pointed
out in CL:358913 enabling the PMIC before the 3.3V causes a race
condition whereby the PMIC may fault.
BUG=chrome-os-partner:51323
BRANCH=none
TEST=built and booted on EVT
Signed-off-by: Rachel Nancollas <rachelsn@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I6eb734f0600daa5de0d970ce228cf3e7ec97d01d
Reviewed-on: https://chromium-review.googlesource.com/372344
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | board/reef/board.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/board/reef/board.c b/board/reef/board.c index ce77746533..bb0aa55df9 100644 --- a/board/reef/board.c +++ b/board/reef/board.c @@ -375,14 +375,13 @@ static void chipset_pre_init(void) * To prevent SLP glitches, PMIC_EN (V5A_EN) should be enabled * at the same time as PP3300 (chrome-os-partner:51323). */ - - /* Enable PMIC */ - gpio_set_level(GPIO_PMIC_EN, 1); - /* Enable 3.3V rail */ gpio_set_level(GPIO_EN_PP3300, 1); while (!gpio_get_level(GPIO_PP3300_PG)) ; + + /* Enable PMIC */ + gpio_set_level(GPIO_PMIC_EN, 1); #endif } DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, chipset_pre_init, HOOK_PRIO_DEFAULT); |