Add eve_fp board

Eve FP MCU is using the STM32L442 microcontroller.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:62893
TEST=make BOARD=eve_fp
run it on Nucleo-L432KC (STM32L432KC is mostly the same MCU without AES)

Change-Id: I18dc57e9bf262c36283f8c835a2d4320bc5ee837
Reviewed-on: https://chromium-review.googlesource.com/442467
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

7 files changed, 152 insertions, 0 deletions

diff --git a/board/eve_fp/board.c b/board/eve_fp/board.c
new file mode 100644
index 0000000000..a84826833d
--- /dev/null
+++ b/board/eve_fp/board.c
@@ -0,0 +1,40 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "spi.h"
+#include "registers.h"
+
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+
+/* Interrupt line from the fingerprint senser */
+void fps_event(enum gpio_signal signal)
+{
+	/* HACK: Forward interrupt to AP */
+	gpio_set_level(GPIO_AP_INT, gpio_get_level(GPIO_FPS_INT));
+	CPRINTS("FPS %d\n", gpio_get_level(GPIO_FPS_INT));
+}
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	/* Fingerprint sensor */
+	{ CONFIG_SPI_FP_PORT, 1, GPIO_SPI3_NSS }
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/* Initialize board-specific configuraiton */
+static void board_init(void)
+{
+	/* Set all SPI master signal pins to very high speed: pins B3/B4/B5 */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00000fc0;
+	/* Enable clocks to SPI3 module (master) */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI3;
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/eve_fp/board.h b/board/eve_fp/board.h
new file mode 100644
index 0000000000..016b83733a
--- /dev/null
+++ b/board/eve_fp/board.h
@@ -0,0 +1,46 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Fingerprint microcontroller configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/*
+ * TODO(crosbug.com/p/62893)
+ * implement flash support for STM32L4
+ * and write protection.
+ */
+#undef  CONFIG_FLASH
+#undef  CONFIG_FLASH_PHYSICAL
+#define CONFIG_SYSTEM_UNLOCKED
+
+/* Serial console */
+#define CONFIG_UART_CONSOLE 1
+#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX
+#define CONFIG_UART_TX_DMA_PH 2
+
+/* Optional features */
+#define CONFIG_CMD_SPI_XFER
+#undef  CONFIG_LID_SWITCH
+#define CONFIG_SPI
+#define CONFIG_SPI_MASTER
+#define CONFIG_STM_HWTIMER32
+
+
+#define CONFIG_SPI_FP_PORT    1  /* SPI3: second SPI master port */
+
+/* Timer selection */
+#define TIM_CLOCK32     2
+#define TIM_WATCHDOG   16
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+
+void fps_event(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/eve_fp/build.mk b/board/eve_fp/build.mk
new file mode 100644
index 0000000000..5f1dc73bf9
--- /dev/null
+++ b/board/eve_fp/build.mk
@@ -0,0 +1,12 @@
+# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicroelectronics STM32L442KC
+CHIP:=stm32
+CHIP_FAMILY:=stm32l4
+CHIP_VARIANT:=stm32l442
+
+board-y=board.o
diff --git a/board/eve_fp/ec.tasklist b/board/eve_fp/ec.tasklist
new file mode 100644
index 0000000000..27e9de03aa
--- /dev/null
+++ b/board/eve_fp/ec.tasklist
@@ -0,0 +1,23 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
+
diff --git a/board/eve_fp/gpio.inc b/board/eve_fp/gpio.inc
new file mode 100644
index 0000000000..9ab359479e
--- /dev/null
+++ b/board/eve_fp/gpio.inc
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+GPIO_INT(FPS_INT,  PIN(A, 1), GPIO_INT_BOTH, fps_event)
+GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_UP,  spi_event)
+
+/* Outputs */
+GPIO(AP_INT,     PIN(A, 2), GPIO_ODR_HIGH | GPIO_PULL_UP)
+GPIO(FP_RST_ODL, PIN(A, 3), GPIO_ODR_HIGH)
+GPIO(SPI3_NSS,   PIN(A, 15), GPIO_OUT_HIGH)
+
+/* Unimplemented signals which we need to emulate for now */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
+
+/* USART1: PA9/10 */
+ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_F7, MODULE_UART, 0)
+/* SPI1 slave from PCH: PA5/6/7 */
+ALTERNATE(PIN_MASK(A, 0x00e0), GPIO_ALT_F5, MODULE_SPI,  0)
+/* SPI3 master to sensor: PB3/4/5 */
+ALTERNATE(PIN_MASK(B, 0x0038), GPIO_ALT_F6, MODULE_SPI_MASTER,  0)
diff --git a/include/config.h b/include/config.h
index 8550865556..3b2e6f3906 100644
--- a/include/config.h
+++ b/include/config.h
@@ -1848,6 +1848,9 @@
 /* SPI flash part supports SR2 register */
 #undef CONFIG_SPI_FLASH_HAS_SR2
 
+/* Define the SPI port to use to access the fingerprint sensor */
+#undef CONFIG_SPI_FP_PORT
+
 /* Support JEDEC SFDP based Serial NOR flash */
 #undef CONFIG_SPI_NOR
 
diff --git a/util/flash_ec b/util/flash_ec
index 9f3a531371..797d4b02b6 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -58,6 +58,7 @@ BOARDS_STM32=(
 	blaze
 	chell_pd
 	elm
+	eve_fp
 	glados_pd
 	hammer
 	honeybuns
@@ -375,6 +376,7 @@ function ec_uart() {
 case "${BOARD}" in
 	oak_pd|samus_pd|strago_pd ) MCU="usbpd" ;;
 	chell_pd|glados_pd ) MCU="usbpd" ;;
+	eve_fp ) MCU="usbpd" ;;
 	dingdong|hoho|twinkie ) DUT_CONTROL_CMD="true" ; MCU="ec" ;;
 	*) MCU="ec" ;;
 esac