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| author | Yidi Lin <yidi.lin@mediatek.com> | 2017-01-12 09:50:05 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-02-09 20:48:44 -0800 |
| commit | 9316ec321ab0708334f035c9e6090e592b0a8077 (patch) | |
| tree | c668737740ccc165e4f818727d0d91f3e3fd688e | |
| parent | 3a6431a3095d132e1212d9ef47a0732824cf2533 (diff) | |
| download | chrome-ec-9316ec321ab0708334f035c9e6090e592b0a8077.tar.gz | |
rowan: config SPI pins
Configure B12/B13/B14/B15 as SPI pins.
BRANCH=master
BUG=chrome-os-partner:62673
TEST=EC_FIRMWARE=rowan emerge-rowan chromeos-ec
Change-Id: Ia7aad9ba0e15a8e6b623a8ae37f76db3f8f7c7a5
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/427563
Commit-Ready: Patrick Berny <pberny@chromium.org>
Tested-by: Patrick Berny <pberny@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
| -rw-r--r-- | board/rowan/board.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/board/rowan/board.c b/board/rowan/board.c index 024c07dbfc..046e1e848d 100644 --- a/board/rowan/board.c +++ b/board/rowan/board.c @@ -421,10 +421,8 @@ static void board_chipset_pre_init(void) gpio_config_module(MODULE_SPI_MASTER, 1); /* Set all four SPI pins to high speed */ - /* pins D0/D1/D3/D4 */ - STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000003cf; - /* pins F6 */ - STM32_GPIO_OSPEEDR(GPIO_F) |= 0x00003000; + /* pins B12/B13/B14/B15 */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000; /* Enable clocks to SPI2 module */ STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; @@ -454,8 +452,7 @@ static void board_chipset_shutdown(void) * Calling gpio_config_module sets disabled alternate function pins to * GPIO_INPUT. But to prevent leakage we want to set GPIO_OUT_LOW */ - gpio_set_flags_by_mask(GPIO_D, 0x1a, GPIO_OUT_LOW); - gpio_set_level(GPIO_SPI2_NSS, 0); + gpio_set_flags_by_mask(GPIO_B, 0xf000, GPIO_OUT_LOW); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); |