stm32: add support for STM32L442

Should be close to the STM32L476 in the STM32L4 family.
Slightly different flash/RAM.

It's currently running from the internal clock (HSI) at 16Mhz,
we need to upgrade to 80Mhz (or 48Mhz if this is fast enough to save us
the PLL locking time).

The internal flash write/erase/protection is still not implemented for
the whole STM32L4 family.

Upgrade the SPI master support and verify that the TX works.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:62893
TEST=make BOARD=eve_fp
run it on Nucleo-L432KC (STM32L432KC is mostly the same MCU without AES)

Change-Id: I87be7d4461aedfbd683ff7bb639c3a6005ee171e
Reviewed-on: https://chromium-review.googlesource.com/442466
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

7 files changed, 98 insertions, 9 deletions

diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c
index 499c327baf..29c548e56e 100644
--- a/chip/stm32/clock-stm32l4.c
+++ b/chip/stm32/clock-stm32l4.c
@@ -29,7 +29,7 @@ enum clock_osc {
 	OSC_PLL,	/* PLL */
 };
 
-static int freq;
+static int freq = STM32_MSI_CLOCK;
 static int current_osc;
 
 int clock_get_freq(void)
diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h
new file mode 100644
index 0000000000..e9f3e04c53
--- /dev/null
+++ b/chip/stm32/config-stm32l442.h
@@ -0,0 +1,24 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Memory mapping */
+#define CONFIG_FLASH_SIZE  0x00040000   /* 256 kB */
+#define CONFIG_FLASH_BANK_SIZE  0x800   /* 2 kB */
+#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
+
+/* Ideal write size in page-mode */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
+
+/*
+ * SRAM1 (48kB) at 0x20000000
+ * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
+ * so they are contiguous.
+ */
+#define CONFIG_RAM_BASE         0x20000000
+#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT 82
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index cc1926dfab..0b79153113 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -36,6 +36,8 @@
 #include "config-stm32l15x.h"
 #elif defined(CHIP_VARIANT_STM32L100)
 #include "config-stm32l100.h"
+#elif defined(CHIP_VARIANT_STM32L442)
+#include "config-stm32l442.h"
 #elif defined(CHIP_VARIANT_STM32F446)
 #include "config-stm32f446.h"
 #elif defined(CHIP_VARIANT_STM32F373)
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 472d7595c7..5fde98d02c 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -77,6 +77,7 @@
 #define STM32_IRQ_USB_LP          20
 #endif
 
+#define STM32_IRQ_ADC1            18 /* STM32L4 only */
 #define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
 #define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
 #define STM32_IRQ_DAC             21
@@ -143,6 +144,8 @@
 #define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
 #define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
 #define STM32_IRQ_TIM19           78 /* STM32F373 only */
+#define STM32_IRQ_AES             79 /* STM32L4 only */
+#define STM32_IRQ_RNG             80 /* STM32L4 only */
 #define STM32_IRQ_FPU             81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
@@ -417,7 +420,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32_GPIOD_BASE            0x48000C00
 #define STM32_GPIOE_BASE            0x48001000
 #define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800	/* only for stm32l4 */
+#define STM32_GPIOG_BASE            0x48001800	/* only for stm32l4x6 */
 #define STM32_GPIOH_BASE            0x48001C00	/* only for stm32l4 */
 
 #define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
@@ -747,6 +750,13 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32_RCC_PLLCFGR_PLLR_SHIFT	(25)
 #define STM32_RCC_PLLCFGR_PLLR_MASK	(3 << STM32_RCC_PLLCFGR_PLLR_SHIFT)
 
+#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_APB1RSTR1             REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR2             REG32(STM32_RCC_BASE + 0x3C)
+#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x40)
+
 #define STM32_RCC_AHB1ENR		REG32(STM32_RCC_BASE + 0x48)
 #define STM32_RCC_AHB1ENR_DMA1EN	(1 << 0)
 #define STM32_RCC_AHB1ENR_DMA2EN	(1 << 1)
@@ -1160,7 +1170,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 /* --- SPI --- */
 #define STM32_SPI1_BASE             0x40013000
 #define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373 */
+#define STM32_SPI3_BASE             0x40003c00 /* STM32F373 and STM32L4 */
 
 /* The SPI controller registers */
 struct stm32_spi_regs {
@@ -1266,8 +1276,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_OPTB_WRP3L            0x18
 #define STM32_OPTB_WRP3H            0x1c
 
-#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-	defined(CHIP_FAMILY_STM32L4)
+#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
 #define STM32_FLASH_REGS_BASE       0x40022000
 
 #define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
@@ -1295,6 +1304,42 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 
 #define STM32_OPTB_COMPL_SHIFT      8
 
+#elif defined(CHIP_FAMILY_STM32L4)
+#define STM32_FLASH_REGS_BASE       0x40022000
+
+#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR_LATENCY_SHIFT (0)
+#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_PRFTEN      (1 << 8)
+#define STM32_FLASH_ACR_ICEN        (1 << 9)
+#define STM32_FLASH_ACR_DCEN        (1 << 10)
+#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define  FLASH_SR_BUSY              (1 << 16)
+#define  FLASH_SR_ERR_MASK          (0xc3fb)
+#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define  FLASH_CR_PG                (1 << 0)
+#define  FLASH_CR_PER               (1 << 1)
+#define  FLASH_CR_STRT              (1 << 16)
+#define  FLASH_CR_LOCK              (1 << 31)
+#define  FLASH_CR_PNB(sec)          (((sec) & 0xff) << 3)
+#define  FLASH_CR_PNB_MASK          FLASH_CR_SNB(0xff)
+#define STM32_FLASH_ECCR            REG32(STM32_FLASH_REGS_BASE + 0x18)
+#define STM32_FLASH_OPTR            REG32(STM32_FLASH_REGS_BASE + 0x20)
+#define STM32_FLASH_PCROP1SR        REG32(STM32_FLASH_REGS_BASE + 0x24)
+#define STM32_FLASH_PCROP1ER        REG32(STM32_FLASH_REGS_BASE + 0x28)
+#define STM32_FLASH_WRP1AR          REG32(STM32_FLASH_REGS_BASE + 0x2C)
+#define STM32_FLASH_WRP1BR          REG32(STM32_FLASH_REGS_BASE + 0x30)
+
+#define STM32_OPTB_BASE             0x1FFF7800
+
+#define STM32_OPTB_USER_RDP_OFF     0x00
+#define STM32_OPTB_WRP1A            0x18
+#define STM32_OPTB_WRP1B            0x20
+#define STM32_OPTB_COMPL_OFF        4
+
 #elif defined(CHIP_FAMILY_STM32F4)
 #define STM32_FLASH_REGS_BASE       0x40023c00
 
@@ -1818,6 +1863,10 @@ enum dma_channel {
 	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
 	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
 #ifdef CHIP_FAMILY_STM32L4
+	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
+	STM32_DMAC_SPI2_TX = STM32_DMAC_CH5,
+	STM32_DMAC_SPI3_RX = STM32_DMAC_CH9,
+	STM32_DMAC_SPI3_TX = STM32_DMAC_CH10,
 	STM32_DMAC_COUNT = 14,
 #elif defined(CHIP_VARIANT_STM32F373)
 	STM32_DMAC_SPI2_RX = STM32_DMAC_CH4,
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c
index f8cebc295d..c18191920a 100644
--- a/chip/stm32/spi_master.c
+++ b/chip/stm32/spi_master.c
@@ -11,6 +11,7 @@
 #include "gpio.h"
 #include "shared_mem.h"
 #include "spi.h"
+#include "stm32-dma.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
@@ -18,11 +19,19 @@
 /* The second (and third if available) SPI port are used as master */
 static stm32_spi_regs_t *SPI_REGS[] = {
 	STM32_SPI2_REGS,
-#ifdef CHIP_VARIANT_STM32F373
+#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4)
 	STM32_SPI3_REGS,
 #endif
 };
 
+#ifdef CHIP_FAMILY_STM32L4
+/* DMA request mapping on channels */
+static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
+	/* SPI2 */ 1,
+	/* SPI3 */ 3,
+};
+#endif
+
 static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
 
 #define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC)
@@ -33,7 +42,7 @@ static const struct dma_option dma_tx_option[] = {
 		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr,
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 	},
-#ifdef CHIP_VARIANT_STM32F373
+#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4)
 	{
 		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
@@ -46,7 +55,7 @@ static const struct dma_option dma_rx_option[] = {
 		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr,
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 	},
-#ifdef CHIP_VARIANT_STM32F373
+#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4)
 	{
 		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
@@ -77,6 +86,10 @@ static int spi_master_initialize(int port)
 	spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI |
 		(div << 3);
 
+#ifdef CHIP_FAMILY_STM32L4
+	dma_select_channel(dma_tx_option[port].channel, dma_req[port]);
+	dma_select_channel(dma_rx_option[port].channel, dma_req[port]);
+#endif
 	/*
 	 * Configure 8-bit datasize, set FRXTH, enable DMA,
 	 * and enable NSS output
diff --git a/chip/stm32/system.c b/chip/stm32/system.c
index 605f095f95..d296a90fa5 100644
--- a/chip/stm32/system.c
+++ b/chip/stm32/system.c
@@ -193,7 +193,7 @@ void system_pre_init(void)
 	clock_wait_bus_cycles(BUS_APB, 1);
 	/* Enable access to RCC CSR register and RTC backup registers */
 	STM32_PWR_CR |= 1 << 8;
-#ifdef CHIP_FAMILY_STM32L4
+#ifdef CHIP_VARIANT_STM32L476
 	/* Enable Vddio2 */
 	STM32_PWR_CR2 |= 1 << 9;
 #endif
diff --git a/util/stm32mon.c b/util/stm32mon.c
index d38b0ed930..aa395534ab 100644
--- a/util/stm32mon.c
+++ b/util/stm32mon.c
@@ -67,6 +67,7 @@ struct stm32_def {
 	{0x416, "STM32L15xxB",   0x08000000, 0x20000, 256, 13},
 	{0x429, "STM32L15xxB-A", 0x08000000, 0x20000, 256, 13},
 	{0x427, "STM32L15xxC",   0x08000000, 0x40000, 256, 13},
+	{0x435, "STM32L44xx",    0x08000000, 0x40000, 2048, 13},
 	{0x420, "STM32F100xx",   0x08000000, 0x20000, 1024, 13},
 	{0x410, "STM32F102R8",   0x08000000, 0x10000, 1024, 13},
 	{0x440, "STM32F05x",     0x08000000, 0x10000, 1024, 13},