npcx: i2c: Fix i2c freq setting when APB clock is 15 MHz

To configure 1 MHz speed when the APB clock is 15 MHz, the firmware
currently sets the SCLHT register to 4. However, we found out that
writing 4 to this register (and to SCLLT register) is illegal and
results in unexpected results.  So there is a need to write 5 in that
case. However, this means that the actual i2c frequency will be 750 KHz.
To get a higher i2c clock frequency, there is a need to run with a
higher APB clock (and a higher core clock). For example, with APB set to
20 MHz, the i2c clock frequency is 833 KHz.
In this CL, the i2c freq setting for APB clock=20 MHz is also added which
may be used for NPCX7 in the future.

BRANCH=none
BUG=chromium:714314
TEST=No build error for make buildall(except gru). Use scope to capture
SCL signal on npcx5 EVB and make sure its freqency is about 750 KHz.

Change-Id: I9025344e6df4b584b203c8c59bb9875250d9fe4f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/484202
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c
index a7af8632f0..6e36b01413 100644
--- a/chip/npcx/i2c.c
+++ b/chip/npcx/i2c.c
@@ -116,6 +116,7 @@ static const struct i2c_timing i2c_400k_timings[] = {
 	{40, 19, 66, 46},
 	{33, 17, 52, 38},
 	{24, 15, 38, 28},
+	{20, 13, 32, 20},
 	{15, 12, 24, 18},
 	{13, 11, 22, 16},
 	{12, 11, 20, 14},};
@@ -127,10 +128,10 @@ static const struct i2c_timing i2c_1m_timings[] = {
 	{40, 12, 26, 20},
 	{33, 11, 20, 16},
 	{24, 10, 16, 12},
-	{15,  9, 10,  8},};
+	{20, 10, 14, 10},
+	{15,  9, 10, 10},};
 const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings);
 
-
 int i2c_port_to_controller(int port)
 {
 	if (port < 0 || port >= I2C_PORT_COUNT)