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| author | Furquan Shaikh <furquan@chromium.org> | 2017-05-23 22:08:35 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-05-24 16:16:05 -0700 |
| commit | 9a4f6e8e2ef99e0ab654d9d08ca3487c8603d7d0 (patch) | |
| tree | 5e484bd16a6687ec505cbaa9bbe8b81d115cf32c | |
| parent | e58472daf82e86824471bbbc56b92de6ee048b3a (diff) | |
| download | chrome-ec-9a4f6e8e2ef99e0ab654d9d08ca3487c8603d7d0.tar.gz | |
poppy: Fix tcpc power mode handling for ANX
ANX has specific sequencing requirements for PWR_EN and RESETN when
entering active and standby modes. The order in which the two GPIOs
were set did not match the spec. Update board_set_tcpc_power_mode to
ensure correct ordering for both the modes.
BUG=b:62043928
BRANCH=None
TEST=make -j buildall
Change-Id: Ifc2991da87c7b7facd3384f752792371efb9fe1e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513477
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
| -rw-r--r-- | board/poppy/board.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/board/poppy/board.c b/board/poppy/board.c index c2cb27390d..bb548dafd5 100644 --- a/board/poppy/board.c +++ b/board/poppy/board.c @@ -345,10 +345,17 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) == /* called from anx74xx_set_power_mode() */ void board_set_tcpc_power_mode(int port, int mode) { - if (port == 0) { - gpio_set_level(GPIO_USB_C0_PD_RST_L, mode); - msleep(mode ? 10 : 1); - gpio_set_level(GPIO_USB_C0_TCPC_PWR, mode); + if (port != 0) + return; + + if (mode) { + gpio_set_level(GPIO_USB_C0_TCPC_PWR, 1); + msleep(10); + gpio_set_level(GPIO_USB_C0_PD_RST_L, 1); + } else { + gpio_set_level(GPIO_USB_C0_PD_RST_L, 0); + msleep(1); + gpio_set_level(GPIO_USB_C0_TCPC_PWR, 0); } } |