diff options
| author | Wei-Ning Huang <wnhuang@google.com> | 2017-05-07 13:48:22 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-06-20 04:12:14 -0700 |
| commit | 5f523464bb04b508e265de6304a92683742ffe2e (patch) | |
| tree | 3a5e2420d283cf74db920c1138939cc9cd54154a | |
| parent | ced1b4f90a1e1c28f45b152c3f17675f32233623 (diff) | |
| download | chrome-ec-5f523464bb04b508e265de6304a92683742ffe2e.tar.gz | |
stm32: flash: enable data and instruction cache properly
The flash controller of STM32F4 and STM32L4 supports data and
instruction caching. Enable them properly.
BRANCH=none
BUG=b:38077127
TEST=on rose,
> rw 0x40023c00
read 0x40023c00 = 0x00000701
Touch process loop is 5% faster.
Change-Id: Ibb28c0ed0c6a293547d5f0f7c6962f36fa417dd3
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/497230
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | chip/stm32/clock-f.c | 18 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 2 |
2 files changed, 19 insertions, 1 deletions
diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c index 1d28fa2168..e9737ddb14 100644 --- a/chip/stm32/clock-f.c +++ b/chip/stm32/clock-f.c @@ -165,14 +165,30 @@ void clock_init(void) * put 1 Wait-State for flash access to ensure proper reads at 48Mhz * and enable prefetch buffer. */ - /* Enable data and instruction cache. */ STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN; +#ifdef CHIP_FAMILY_STM32F4 + /* Enable data and instruction cache. */ + STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN; +#endif + config_hispeed_clock(); rtc_init(); } +#ifdef CHIP_FAMILY_STM32F4 +void reset_flash_cache(void) +{ + /* Disable data and instruction cache. */ + STM32_FLASH_ACR &= ~(STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN); + + /* Reset data and instruction cache */ + STM32_FLASH_ACR |= STM32_FLASH_ACR_DCRST | STM32_FLASH_ACR_ICRST; +} +DECLARE_HOOK(HOOK_SYSJUMP, reset_flash_cache, HOOK_PRIO_DEFAULT); +#endif + /*****************************************************************************/ /* Console commands */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 1e2cc14bd7..7616ea0355 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1356,6 +1356,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_ACR_PRFTEN (1 << 8) #define STM32_FLASH_ACR_ICEN (1 << 9) #define STM32_FLASH_ACR_DCEN (1 << 10) +#define STM32_FLASH_ACR_ICRST (1 << 11) +#define STM32_FLASH_ACR_DCRST (1 << 12) #define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) #define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) #define FLASH_KEYR_KEY1 0x45670123 |