npcx: clock: Add support for external 32kHz crystal osc.

In this CL, we add selecting LFCLK sources functionality for npcx7 ec
series. (Please notice not all of npcx7 ec series support this feature.)
Beside internal LFCLK source, ec also can choose the external 32kHz
crystal oscillator as LFCLK source for the specific application. We also
introduce a new definition, CONFIG_CLOCK_SRC_EXTERNAL, to switch this
feature in the board level driver.

This CL also adds:
1. LFCG register definitions in registers.h.
2. Change the order of each npcx modules by memory address.

BRANCH=none
BUG=none
TEST=Output LFCLK source through GPIO75. Compare with external 32kHz
crystal osc. on npcx7_evb and make sure the sources are the same.

Change-Id: I137146bf51ccb51266b9aac1e2e28bcea87dc4f5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/520745
Reviewed-by: Randall Spangler <rspangler@chromium.org>

4 files changed, 31 insertions, 4 deletions

diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h
index 1b00a4715a..0c93999497 100644
--- a/board/npcx7_evb/board.h
+++ b/board/npcx7_evb/board.h
@@ -57,6 +57,7 @@
 /* New features on npcx7 ec */
 #define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */
 #undef CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
+#undef CONFIG_CLOCK_SRC_EXTERNAL /* Use external 32kHz OSC as LFCLK source */
 
 /* Optional feature to configure npcx7 chip */
 #define NPCX_UART_MODULE2  0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index 17885b40e4..981cf503dc 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -88,6 +88,11 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
  */
 void clock_init(void)
 {
+#if defined(CONFIG_CLOCK_SRC_EXTERNAL) && defined(NPCX_EXT32K_OSC_SUPPORT)
+	/* Select external 32kHz crystal oscillator as LFCLK source. */
+	SET_BIT(NPCX_LFCGCTL2, NPCX_LFCGCTL2_XT_OSC_SL_EN);
+#endif
+
 	/*
 	 * Configure frequency multiplier M/N values according to
 	 * the requested OSC_CLK (Unit:Hz).
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index e07870cfc2..979833d5b0 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -65,16 +65,19 @@
 #define DEBUG_ESPI                       0
 
 /* Modules Map */
+#define NPCX_ESPI_BASE_ADDR              0x4000A000
 #define NPCX_MDC_BASE_ADDR               0x4000C000
-#define NPCX_SIB_BASE_ADDR               0x4000E000
 #define NPCX_PMC_BASE_ADDR               0x4000D000
+#define NPCX_SIB_BASE_ADDR               0x4000E000
+#define NPCX_SHI_BASE_ADDR               0x4000F000
 #define NPCX_SHM_BASE_ADDR               0x40010000
+#define NPCX_GDMA_BASE_ADDR              0x40011000
 #define NPCX_FIU_BASE_ADDR               0x40020000
 #define NPCX_KBSCAN_REGS_BASE            0x400A3000
 #define NPCX_GLUE_REGS_BASE              0x400A5000
 #define NPCX_BBRAM_BASE_ADDR             0x400AF000
 #define NPCX_HFCG_BASE_ADDR              0x400B5000
-#define NPCX_SHI_BASE_ADDR               0x4000F000
+#define NPCX_LFCG_BASE_ADDR              0x400B5100
 #define NPCX_MTC_BASE_ADDR               0x400B7000
 #define NPCX_MSWC_BASE_ADDR              0x400C1000
 #define NPCX_SCFG_BASE_ADDR              0x400C3000
@@ -84,8 +87,6 @@
 #define NPCX_SPI_BASE_ADDR               0x400D2000
 #define NPCX_PECI_BASE_ADDR              0x400D4000
 #define NPCX_TWD_BASE_ADDR               0x400D8000
-#define NPCX_ESPI_BASE_ADDR              0x4000A000
-#define NPCX_GDMA_BASE_ADDR              0x40011000
 
 /* Multi-Modules Map */
 #define NPCX_PWM_BASE_ADDR(mdl)          (0x40080000 + ((mdl) * 0x2000L))
@@ -271,6 +272,20 @@
 #define NPCX_HFCGCTRL_CLK_CHNG           7
 
 /******************************************************************************/
+/* Low Frequency Clock Generator (LFCG) registers */
+#define NPCX_LFCGCTL                      REG8(NPCX_LFCG_BASE_ADDR + 0x000)
+#define NPCX_HFRDI                       REG16(NPCX_LFCG_BASE_ADDR + 0x002)
+#define NPCX_HFRDF                       REG16(NPCX_LFCG_BASE_ADDR + 0x004)
+#define NPCX_FRCDIV                      REG16(NPCX_LFCG_BASE_ADDR + 0x006)
+#define NPCX_DIVCOR1                     REG16(NPCX_LFCG_BASE_ADDR + 0x008)
+#define NPCX_DIVCOR2                     REG16(NPCX_LFCG_BASE_ADDR + 0x00A)
+#define NPCX_LFCGCTL2                     REG8(NPCX_LFCG_BASE_ADDR + 0x014)
+
+/* LFCG register fields */
+#define NPCX_LFCGCTL_XTCLK_VAL            7
+#define NPCX_LFCGCTL2_XT_OSC_SL_EN        6
+
+/******************************************************************************/
 /*CR UART Register */
 #define NPCX_UTBUF                        REG8(NPCX_CR_UART_BASE_ADDR + 0x000)
 #define NPCX_URBUF                        REG8(NPCX_CR_UART_BASE_ADDR + 0x002)
diff --git a/include/config.h b/include/config.h
index 1058750fa0..cff891a433 100644
--- a/include/config.h
+++ b/include/config.h
@@ -624,6 +624,12 @@
 /* Indicate if a clock source is connected to stm32f4's "HSE" specific input */
 #undef CONFIG_STM32_CLOCK_HSE_HZ
 
+/*
+ * Chip config for clock source
+ *	 define = external crystal oscillator / undef = internal clock source
+ */
+#undef CONFIG_CLOCK_SRC_EXTERNAL
+
 /*****************************************************************************/
 /* Support curve25519 public key cryptography */
 #undef CONFIG_CURVE25519