nefario: initial board commit

Initial EC board support for nefario.
There will be more follow-up patches.

BUG=b:63408169
BRANCH=None
TEST=`make BOARD=nefario`

Change-Id: I8889e03e79d0240cb4374e3ab8e765fd9b32c7f5
Reviewed-on: https://chromium-review.googlesource.com/562977
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>

7 files changed, 1600 insertions, 0 deletions

diff --git a/board/nefario/battery.c b/board/nefario/battery.c
new file mode 100644
index 0000000000..29619884d8
--- /dev/null
+++ b/board/nefario/battery.c
@@ -0,0 +1,138 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "util.h"
+
+/* Shutdown mode parameter to write to manufacturer access register */
+#define SB_SHUTDOWN_DATA	0x0010
+
+static const struct battery_info info = {
+	.voltage_max		= 8688, /* 8700mA, round down for chg reg */
+	.voltage_normal		= 7600,
+	.voltage_min		= 5800,
+	.precharge_current	= 256,
+	.start_charging_min_c	= 0,
+	.start_charging_max_c	= 50,
+	.charging_min_c		= 0,
+	.charging_max_c		= 50,
+	.discharging_min_c	= -20,
+	.discharging_max_c	= 60,
+};
+
+const struct battery_info *battery_get_info(void)
+{
+	return &info;
+}
+
+int board_cut_off_battery(void)
+{
+	int rv;
+
+	/* Ship mode command must be sent twice to take effect */
+	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
+	if (rv != EC_SUCCESS)
+		return EC_RES_ERROR;
+
+	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
+	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
+}
+
+enum battery_disconnect_state battery_get_disconnect_state(void)
+{
+	uint8_t data[6];
+	int rv;
+
+	/*
+	 * Take note if we find that the battery isn't in disconnect state,
+	 * and always return NOT_DISCONNECTED without probing the battery.
+	 * This assumes the battery will not go to disconnect state during
+	 * runtime.
+	 */
+	static int not_disconnected;
+
+	if (not_disconnected)
+		return BATTERY_NOT_DISCONNECTED;
+
+	if (extpower_is_present()) {
+		/* Check if battery charging + discharging is disabled. */
+		rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
+				SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+		if (rv)
+			return BATTERY_DISCONNECT_ERROR;
+		if (~data[3] & (BATTERY_DISCHARGING_DISABLED |
+				BATTERY_CHARGING_DISABLED)) {
+			not_disconnected = 1;
+			return BATTERY_NOT_DISCONNECTED;
+		}
+
+		/*
+		 * Battery is neither charging nor discharging. Verify that
+		 * we didn't enter this state due to a safety fault.
+		 */
+		rv = sb_read_mfgacc(PARAM_SAFETY_STATUS,
+				SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+
+		if (rv || data[2] || data[3] || data[4] || data[5])
+			return BATTERY_DISCONNECT_ERROR;
+
+		/* No safety fault, battery is disconnected */
+		return BATTERY_DISCONNECTED;
+	}
+	not_disconnected = 1;
+	return BATTERY_NOT_DISCONNECTED;
+}
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	const struct battery_info *batt_info = battery_get_info();
+	int now_discharging;
+
+	/* battery temp in 0.1 deg C */
+	int bat_temp_c = curr->batt.temperature - 2731;
+
+	if (curr->state == ST_CHARGE) {
+		/* Don't charge if outside of allowable temperature range */
+		if (bat_temp_c >= batt_info->charging_max_c * 10 ||
+		    bat_temp_c < batt_info->charging_min_c * 10) {
+			curr->requested_current = curr->requested_voltage = 0;
+			curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
+			curr->state = ST_IDLE;
+			now_discharging = 0;
+		/* Don't start charging if battery is nearly full */
+		} else if (curr->batt.status & STATUS_FULLY_CHARGED) {
+			curr->requested_current = curr->requested_voltage = 0;
+			curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
+			curr->state = ST_DISCHARGE;
+			now_discharging = 1;
+		} else
+			now_discharging = 0;
+		charger_discharge_on_ac(now_discharging);
+	}
+
+	return 0;
+}
+
+/* Customs options controllable by host command. */
+#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/nefario/board.c b/board/nefario/board.c
new file mode 100644
index 0000000000..f17cca91e3
--- /dev/null
+++ b/board/nefario/board.c
@@ -0,0 +1,598 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "backlight.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "driver/accel_bma2x2.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/charger/bd9995x.h"
+#include "driver/tcpm/fusb302.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "registers.h"
+#include "shi_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "tcpm.h"
+#include "timer.h"
+#include "thermal.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+#ifdef HAS_TASK_PDCMD
+	/* Exchange status with TCPCs */
+	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
+#endif
+}
+
+static void overtemp_interrupt(enum gpio_signal signal)
+{
+	CPRINTS("AP wants shutdown");
+	chipset_force_shutdown();
+}
+
+static void warm_reset_request_interrupt(enum gpio_signal signal)
+{
+	CPRINTS("AP wants warm reset");
+	chipset_reset(0);
+}
+
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	[ADC_BOARD_ID] = {
+		"BOARD_ID", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+	[ADC_PP900_AP] = {
+		"PP900_AP", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+	[ADC_PP1200_LPDDR] = {
+		"PP1200_LPDDR", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+	[ADC_PPVAR_CLOGIC] = {
+		"PPVAR_CLOGIC",
+		NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+	[ADC_PPVAR_LOGIC] = {
+		"PPVAR_LOGIC", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************/
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	/* ArcticSand part on Gru requires >= 2.6KHz */
+	[PWM_CH_DISPLIGHT] = { 2, 0, 2600 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"tcpc0",   NPCX_I2C_PORT0_0, 1000, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
+	{"tcpc1",   NPCX_I2C_PORT0_1, 1000, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1},
+	{"sensors", NPCX_I2C_PORT1,    400, GPIO_I2C1_SCL,  GPIO_I2C1_SDA},
+	{"charger", NPCX_I2C_PORT2,    400, GPIO_I2C2_SCL,  GPIO_I2C2_SDA},
+	{"battery", NPCX_I2C_PORT3,    100, GPIO_I2C3_SCL,  GPIO_I2C3_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{GPIO_PP5000_PG,         1, "PP5000_PWR_GOOD"},
+	{GPIO_TPS65261_PG,       1, "SYS_PWR_GOOD"},
+	{GPIO_AP_CORE_PG,        1, "AP_PWR_GOOD"},
+	{GPIO_AP_EC_S3_S0_L,     0, "SUSPEND_DEASSERTED"},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/******************************************************************************/
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ CONFIG_SPI_ACCEL_PORT, 1, GPIO_SPI_SENSOR_CS_L }
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/******************************************************************************/
+/* Wake-up pins for hibernate */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_POWER_BUTTON_L, GPIO_CHARGER_INT_L, GPIO_LID_OPEN
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* Keyboard scan setting */
+struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 60,
+	.debounce_down_us = 6 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 1500,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = SECOND,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xc8  /* full set with lock key */
+	},
+};
+
+const struct button_config buttons[CONFIG_BUTTON_COUNT] = {
+	{"Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L,
+	 30 * MSEC, 0},
+	{"Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L,
+	 30 * MSEC, 0},
+};
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = {
+	{I2C_PORT_TCPC0, FUSB302_I2C_SLAVE_ADDR, &fusb302_tcpm_drv},
+	{I2C_PORT_TCPC1, FUSB302_I2C_SLAVE_ADDR, &fusb302_tcpm_drv},
+};
+
+struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = {
+	{
+		.port_addr = 0,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+	},
+	{
+		.port_addr = 1,
+		.driver = &virtual_usb_mux_driver,
+		.hpd_update = &virtual_hpd_update,
+	},
+};
+
+void board_reset_pd_mcu(void)
+{
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_L))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_L))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int board_set_active_charge_port(int charge_port)
+{
+	enum bd9995x_charge_port bd9995x_port;
+	int bd9995x_port_select = 1;
+	static int initialized;
+
+	/*
+	 * Reject charge port disable if our battery is critical and we
+	 * have yet to initialize a charge port - continue to charge using
+	 * charger ROM / POR settings.
+	 */
+	if (!initialized &&
+	    charge_port == CHARGE_PORT_NONE &&
+	    (charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON ||
+	    battery_get_disconnect_state() == BATTERY_DISCONNECTED)) {
+		CPRINTS("Bat critical, don't stop charging");
+		return -1;
+	}
+
+	CPRINTS("New chg p%d", charge_port);
+
+	switch (charge_port) {
+	case 0: case 1:
+		/* Don't charge from a source port */
+		if (board_vbus_source_enabled(charge_port))
+			return -1;
+
+		bd9995x_port = bd9995x_pd_port_to_chg_port(charge_port);
+		break;
+	case CHARGE_PORT_NONE:
+		bd9995x_port_select = 0;
+		bd9995x_port = BD9995X_CHARGE_PORT_BOTH;
+		break;
+	default:
+		panic("Invalid charge port\n");
+		break;
+	}
+
+	initialized = 1;
+	return bd9995x_select_input_port(bd9995x_port, bd9995x_port_select);
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma,
+			    int max_ma, int charge_mv)
+{
+	/*
+	 * Ignore lower charge ceiling on PD transition if our battery is
+	 * critical, as we may brownout.
+	 */
+	if (supplier == CHARGE_SUPPLIER_PD &&
+	    charge_ma < 1500 &&
+	    (charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON ||
+	    battery_get_disconnect_state() == BATTERY_DISCONNECTED)) {
+		CPRINTS("Using max ilim %d", max_ma);
+		charge_ma = max_ma;
+	}
+
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
+
+int extpower_is_present(void)
+{
+	int port;
+	int p0_src = board_vbus_source_enabled(0);
+	int p1_src = board_vbus_source_enabled(1);
+
+	/*
+	 * The charger will indicate VBUS presence if we're sourcing 5V,
+	 * so exclude such ports.
+	 */
+	if (p0_src && p1_src)
+		return 0;
+	else if (!p0_src && !p1_src)
+		port = BD9995X_CHARGE_PORT_BOTH;
+	else
+		port = bd9995x_pd_port_to_chg_port(p0_src);
+
+	return bd9995x_is_vbus_provided(port);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	enum bd9995x_charge_port bd9995x_port;
+
+	switch (port) {
+	case 0:
+	case 1:
+		bd9995x_port = bd9995x_pd_port_to_chg_port(port);
+		break;
+	default:
+		panic("Invalid charge port\n");
+		break;
+	}
+
+	return bd9995x_is_vbus_provided(bd9995x_port);
+}
+
+static void board_spi_enable(void)
+{
+	spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
+	     board_spi_enable,
+	     MOTION_SENSE_HOOK_PRIO - 1);
+
+/*
+ * Don't yank our SPI pins until we know HOOK_INIT has completed, since we
+ * do sensor initialization from HOOK_INIT.
+ */
+static int hook_init_done;
+
+static void hook_init_last(void)
+{
+	hook_init_done = 1;
+}
+DECLARE_HOOK(HOOK_INIT, hook_init_last, HOOK_PRIO_LAST + 1);
+
+static void board_spi_disable(void)
+{
+	while (!hook_init_done)
+		msleep(10);
+
+	spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
+	     board_spi_disable,
+	     MOTION_SENSE_HOOK_PRIO + 1);
+
+static void board_init(void)
+{
+	/* Enable TCPC alert interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_L);
+
+	/* Enable charger interrupt for BC1.2 detection on attach / detach */
+	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
+
+	/* Enable reboot / shutdown control inputs from AP */
+	gpio_enable_interrupt(GPIO_WARM_RESET_REQ);
+	gpio_enable_interrupt(GPIO_AP_OVERTEMP);
+
+	/* Enable interrupts from BMI160 sensor. */
+	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
+
+	/* Sensor Init */
+	if (system_jumped_to_this_image() && chipset_in_state(CHIPSET_STATE_ON))
+		board_spi_enable();
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	int i;
+	int rv;
+
+	/*
+	 * Disable the power enables for the TCPCs since we're going into
+	 * hibernate.  The charger VBUS interrupt will wake us up and reset the
+	 * EC.  Upon init, we'll reinitialize the TCPCs to be at full power.
+	 */
+	CPRINTS("Set TCPCs to low power");
+	for (i = 0; i < CONFIG_USB_PD_PORT_COUNT; i++) {
+		rv = tcpc_write(i, TCPC_REG_POWER, TCPC_REG_POWER_PWR_LOW);
+		if (rv)
+			CPRINTS("Error setting TCPC %d", i);
+	}
+
+	cflush();
+}
+
+enum nefario_board_version {
+	BOARD_VERSION_UNKNOWN = -1,
+	BOARD_VERSION_REV0 = 0,
+	BOARD_VERSION_REV1 = 1,
+	BOARD_VERSION_REV2 = 2,
+	BOARD_VERSION_REV3 = 3,
+	BOARD_VERSION_REV4 = 4,
+	BOARD_VERSION_REV5 = 5,
+	BOARD_VERSION_REV6 = 6,
+	BOARD_VERSION_REV7 = 7,
+	BOARD_VERSION_REV8 = 8,
+	BOARD_VERSION_REV9 = 9,
+	BOARD_VERSION_REV10 = 10,
+	BOARD_VERSION_REV11 = 11,
+	BOARD_VERSION_REV12 = 12,
+	BOARD_VERSION_REV13 = 13,
+	BOARD_VERSION_REV14 = 14,
+	BOARD_VERSION_REV15 = 15,
+	BOARD_VERSION_COUNT,
+};
+
+struct {
+	enum nefario_board_version version;
+	int expect_mv;
+} const nefario_boards[] = {
+	{ BOARD_VERSION_REV0, 109 },   /* 51.1K , 2.2K(gru 3.3K) ohm */
+	{ BOARD_VERSION_REV1, 211 },   /* 51.1k , 6.8K ohm */
+	{ BOARD_VERSION_REV2, 319 },   /* 51.1K , 11K ohm */
+	{ BOARD_VERSION_REV3, 427 },   /* 56K   , 17.4K ohm */
+	{ BOARD_VERSION_REV4, 542 },   /* 51.1K , 22K ohm */
+	{ BOARD_VERSION_REV5, 666 },   /* 51.1K , 30K ohm */
+	{ BOARD_VERSION_REV6, 781 },   /* 51.1K , 39.2K ohm */
+	{ BOARD_VERSION_REV7, 900 },   /* 56K   , 56K ohm */
+	{ BOARD_VERSION_REV8, 1023 },  /* 47K   , 61.9K ohm */
+	{ BOARD_VERSION_REV9, 1137 },  /* 47K   , 80.6K ohm */
+	{ BOARD_VERSION_REV10, 1240 }, /* 56K   , 124K ohm */
+	{ BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */
+	{ BOARD_VERSION_REV12, 1457 }, /* 47K   , 200K ohm */
+	{ BOARD_VERSION_REV13, 1576 }, /* 47K   , 330K ohm */
+	{ BOARD_VERSION_REV14, 1684 }, /* 47K   , 680K ohm */
+	{ BOARD_VERSION_REV15, 1800 }, /* 56K   , NC */
+};
+BUILD_ASSERT(ARRAY_SIZE(nefario_boards) == BOARD_VERSION_COUNT);
+
+#define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */
+
+int board_get_version(void)
+{
+	static int version = BOARD_VERSION_UNKNOWN;
+	int mv;
+	int i;
+
+	if (version != BOARD_VERSION_UNKNOWN)
+		return version;
+
+	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 0);
+	/* Wait to allow cap charge */
+	msleep(10);
+	mv = adc_read_channel(ADC_BOARD_ID);
+
+	/* TODO(crosbug.com/p/54971): Fix failure on first ADC conversion. */
+	if (mv == ADC_READ_ERROR)
+		mv = adc_read_channel(ADC_BOARD_ID);
+
+	gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 1);
+
+	for (i = 0; i < BOARD_VERSION_COUNT; ++i) {
+		if (mv < nefario_boards[i].expect_mv + THRESHOLD_MV) {
+			version = nefario_boards[i].version;
+			break;
+		}
+	}
+
+	return version;
+}
+
+/* Motion sensors */
+#ifdef HAS_TASK_MOTIONSENSE
+/* Mutexes */
+static struct mutex g_base_mutex;
+struct bmi160_drv_data_t g_bmi160_data;
+
+/* Matrix to rotate accelerometer into standard reference frame */
+const matrix_3x3_t base_standard_ref = {
+	{ FLOAT_TO_FP(-1), 0,  0},
+	{ 0,  FLOAT_TO_FP(1),  0},
+	{ 0,  0, FLOAT_TO_FP(-1)}
+};
+
+const matrix_3x3_t lid_standard_ref = {
+	{ 0, FLOAT_TO_FP(1),  0},
+	{ FLOAT_TO_FP(-1), 0, 0},
+	{ 0,  0, FLOAT_TO_FP(1)}
+};
+
+struct motion_sensor_t motion_sensors[] = {
+	/*
+	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Requirement: accelerometer sensor must init before gyro sensor
+	 * DO NOT change the order of the following table.
+	 */
+	[BASE_ACCEL] = {
+	 .name = "Base Accel",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_ACCEL,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .addr = BMI160_SET_SPI_ADDRESS(CONFIG_SPI_ACCEL_PORT),
+	 .rot_standard_ref = &base_standard_ref,
+	 .default_range = 2,  /* g, enough for laptop. */
+	 .config = {
+		 /* AP: by default use EC settings */
+		 [SENSOR_CONFIG_AP] = {
+			 .odr = 0,
+			 .ec_rate = 0,
+		 },
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 10000 | ROUND_UP_FLAG,
+			 .ec_rate = 100 * MSEC,
+		 },
+		 /* EC use accel for angle detection */
+		 [SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 0,
+		 },
+		 /* Sensor off in S3/S5 */
+		 [SENSOR_CONFIG_EC_S5] = {
+			 .odr = 0,
+			 .ec_rate = 0
+		 },
+	 },
+	},
+	[BASE_GYRO] = {
+	 .name = "Base Gyro",
+	 .active_mask = SENSOR_ACTIVE_S0_S3,
+	 .chip = MOTIONSENSE_CHIP_BMI160,
+	 .type = MOTIONSENSE_TYPE_GYRO,
+	 .location = MOTIONSENSE_LOC_BASE,
+	 .drv = &bmi160_drv,
+	 .mutex = &g_base_mutex,
+	 .drv_data = &g_bmi160_data,
+	 .port = CONFIG_SPI_ACCEL_PORT,
+	 .addr = BMI160_SET_SPI_ADDRESS(CONFIG_SPI_ACCEL_PORT),
+	 .default_range = 1000, /* dps */
+	 .rot_standard_ref = NULL, /* Identity matrix. */
+	 .config = {
+		 /* AP: by default shutdown all sensors */
+		 [SENSOR_CONFIG_AP] = {
+			 .odr = 0,
+			 .ec_rate = 0,
+		 },
+		 /* EC does not need in S0 */
+		 [SENSOR_CONFIG_EC_S0] = {
+			 .odr = 0,
+			 .ec_rate = 0,
+		 },
+		 /* Sensor off in S3/S5 */
+		 [SENSOR_CONFIG_EC_S3] = {
+			 .odr = 0,
+			 .ec_rate = 0,
+		 },
+		 /* Sensor off in S3/S5 */
+		 [SENSOR_CONFIG_EC_S5] = {
+			 .odr = 0,
+			 .ec_rate = 0,
+		 },
+	 },
+	},
+};
+const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+#endif /* defined(HAS_TASK_MOTIONSENSE) */
+
+#ifndef TEST_BUILD
+void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+#endif
+
+static void usb_charge_resume(void)
+{
+	/* Turn on USB-A ports on as we go into S0 from S3. */
+	gpio_set_level(GPIO_USB_A_EN, 1);
+	gpio_set_level(GPIO_USB_A_CHARGE_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, usb_charge_resume, HOOK_PRIO_DEFAULT);
+
+static void usb_charge_shutdown(void)
+{
+	/* Turn off USB-A ports as we go back to S5. */
+	gpio_set_level(GPIO_USB_A_CHARGE_EN, 0);
+	gpio_set_level(GPIO_USB_A_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_charge_shutdown, HOOK_PRIO_DEFAULT);
+
+#define PWM_DISPLIGHT_SYSJUMP_TAG 0x5044 /* "PD" */
+#define PWM_HOOK_VERSION 1
+
+static void pwm_displight_restore_state(void)
+{
+	const int *prev;
+	int version, size;
+
+	prev = (const int *)system_get_jump_tag(PWM_DISPLIGHT_SYSJUMP_TAG,
+						&version, &size);
+	if (prev && version == PWM_HOOK_VERSION && size == sizeof(*prev))
+		pwm_set_raw_duty(PWM_CH_DISPLIGHT, *prev);
+}
+DECLARE_HOOK(HOOK_INIT, pwm_displight_restore_state, HOOK_PRIO_INIT_PWM + 1);
+
+static void pwm_displight_preserve_state(void)
+{
+	int pwm_displight_duty = pwm_get_raw_duty(PWM_CH_DISPLIGHT);
+
+	system_add_jump_tag(PWM_DISPLIGHT_SYSJUMP_TAG, PWM_HOOK_VERSION,
+			    sizeof(pwm_displight_duty), &pwm_displight_duty);
+}
+DECLARE_HOOK(HOOK_SYSJUMP, pwm_displight_preserve_state, HOOK_PRIO_DEFAULT);
+
+int board_allow_i2c_passthru(int port)
+{
+	return (port == I2C_PORT_VIRTUAL_BATTERY);
+}
diff --git a/board/nefario/board.h b/board/nefario/board.h
new file mode 100644
index 0000000000..58e8eb372f
--- /dev/null
+++ b/board/nefario/board.h
@@ -0,0 +1,242 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Nefario */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Optional modules */
+#define CONFIG_ADC
+#define CONFIG_CHIPSET_RK3399
+#define CONFIG_CMD_RTC
+#define CONFIG_HOSTCMD_RTC
+#define CONFIG_HOSTCMD_SPS
+#define CONFIG_I2C
+#define CONFIG_I2C_MASTER
+#define CONFIG_I2C_VIRTUAL_BATTERY
+#define CONFIG_I2C_PASSTHRU_RESTRICTED
+#define CONFIG_LED_COMMON
+#define CONFIG_LED_POLICY_STD
+#define CONFIG_LED_BAT_ACTIVE_LOW
+#define CONFIG_LED_POWER_ACTIVE_LOW
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_POWER_COMMON
+#define CONFIG_PWM
+#define CONFIG_PWM_DISPLIGHT
+#define CONFIG_SPI
+#define CONFIG_SPI_MASTER
+#define CONFIG_SPI_FLASH_GD25LQ40
+#define CONFIG_SPI_FLASH_REGS
+
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
+
+/*
+ * We are code space-constrained on nefario, so take 10K that is normally used
+ * as data RAM (was 30K, now 22K) and use it for code RAM (was 96K, now 104K)
+ */
+#define RAM_SHIFT_SIZE (8 * 1024)
+#undef  CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE (NPCX_PROGRAM_MEMORY_SIZE + RAM_SHIFT_SIZE)
+#undef  CONFIG_RAM_BASE
+#define CONFIG_RAM_BASE (0x200C0000 + RAM_SHIFT_SIZE)
+#undef  CONFIG_RAM_SIZE
+#define CONFIG_RAM_SIZE (0x00008000 - 0x800 - RAM_SHIFT_SIZE)
+/* Region sizes are no longer a power of 2 so we can't enable MPU */
+#undef  CONFIG_MPU
+
+/* Optional features */
+#define CONFIG_BOARD_VERSION
+#define CONFIG_BOARD_SPECIFIC_VERSION
+#define CONFIG_BUTTON_COUNT        2
+#define CONFIG_FLASH_SIZE          0x00080000 /* 512KB spi flash */
+#define CONFIG_HOST_COMMAND_STATUS
+/* By default, set hcdebug to off */
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard */
+#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
+#define CONFIG_LTO
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_SOFTWARE_PANIC
+#define CONFIG_VBOOT_HASH
+
+#define CONFIG_CHARGER
+#define CONFIG_CHARGER_BD99955
+#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_MAINTAIN_VBAT
+#define CONFIG_CHARGER_V2
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2
+#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 2
+#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_USB_CHARGER
+#define CONFIG_USB_MUX_VIRTUAL
+
+/* Increase tx buffer size, as we'd like to stream EC log to AP. */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Motion Sensors */
+#define CONFIG_ACCEL_BMA255
+#define CONFIG_ACCEL_KX022
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCEL_INTERRUPTS
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT TASK_EVENT_CUSTOM(4)
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_INVALID_CHECK
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE    BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID     LID_ACCEL
+/* FIFO size is in power of 2. */
+#define CONFIG_ACCEL_FIFO 256
+#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO / 3)
+
+/*
+ * Sensor internal FIFO is enabled for BMI160, but not for BMA255.
+ */
+#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
+
+/* USB PD config */
+#define CONFIG_CASE_CLOSED_DEBUG_EXTERNAL
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_CUSTOM_VDM
+#define CONFIG_USB_PD_DISCHARGE
+#define CONFIG_USB_PD_DISCHARGE_GPIO
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_LOG_SIZE 512
+#define CONFIG_USB_PD_PORT_COUNT 2
+#define CONFIG_USB_PD_TCPM_FUSB302
+#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
+#define CONFIG_USB_PD_VBUS_DETECT_CHARGER
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_USB_PD_COMM_LOCKED
+
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_SMART
+
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW       60000
+#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_VOLTAGE_MV     20000
+
+#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000  /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* Optional features for test commands */
+#define CONFIG_CMD_CHARGER_PSYS
+
+/* Set PSYS gain for 50W max measurement */
+#define BD99955_PSYS_GAIN_SELECT \
+		BD99955_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_08UAW
+
+#define CONFIG_UART_HOST                0
+
+/* Optional feature - used by nuvoton */
+#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_TACH_SEL2       0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */
+/* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */
+#define NPCX_SHI_CS_PU
+#define NPCX_SHI_BYPASS_OVER_256B
+
+/* Optional for testing */
+#undef  CONFIG_PECI
+#undef  CONFIG_PSTORE
+
+/* Modules we want to exclude */
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_CHARGER_PSYS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_HASH
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_MD
+#undef CONFIG_CMD_POWERINDEBUG
+#undef CONFIG_CMD_TIMERINFO
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+/*
+ * Remove task profiling to improve SHI interrupt latency.
+ * TODO(crosbug.com/p/55710): Re-define once interrupt latency is within
+ * tolerance.
+ */
+#undef CONFIG_TASK_PROFILING
+
+#define I2C_PORT_TCPC0    NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1    NPCX_I2C_PORT0_1
+#define I2C_PORT_ACCEL    NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER  NPCX_I2C_PORT2
+#define I2C_PORT_BATTERY  NPCX_I2C_PORT3
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+
+/* Enable Accel over SPI */
+#define CONFIG_SPI_ACCEL_PORT    0  /* SPI master port (SPIP) form BMI160 */
+
+#define CONFIG_MKBP_EVENT
+/* Define the MKBP events which are allowed to wakeup AP in S3. */
+#define CONFIG_MKBP_WAKEUP_MASK \
+		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
+		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
+
+#ifndef __ASSEMBLER__
+
+enum adc_channel {
+	/* Real ADC channels begin here */
+	ADC_BOARD_ID = 0,
+	ADC_PP900_AP,
+	ADC_PP1200_LPDDR,
+	ADC_PPVAR_CLOGIC,
+	ADC_PPVAR_LOGIC,
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_DISPLIGHT,
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+/* power signal definitions */
+enum power_signal {
+	PP5000_PWR_GOOD = 0,
+	SYS_PWR_GOOD,
+	AP_PWR_GOOD,
+	SUSPEND_DEASSERTED,
+
+	/* Number of signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* Motion sensors */
+enum sensor_id {
+	BASE_ACCEL = 0,
+	BASE_GYRO,
+	LID_ACCEL,
+};
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+void board_reset_pd_mcu(void);
+int board_get_version(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/nefario/build.mk b/board/nefario/build.mk
new file mode 100644
index 0000000000..98be206edc
--- /dev/null
+++ b/board/nefario/build.mk
@@ -0,0 +1,13 @@
+# -*- makefile -*-
+# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+# the IC is Nuvoton M-Series EC (npcx5m5g, npcx5m6g)
+CHIP:=npcx
+CHIP_VARIANT:=npcx5m5g
+
+board-y=battery.o board.o usb_pd_policy.o
diff --git a/board/nefario/ec.tasklist b/board/nefario/ec.tasklist
new file mode 100644
index 0000000000..2ad1c7eedd
--- /dev/null
+++ b/board/nefario/ec.tasklist
@@ -0,0 +1,31 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' is the name of the task
+ * 'r' is the main routine of the task
+ * 'd' is an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
+
diff --git a/board/nefario/gpio.inc b/board/nefario/gpio.inc
new file mode 100644
index 0000000000..92397e7577
--- /dev/null
+++ b/board/nefario/gpio.inc
@@ -0,0 +1,169 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+
+GPIO_INT(WP_L,             PIN(9, 3), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(SHI_CS_L,         PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN,
+         shi_cs_event)
+GPIO_INT(USB_C0_PD_INT_L,  PIN(6, 0), GPIO_INT_FALLING | GPIO_PULL_UP,
+         tcpc_alert_event)
+GPIO_INT(USB_C1_PD_INT_L,  PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP,
+         tcpc_alert_event)
+GPIO_INT(VOLUME_UP_L,      PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt)
+GPIO_INT(VOLUME_DOWN_L,    PIN(8, 3), GPIO_INT_BOTH | GPIO_PULL_UP,
+         button_interrupt)
+GPIO_INT(POWER_BUTTON_L,   PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,
+         power_button_interrupt)
+GPIO_INT(LID_OPEN,         PIN(9, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
+         lid_interrupt)
+
+GPIO_INT(PP5000_PG,        PIN(7, 1), GPIO_INT_BOTH | GPIO_PULL_UP,
+         power_signal_interrupt)
+GPIO_INT(TPS65261_PG,      PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,
+         power_signal_interrupt)
+/* TODO: Remove PD in S3 for power savings */
+GPIO_INT(AP_EC_S3_S0_L,    PIN(C, 1), GPIO_INT_BOTH | GPIO_PULL_DOWN,
+         power_signal_interrupt)
+GPIO_INT(AP_CORE_PG,       PIN(6, 7), GPIO_INT_BOTH | GPIO_PULL_UP,
+         power_signal_interrupt)
+GPIO_INT(WARM_RESET_REQ,   PIN(7, 3), GPIO_INT_RISING | GPIO_PULL_DOWN,
+         warm_reset_request_interrupt)
+GPIO_INT(AP_OVERTEMP,      PIN(7, 4), GPIO_INT_RISING | GPIO_PULL_DOWN,
+         overtemp_interrupt)
+GPIO_INT(CHARGER_INT_L,    PIN(3, 3), GPIO_INT_FALLING | GPIO_PULL_UP,
+         bd9995x_vbus_interrupt)
+GPIO_INT(BASE_SIXAXIS_INT_L,PIN(4, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V,
+         bmi160_interrupt)
+
+/* VR EN */
+GPIO(AP_CORE_EN,           PIN(7, 2), GPIO_OUT_LOW)
+GPIO(LPDDR_PWR_EN,         PIN(8, 6), GPIO_OUT_LOW)
+GPIO(PPVAR_CLOGIC_EN,      PIN(C, 5), GPIO_OUT_LOW)
+GPIO(PPVAR_LOGIC_EN,       PIN(8, 5), GPIO_OUT_LOW)
+
+GPIO(PP900_AP_EN,          PIN(B, 7), GPIO_OUT_LOW)
+GPIO(PP900_DDRPLL_EN,      PIN(C, 0), GPIO_OUT_LOW)
+GPIO(PP900_PLL_EN,         PIN(5, 4), GPIO_OUT_LOW)
+GPIO(PP900_PMU_EN,         PIN(C, 2), GPIO_OUT_LOW)
+GPIO(PP900_USB_EN,         PIN(A, 5), GPIO_OUT_LOW)
+GPIO(PP900_PCIE_EN,        PIN(0, 0), GPIO_OUT_LOW)
+
+/* NC */
+GPIO(GPIO81_NC,            PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+
+GPIO(PP1800_SENSOR_EN_L,   PIN(A, 7), GPIO_OUT_HIGH)
+GPIO(PP1800_USB_EN_L,      PIN(A, 6), GPIO_OUT_HIGH)
+GPIO(PP1800_LID_EN_L,      PIN(B, 0), GPIO_OUT_HIGH)
+GPIO(PP1800_PMU_EN_L,      PIN(5, 1), GPIO_OUT_HIGH)
+GPIO(PP1800_AP_AVDD_EN_L,  PIN(5, 2), GPIO_OUT_HIGH)
+GPIO(PP1800_S0_EN_L,       PIN(5, 0), GPIO_OUT_HIGH)
+GPIO(PP1800_SIXAXIS_EN_L,  PIN(5, 6), GPIO_OUT_HIGH)
+
+GPIO(PP3300_TRACKPAD_EN_L, PIN(3, 2), GPIO_OUT_HIGH)
+GPIO(PP3300_USB_EN_L,      PIN(3, 7), GPIO_OUT_HIGH)
+
+GPIO(PP5000_EN,            PIN(C, 6), GPIO_OUT_LOW)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(I2C0_SCL0,            PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C0_SDA0,            PIN(B, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C0_SCL1,            PIN(B, 3), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C0_SDA1,            PIN(B, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C1_SCL,             PIN(9, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C1_SDA,             PIN(8, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C2_SCL,             PIN(9, 2), GPIO_ODR_HIGH)
+GPIO(I2C2_SDA,             PIN(9, 1), GPIO_ODR_HIGH)
+GPIO(I2C3_SCL,             PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(I2C3_SDA,             PIN(D, 0), GPIO_ODR_HIGH)
+
+/* Attached to push-pull interrupt pin of accel, but unused */
+GPIO(LID_ACCEL_INT_L,      PIN(C, 7), GPIO_INPUT)
+
+/* KSO2 is inverted */
+GPIO(KBD_KSO2,             PIN(1, 7), GPIO_OUT_LOW)
+
+GPIO(USB_C0_5V_EN,       PIN(D, 3), GPIO_OUT_LOW | GPIO_PULL_UP)
+GPIO(USB_C1_5V_EN,       PIN(D, 2), GPIO_OUT_LOW | GPIO_PULL_UP)
+
+GPIO(ENTERING_RW,          PIN(7, 6), GPIO_OUT_LOW)
+GPIO(SYS_RST_L,            PIN(6, 1), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(EC_INT_L,             PIN(5, 7), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(EC_BOARD_ID_EN_L,     PIN(3, 5), GPIO_OUT_HIGH)
+
+GPIO(USB_DP_HPD,           PIN(6, 6), GPIO_OUT_LOW)
+GPIO(CHARGER_RESET_L,      PIN(0, 1), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(TPM_ALLOW_RST,        PIN(0, 2), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(EC_BATT_PRES_L,       PIN(3, 4), GPIO_INPUT)
+GPIO(LID_360_L,            PIN(3, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(CCD_MODE_ODL,         PIN(6, 3), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(PP3300_S0_EN_L,       PIN(7, 0), GPIO_OUT_HIGH)
+GPIO(SPI_SENSOR_CS_L,      PIN(9, 4), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+
+GPIO(USB_C0_DISCHARGE,     PIN(0, 3), GPIO_OUT_LOW)
+GPIO(USB_C1_DISCHARGE,     PIN(B, 1), GPIO_OUT_LOW)
+
+GPIO(USB_A_EN,             PIN(C, 3), GPIO_OUT_LOW)
+GPIO(USB_A_CHARGE_EN,      PIN(8, 4), GPIO_OUT_LOW)
+
+/* Nefario LEDs */
+GPIO(POWER_LED,            PIN(B, 6), GPIO_OUT_LOW)
+GPIO(BAT_LED_GREEN,        PIN(4, 4), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(BAT_LED_RED,          PIN(8, 0), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+
+/*
+ * SPI host interface - enable PDs by default. These will be made functional
+ * by the SHI driver when the AP powers up, and restored back to GPIO when
+ * the AP powers down.
+ */
+GPIO(SHI_SDI,              PIN(4, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(SHI_SDO,              PIN(4, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(SHI_SCLK,             PIN(5, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+
+/* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
+ALTERNATE(PIN_MASK(A, 0x0A), 1,  MODULE_SPI,           0)
+/* SPIP_MISO GPIO95 */
+ALTERNATE(PIN_MASK(9, 0x20), 1,  MODULE_SPI,           0)
+/* I2C0SDA1/I2C0SCL1 GPIOB2/B3 */
+ALTERNATE(PIN_MASK(B, 0x0C), 1,  MODULE_I2C,           0)
+/* I2C0SDA0/I2C0SCL0 GPIOB4/B5 */
+ALTERNATE(PIN_MASK(B, 0x30), 1,  MODULE_I2C,           0)
+/* I2C1SDA GPIO87 */
+ALTERNATE(PIN_MASK(8, 0x80), 1,  MODULE_I2C,           0)
+/* I2C1SCL/I2C2SDA/I2C2SCL GPIO90/91/92 */
+ALTERNATE(PIN_MASK(9, 0x07), 1,  MODULE_I2C,           0)
+/* I2C3SDA/I2C3SCL GPIOD0/D1    */
+ALTERNATE(PIN_MASK(D, 0x03), 1,  MODULE_I2C,           0)
+/* PWM2 / BLPWM */
+ALTERNATE(PIN_MASK(C, 0x10), 1,  MODULE_PWM,           0)
+/* PWM3 / LED_RED(net LED_CHARGE) */
+ALTERNATE(PIN_MASK(8, 0x01), 1,  MODULE_PWM,           0)
+
+/* CR_SIN/SOUT GPIO64/65 */
+ALTERNATE(PIN_MASK(6, 0x30), 1,  MODULE_UART,          GPIO_PULL_UP)
+/* ADC0-4 */
+ALTERNATE(PIN_MASK(4, 0x3e), 1,  MODULE_ADC,           0)
+
+/* Keyboard Columns */
+ALTERNATE(PIN_MASK(0, 0xE0), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(1, 0x7F), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
+
+/* Keyboard Rows */
+ALTERNATE(PIN_MASK(2, 0xFC), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
+
+/* External 32KHz input clock - GPIOE7 */
+ALTERNATE(PIN_MASK(E, 0x80), 1,  MODULE_CLOCK,         0)
diff --git a/board/nefario/usb_pd_policy.c b/board/nefario/usb_pd_policy.c
new file mode 100644
index 0000000000..51a1adec4b
--- /dev/null
+++ b/board/nefario/usb_pd_policy.c
@@ -0,0 +1,409 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "atomic.h"
+#include "charge_manager.h"
+#include "common.h"
+#include "console.h"
+#include "driver/charger/bd9995x.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
+			 PDO_FIXED_COMM_CAP)
+
+const uint32_t pd_src_pdo[] = {
+		PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+const uint32_t pd_src_pdo_max[] = {
+		PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_max_cnt = ARRAY_SIZE(pd_src_pdo_max);
+
+const uint32_t pd_snk_pdo[] = {
+		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+		PDO_BATT(4750, 21000, 15000),
+		PDO_VAR(4750, 21000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+int pd_is_valid_input_voltage(int mv)
+{
+	return 1;
+}
+
+void pd_transition_voltage(int idx)
+{
+	/* No-operation: we are always 5V */
+}
+
+static uint8_t vbus_en[CONFIG_USB_PD_PORT_COUNT];
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_COUNT] = {TYPEC_RP_1A5, TYPEC_RP_1A5};
+
+int board_vbus_source_enabled(int port)
+{
+	return vbus_en[port];
+}
+
+static void board_vbus_update_source_current(int port)
+{
+	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
+	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
+		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
+
+	/*
+	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
+	 * (2x 33k in parallel) on the NX5P3290 load switch ILIM pin,
+	 * setting a minimum OCP current of 3186 mA.
+	 * Putting an internal pull-up on USB_Cx_5V_EN, effectively put a 33k
+	 * resistor on ILIM, setting a minimum OCP current of 1505 mA.
+	 */
+	gpio_set_level(gpio, vbus_en[port]);
+	gpio_set_flags(gpio, flags);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Ensure we're not charging from this port */
+	bd9995x_select_input_port(bd9995x_pd_port_to_chg_port(port), 0);
+
+	/* Ensure we advertise the proper available current quota */
+	charge_manager_source_port(port, 1);
+
+	pd_set_vbus_discharge(port, 0);
+	/* Provide VBUS */
+	vbus_en[port] = 1;
+	board_vbus_update_source_current(port);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = vbus_en[port];
+	/* Disable VBUS */
+	vbus_en[port] = 0;
+	board_vbus_update_source_current(port);
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+	/* Give back the current quota we are no longer using */
+	charge_manager_source_port(port, 0);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+void pd_set_input_current_limit(int port, uint32_t max_ma,
+				uint32_t supply_voltage)
+{
+#ifdef CONFIG_CHARGE_MANAGER
+	struct charge_port_info charge;
+
+	charge.current = max_ma;
+	charge.voltage = supply_voltage;
+	charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge);
+#endif
+}
+
+void typec_set_input_current_limit(int port, uint32_t max_ma,
+				   uint32_t supply_voltage)
+{
+#ifdef CONFIG_CHARGE_MANAGER
+	struct charge_port_info charge;
+
+	charge.current = max_ma;
+	charge.voltage = supply_voltage;
+	charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge);
+#endif
+}
+
+void typec_set_source_current_limit(int port, int rp)
+{
+	vbus_rp[port] = rp;
+
+	/* change the GPIO driving the load switch if needed */
+	board_vbus_update_source_current(port);
+}
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
+int pd_check_power_swap(int port)
+{
+	/*
+	 * Allow power swap as long as we are acting as a dual role device,
+	 * otherwise assume our role is fixed (not in S0 or console command
+	 * to fix our role).
+	 */
+	return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0;
+}
+
+int pd_check_data_swap(int port, int data_role)
+{
+	/* Allow data swap if we are a UFP, otherwise don't allow */
+	return (data_role == PD_ROLE_UFP) ? 1 : 0;
+}
+
+int pd_check_vconn_swap(int port)
+{
+	return gpio_get_level(GPIO_PP5000_EN);
+}
+
+void pd_execute_data_swap(int port, int data_role)
+{
+	/* Do nothing */
+}
+
+void pd_check_pr_role(int port, int pr_role, int flags)
+{
+	/*
+	 * If partner is dual-role power and dualrole toggling is on, consider
+	 * if a power swap is necessary.
+	 */
+	if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
+	    pd_get_dual_role() == PD_DRP_TOGGLE_ON) {
+		/*
+		 * If we are a sink and partner is not externally powered, then
+		 * swap to become a source. If we are source and partner is
+		 * externally powered, swap to become a sink.
+		 */
+		int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER;
+
+		if ((!partner_extpower && pr_role == PD_ROLE_SINK) ||
+		     (partner_extpower && pr_role == PD_ROLE_SOURCE))
+			pd_request_power_swap(port);
+	}
+}
+
+void pd_check_dr_role(int port, int dr_role, int flags)
+{
+	/* If UFP, try to switch to DFP */
+	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
+		pd_request_data_swap(port);
+}
+/* ----------------- Vendor Defined Messages ------------------ */
+const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
+
+int pd_custom_vdm(int port, int cnt, uint32_t *payload,
+		  uint32_t **rpayload)
+{
+	int cmd = PD_VDO_CMD(payload[0]);
+	uint16_t dev_id = 0;
+	int is_rw;
+
+	/* make sure we have some payload */
+	if (cnt == 0)
+		return 0;
+
+	switch (cmd) {
+	case VDO_CMD_VERSION:
+		/* guarantee last byte of payload is null character */
+		*(payload + cnt - 1) = 0;
+		CPRINTF("version: %s\n", (char *)(payload+1));
+		break;
+	case VDO_CMD_READ_INFO:
+	case VDO_CMD_SEND_INFO:
+		/* copy hash */
+		if (cnt == 7) {
+			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
+			is_rw = VDO_INFO_IS_RW(payload[6]);
+
+			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
+				HW_DEV_ID_MAJ(dev_id),
+				HW_DEV_ID_MIN(dev_id),
+				VDO_INFO_SW_DBG_VER(payload[6]),
+				is_rw);
+		} else if (cnt == 6) {
+			/* really old devices don't have last byte */
+			pd_dev_store_rw_hash(port, dev_id, payload + 1,
+					     SYSTEM_IMAGE_UNKNOWN);
+		}
+		break;
+	case VDO_CMD_CURRENT:
+		CPRINTF("Current: %dmA\n", payload[1]);
+		break;
+	case VDO_CMD_FLIP:
+		usb_mux_flip(port);
+		break;
+#ifdef CONFIG_USB_PD_LOGGING
+	case VDO_CMD_GET_LOG:
+		pd_log_recv_vdm(port, cnt, payload);
+		break;
+#endif /* CONFIG_USB_PD_LOGGING */
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+static int dp_flags[CONFIG_USB_PD_PORT_COUNT];
+/* DP Status VDM as returned by UFP */
+static uint32_t dp_status[CONFIG_USB_PD_PORT_COUNT];
+
+static void svdm_safe_dp_mode(int port)
+{
+	/* make DP interface safe until configure */
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+	usb_mux_set(port, TYPEC_MUX_NONE,
+		    USB_SWITCH_CONNECT, pd_get_polarity(port));
+}
+
+static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
+{
+	/* Only enter mode if device is DFP_D capable */
+	if (mode_caps & MODE_DP_SNK) {
+		svdm_safe_dp_mode(port);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int svdm_dp_status(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_STATUS | VDO_OPOS(opos));
+	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				   0, /* HPD level ... not applicable */
+				   0, /* exit DP? ... no */
+				   0, /* usb mode? ... no */
+				   0, /* multi-function ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
+				   0, /* power low? ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)));
+	return 2;
+};
+
+static int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
+
+	if (!pin_mode)
+		return 0;
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
+				1,             /* DPv1.3 signaling */
+				2);            /* UFP connected */
+	return 2;
+};
+
+static void svdm_dp_post_config(int port)
+{
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+}
+
+static int svdm_dp_attention(int port, uint32_t *payload)
+{
+	const struct usb_mux *mux = &usb_muxes[port];
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	int mf_pref = PD_VDO_DPSTS_MF_PREF(payload[1]);
+
+	dp_status[port] = payload[1];
+
+	mux->hpd_update(port, lvl, irq);
+
+	if (lvl)
+		usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP,
+			    USB_SWITCH_CONNECT, pd_get_polarity(port));
+	else
+		usb_mux_set(port, mf_pref ? TYPEC_MUX_USB : TYPEC_MUX_NONE,
+			    USB_SWITCH_CONNECT, pd_get_polarity(port));
+
+	return 1;
+}
+
+static void svdm_exit_dp_mode(int port)
+{
+	const struct usb_mux *mux = &usb_muxes[port];
+
+	svdm_safe_dp_mode(port);
+	mux->hpd_update(port, 0, 0);
+}
+
+static int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
+{
+	/* Always enter GFU mode */
+	return 0;
+}
+
+static void svdm_exit_gfu_mode(int port)
+{
+}
+
+static int svdm_gfu_status(int port, uint32_t *payload)
+{
+	/*
+	 * This is called after enter mode is successful, send unstructured
+	 * VDM to read info.
+	 */
+	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
+	return 0;
+}
+
+static int svdm_gfu_config(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+static int svdm_gfu_attention(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+const struct svdm_amode_fx supported_modes[] = {
+	{
+		.svid = USB_SID_DISPLAYPORT,
+		.enter = &svdm_enter_dp_mode,
+		.status = &svdm_dp_status,
+		.config = &svdm_dp_config,
+		.post_config = &svdm_dp_post_config,
+		.attention = &svdm_dp_attention,
+		.exit = &svdm_exit_dp_mode,
+	},
+	{
+		.svid = USB_VID_GOOGLE,
+		.enter = &svdm_enter_gfu_mode,
+		.status = &svdm_gfu_status,
+		.config = &svdm_gfu_config,
+		.attention = &svdm_gfu_attention,
+		.exit = &svdm_exit_gfu_mode,
+	}
+};
+const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
+